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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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SH7727 group hardware manual 32 users manual rev.6.00 2009.03 renesas 32-bit risc microcomputer superh? risc engine family/ sh7700 series SH7727 hd6417727
rev.6.00 mar. 27, 2009 page ii of lvi rej09b0254-0600 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials
rev.6.00 mar. 27, 2009 page iii of lvi rej09b0254-0600 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are gen erally in the high-impedance state. in operation with an unused pin in the open-circui t state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recogni tion of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from t he moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from t he moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to anothe r, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the sa me group but having different type numbers may differ because of the differences in inte rnal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products.
rev.6.00 mar. 27, 2009 page iv of lvi rej09b0254-0600
rev.6.00 mar. 27, 2009 page v of lvi rej09b0254-0600 preface the SH7727 microproces sor incorporates the 32-bit sh-3 cpu and is also equipped with peripheral functions necessary for configuring a user system. the SH7727 is built in with a variety of peri pheral functions such as cache memory, memory management unit (mmu), interrupt controller, timers, three serial communication interfaces (sci, scif, siof), real-time clock (r tc), user break controller (ubc), bus state controller (bsc) and afe interface. the SH7727 can be used in a va riety of applications that demand a high-speed microcomputer with low power consumption. the descriptions in this manual are based on the SH7727c. for details on using versions previous to the SH7727c please refer to using versions previous to the SH7727c at the end of the manual. note that the version is the SH7727c if ?c? is engraved on the chip and the version is the SH7727b if ?b? is engraved. if there is no such indication the product is a version previous to the SH7727b. (see appendix e.) target readers: this manual is designed for use by people who design application systems using the SH7727. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. purpose: this manual provides the information of the hardware functions and electrical characteristics of the SH7727. the sh-3, sh-3e, sh3-dsp software manual contains detailed information of executable instructions. please read the software manual together with this manual. how to use the book: ? to understand general functions read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions refer to the separate sh-3, sh-3e, sh3-dsp software manual. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are available on our web site. please make sure that you have the latest version. (http://www .renesas.com/)
rev.6.00 mar. 27, 2009 page vi of lvi rej09b0254-0600 ? user manuals for SH7727 name of document document no. SH7727 hardware manual this manual sh-3, sh-3e, sh3-dsp software manual rej09b0317-0400 ? user manuals for development tools name of document document no. superh? risc engine c/c++ compiler, assembler, optimizing linkage editor compiler package v.9.00 user?s manual rej10b0152-0101 superh? risc engine high-performance embedded workshop 3 user?s manual rej10b0025-0200h superh risc engine high-performance embedded workshop 3 tutorial rej10b0023-0200h ? application note name of document document no. superh risc engine c/c++ compiler pa ckage application note rej05b0463-0400
rev.6.00 mar. 27, 2009 page vii of lvi rej09b0254-0600 revisions and additions page previous version revised version 3, 17, 236, 260, 261, 262, 265, 277, 479, 933 crystal oscillator, (a) crystal oscillation, oscillator crystal resonator 9 1.3.1 pin arrangement figure 1.2 pin arrangement (prqp0240kc-b) ras3 /ptj[0] cke/ptk[5] pte[1]/usb2_pwr_en pte[2]/usb1_pwr_en rts2 /usb1d_txenl usb2_ovr_crnt usb1_ovr_crnt /usbf_vbus 129 128 127 126 125 124 123 ras /ptj[0] cke/ptk[5] pte[1]/usb2_pwr_en pte[2]/usb1_pwr_en rts2 /usb1d_txenl usb2_ovr_ current usb1_ovr_ current /usbf_vbus 129 128 127 126 125 124 123 10 figure 1.3 pin arrangement (plbg0240ja-a) pte2 usb1d_ suspend usb2 ovr_crnt usb1 ovr_crnt ptm5 ptm7 ras3 pte1 rts2 ptm4 pte2 usb1d_ suspend usb2_ ovr_ current usb1_ ovr_ current ptm5 ptm7 ras pte1 rts2 ptm4 15, 17, 18 1.3.2 pin functions table 1.2 SH7727 pin function pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name function 123 usb1_ovr_crnt / usbf_vbus i/i usb host 1 overcurrent detection / usb function vbus 124 usb2_ovr_crnt i usb host 2 overcurrent detection 129 ras3 /ptj[0] o/io ras for sdram / i/o port j 179 xtal o clock oscillator 224 scan_testen i test pin (fixed to 3.3 v) i/o w18 v17 w15 v4 g1 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name function 123 usb1_ovr_current / usbf_vbus i/i usb host 1 overcurrent detection / usb function vbus 124 usb2_ovr_current i usb host 2 overcurrent detection 129 ras /ptj[0] o/io ras for sdram / i/o port j 179 xtal o crystal resonator 224 scan_testen i test pin (pull up to vccq) i/o w18 v17 w15 v4 g1 278 10.9 notes on board design when using a pll oscillator circuit: ... in clock mode 7, connect the extal pin to v cc or v ss and leave the xtal pin open. ... in clock mode 7, connect the extal pin to v cc q or v ss q and leave the xtal pin open. 286 12.1.3 pin configuration table 12.1 pin configuration pin name signal i/o description row address strobe 3 ras3 output when synchronous dram is used in area 3, ras3 for 64-mbyte address. column address strobe cas output when synchronous dram is used, cas signal is used for 64-mbyte address. pin name signal i/o description row address strobe ras output when synchronous dram is used, ras signal. column address strobe cas output when synchronous dram is used, cas signal .
rev.6.00 mar. 27, 2009 page viii of lvi rej09b0254-0600 page previous version revised version 323 12.3.2 description of areas area 2: when synchronous dram is connected, the ras3 signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. control of ras3 , cas , data timing, and address multiplexing is set with mcr. when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. control of ras , cas , data timing, and address multiplexing is set with mcr. 12.3.2 description of areas area 3: when synchronous dram is connected, the ras3 signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. 331 12.3.4 synchronous dram interface ras3 ras 332 figure 12.11 example of 64-mbit synchronous dram connection (32-bit bus width) ras3 ras 333 figure 12.12 example of 64-mbit synchronous dram (16-bit bus width) ras3 ras 336 figure 12.13 basic timing for synchronous dram burst read ras3 ras 337 figure 12.14 synchronous dram burst read wait specification timing ras3 ras 338 figure 12.15 basic timing for synchronous dram single read ras3 ras 339 figure 12.16 basic timing for synchronous dram burst write ras3 ras
rev.6.00 mar. 27, 2009 page ix of lvi rej09b0254-0600 page previous version revised version 341 figure 12.17 basic timing for synchronous dram single write ras3 ras 343 figure 12.19 synchronous dram auto- refresh timing ras3 ras 344 figure 12.20 synchronous dram self- refresh timing ras3 ras 346 figure 12.21 synchronous dram mode write timing ras3 ras 379 14.1 overview this chip includes a four-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip supporting modules (siof, scif, usb function, and a/d converter). using the dmac reduces the burden on the cpu and increases overall operating efficiency this chip includes a four-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip supporting modules (siof, scif, usbf, a/d converter, and d/a converter). using the dmac reduces the burden on the cpu and increases overall operating efficiency 441 14.6 usage notes 5. the on-chip supporting modules that the dmac can access are, siof, scif, usb function, a/d converter, and i/o ports. do not access the other on-chip supporting modules by the dmac. 5. the on-chip supporting modules that the dmac can access are, siof, scif, usbf, a/d converter, d/a converter, and i/o ports. do not access the other on-chip supporting modules by the dmac. 459 16.1.3 pin configuration table 16.1 rtc pin configuration notes: 1. when the rtc is not used, set extal2 to pull-up (to vcc) and make no connection for xtal2. notes: 1. when the rtc is not used, set extal2 to pull-up (to vcc-rtc) and make no connection for xtal2. ? section 17 serial communication interface (sci) txd, rxd, sck txd0, rxd0, sck0 ? section 18 smart card interface txd, rxd, sck txd0, rxd0, sck0
rev.6.00 mar. 27, 2009 page x of lvi rej09b0254-0600 page previous version revised version 543 18.1 overview as an additional serial communications interface function (sci), an ic card (smart card) interface that is compatible to the iso/iec standard 7816-3 for identification of cards is supported. ... as an additional serial communications interface function, a smart card (integrated circuit card) interface (sci) that is compatible with the t = 0 data transfer protocol of iso/iec standard 7816-3 (identification card) is supported. ... ? section 19 serial communication interface with fifo (scif) txd/txd, rxd/rxd, cts , rts txd2, rxd2, cts2 , rts2 601 19.5 usage notes 4. sending a break signal: the i/o condition and level of the txd pin are determined scp4dt bit in the port sc data register 2 (scpdr2) and bits scp4md0 and scp4md1 port sc control register 2 (scpcr2). this feature can be used to send a break signal. to send a break signal during serial transmission, clear the cp4dt bit to 0 (designating level), then set the scp4md0 and scp4md1 bits to 0 and 1, respectively, and finally clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd pin. 4. sending a break signal: the i/o condition and level of the txd pin are determined scp4dt bit in the port sc data register 2 (scpdr2) and bits scp4md0 and scp4md1 port sc control register 2 (scpcr2). this feature can be used to send a break signal. to send a break signal during serial transmission, clear the cp4dt bit to 0 (designating level), then set the scp4md0 and scp4md1 bits to 1 and 0, respectively, and finally clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd pin. ? section 20 serial io (siof) siofsyn, siorxd siofsync, rxd_sio 634 20.3.4 register assignment for transfer data note: in figure 20.5, only data portions that are shown by the oblique lines are transmitted or received as effective data. thus, it is necessary to transmit in byte for 8 bit data and in word 16 bit data. the areas without the oblique lines are not the object to transmit or receive. note: in figure 20.5, only data portions that are shown by the oblique lines are transmitted or received as effective data. thus, the areas without the oblique lines are not the object to transmit or receive. 635 table 20.6 transmit data sound mode bit mode tdle tdre tdrep monaural 0 * stereo 1 0 same sound for right and left 1 1 1 1 1 bit mode tdle tdre tlrep monaural 0 * stereo 1 0 same sound for right and left 1 1 1 1 1
rev.6.00 mar. 27, 2009 page xi of lvi rej09b0254-0600 page previous version revised version 641 20.3.7 procedures for transmit or receive (1) transmitting in master figure 20.9 example of transmit operation in master no. time chart setting content of siof 1 start settting of simdr register, simcr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request no. time chart setting content of siof 1 start settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request 642 (2) receiving in master figure 20.10 example of receive operation in master no. time chart setting content of siof 1 start settting of simdr register, simcr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request no. time chart setting content of siof 1 start settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request 643 (3) transmitting in slave figure 20.11 example of transmit operation in slave no. time chart setting content of siof 1 start settting of simdr register, simcr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request no. time chart setting content of siof 1 start settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request 644 (4) receiving in slave figure 20.12 example of receive operation in slave no. time chart setting content of siof 1 start settting of simdr register, simcr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request no. time chart setting content of siof 1 start settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request 650 (5) a case of 16 bits stereo (no.2) figure 20.17 transmit or receive timing (16 bits stereo 2) setting: trmd = 01, redg = 1, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0001, cd0e = 0, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length 64 bits), tdre = 1, tdra3 to tdra0 = 0010, rdre = 1, rdra3 to rdra0 = 0011, cd1e = 0, cd1a3 to cd1a0 = 0000 setting: trmd = 11, redg = 1, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0001, cd0e = 0, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length 64 bits), tdre = 1, tdra3 to tdra0 = 0010, rdre = 1, rdra3 to rdra0 = 0011, cd1e = 0, cd1a3 to cd1a0 = 0000 680 22.1.1 block diagram figure 22.1 block diagram of usb pin multiplexer usb2p, usb2m, usb1p, usb1m usb2_p, usb2_m, usb1_p, usb1_m
rev.6.00 mar. 27, 2009 page xii of lvi rej09b0254-0600 page previous version revised version 681 22.1.2 pin configuration table 22.2 pin configuration (analog transceiver signal) usb1p, usb1m, usb2p, usb2m note: the pins shown in table 22.2 can be used as two-port usb host controller pins, or as one-port usb host controller pins and oneport usb function controller pins. make these pins open, when they are not used. usb1_p, usb1_m, usb2_p, usb2_m note: the pins shown in table 22.2 can be used as two-port usb host controller pins or as one-port usb host controller pins and one-port usb function controller pins. leave these pins open or pull them down when not used. 684 22.3.1 example of the connection between usb function controller and transceiver figure 22.2 example 1 of transceiver connection for usb function controller (on-chip transceiver is used) usb1p, usb1m usb1_p, usb1_m 685 figure 22.3 example 2 of transceiver connection for usb function controller (on-chip transceiver is used) usb1p, usb1m usb1_p, usb1_m 689 22.3.2 example of the connection between usb host controller and transceiver ? by using the usb2_ovr_current , usb2_pwr_en, usb2p, and usb2m pins in an external circuit similar to that in figure 22.6, you can also use built-in usb transceiver 2. ? description amended ? by using the usb2_ovr_current , usb2_pwr_en, usb2_p, and usb2_m pins in an external circuit similar to that in figure 22.6, you can also use built-in usb transceiver 2. ? 689 figure 22.6 example 1 of transceiver connection for usb host controller (on-chip transceiver is used) usb1p, usb1m usb1_p, usb1_m 725 24.1 general description it is necessary to refer open hci specification to develop drivers for this usb host controller and hardware. description amended it is necessary to refer open hci specification to develop drivers for this usb host controller and hardware. also refer to the restrictions on the use of the module listed at the end of this section. 726 24.1.2 pin configuration table 24.1 pin configuration usb1p, usb1m, usb2p, usb2m usb1_p, usb1_m, usb2_p, usb2_m
rev.6.00 mar. 27, 2009 page xiii of lvi rej09b0254-0600 page previous version revised version 759 24.5.1 restriction of the data size in in transfer when a data packet shorter than maxpacketsize (short packet) is transferred in the in data transfer other than the isochronous transfer, following usages are restricted. 2. ?be sure to transfer maxpacketsize mainly and the processed data will be used so that the end of the data or head can be recognized when a short packet is sent. when a data packet shorter than maxpacketsize (short packet) is transferred in the in data transfer , following usages are restricted. 2. ?be sure to transfer maxpacketsize mainly and the processed data will be used so that the end of the data or head can be recognized when a short packet is sent. in applications where the receive data size cannot be controlled by software, it is not possible to use software to remove the 1 byte of unnecessary data. when using the module in such cases, appropriate countermeasures must be considered. 761 24.8 usage notes of resume operation of usb host controller (usbh) newly added 816 25.4 clock and lcd data signal examples figure 25.19 "clock and lcd data signal example" deleted 819 25.5 usage notes note 2 newly added 824 26.1 overview table 26.1 list of multiplexed pins ras3 ras 885 30.1.1 features newly added ? when the pcc is enabled (p0use bit in pcc0gcr set to 1), pcc0wait functions as a wait signal in the same manner as wait . 890 30.1.4 pcmcia support figures 30.3 and 30.4 show the relationship between the memory space of the SH7727 and the memory and i/o spaces of the pc card in the continuous 16-mb area mode. although memory space and i/o space are supported in area 6. figure 30.3 shows the relationship between the memory space of the SH7727 and the memory and i/o spaces of the pc card in the continuous 16-mb area mode. although memory space and i/o space are supported in area 6.
rev.6.00 mar. 27, 2009 page xiv of lvi rej09b0254-0600 page previous version revised version 898 30.2.3 area 6 card status change register (pcc0cscr) bit 4?pcc0 status change (p0sc): indicates a change in the value of the stschg pin of the pc card when the pc card connected to area 6 is the i/o card interface type. when the stschg pin is changed from 1 to 0, the sc bit is set to 1. bit 4?pcc0 status change (p0sc): indicates a change in the value of the stschg pin of the pc card when the pc card connected to area 6 is the i/o card interface type. when the stschg pin is changed from 1 to 0, the p0sc bit is set to 1. 922, 923 31.3.3 boundary-scan register (sdbsr) table 31.3 correspondence between SH7727 pins and boundary-scan register bit pin name i/o 167 usb1_ovr_crnt /usbf_vbus 166 usb2_ovr_crnt in 165 rts2 /usb1d_txenl 164 pte2/usb1_pwr_en in 163 pte1/usb2_pwr_en in 162 cke/ptk5 in 161 ras3 /ptj0 bit pin name i/o r 132 pte1/usb2_pw _en out 131 cke/ptk5 out 0 103 ras3 /ptj0 in control in 130 ras3 /ptj out in bit pin name i/o 167 usb1_ovr_current /usbf_vbus in 166 usb2_ovr_current in 165 rts2 /usb1d_txenl 164 pte2/usb1_pwr_en in 163 pte1/usb2_pwr_en in 162 cke/ptk5 in 161 ras /ptj0 bit pin name i/o r 132 pte1/usb2_pw _en out 131 cke/ptk5 out 0 103 ras /ptj0 in control in 130 ras /ptj out 933 32.2 dc characteristics table 32.2 dc characteristics (2) item symbol min typ max unit measurement conditions resetp , resetm , nmi, irq5 to irq0, md5 to md0, irl3 to irl0 , pint15 to pint0, asemd0 , adtrg , trst , extal, ckio, ca v cc q 0.9 ? v cc q + 0.3 extal2 ? ? ? connect to vcc when crystal oscillator is connected port l 2.0 ? av cc + 0.3 input high voltage other input pins v ih 2.0 v cc q + 0.3 v ? item symbol min typ max unit measurement conditions resetp , resetm , nmi, irq5 to irq0, md5 to md0, irl3 to irl0 , pint15 to pint0, asemd0 , adtrg , trst , extal, ckio, ca v cc q 0.9 ? v cc q + 0.3 extal2 ? ? ? connect to vcc-rtc when no crystal resonator is connected port l 2.0 ? av cc + 0.3 input high voltage other input pins v ih 2.0 v cc q + 0.3 v ? 965 32.3.6 synchronous dram timing figure 32.31 synchronous dram auto- refresh cycle (tras = 1, tpc = 1) ras3 ras 966 figure 32.32 synchronous dram self- refresh cycle (tpc = 0) ras3 ras 967 figure 32.33 synchronous dram mode register write cycle casxx cas
rev.6.00 mar. 27, 2009 page xv of lvi rej09b0254-0600 page previous version revised version 985 32.3.12 usb module signal timing table 32.15 usb module signal timing item symbol min max unit figure uclk external input clock frequency (48 mhz) t freq 47.9 48.1 mhz 32.58 clock rise time t r48 ? 6 ns clock fall time t f48 ? 6 ns item symbol min max unit figure uclk external input clock frequency (48 mhz) (when using usb function controller) t freq 47.9 48.1 mhz 32.58 uclk external input clock frequency (48 mhz) (when using usb host controller) 47.976 48.024 clock rise time t r48 ? 6 ns clock fall time t f48 ? 6 ns 989 32.3.14 ac characteristics measurement conditions figure 32.60 output load circuit notes: 1. c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pf: ckio, rasxx , casxx , cs0 , cs2 to cs6 , ce2a , ce2b , back note amended notes: 1. c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pf: ckio, ras , cas , cs0 , cs2 to cs6 , ce2a , ce2b , back 994, 996 a.1 pin functions table a.1 pin functions type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges bus functions ra r a s3 s 3 /ptj[0], reserved /ptj[1], reserved /ptj[3] * 3 , reserved /ptj[4] * 3 , reserved /ptj[5] * 3 129, 130, 133, 135, 136 o/io h o/p z(h)/k z(h)/p usb related us u s b1_o b 1 _ o vr_ v r _ c rnt r n t / usbf_vbus 123 i z/z z/z i/i us u s b2_o b 2 _ o vr_ v r _ c rnt r n t 124 i i z z i i/i type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges bus functions ra r a s / ptj[0], reserved /ptj[1], reserved /ptj[3] * 3 , reserved /ptj[4] * 3 , reserved /ptj[5] * 3 129, 130, 133, 135, 136 o/io h o/p z(h)/k z(h)/p usb related us u s b1_o b 1 _ o vr_ v r _ c urrent u r r e n t / usbf_vbus 123 i z/z z/z i/i us u s b2_o b 2 _ o vr_ v r _ c urrent u r r e n t 124 i i z z i i/i 999, 1000, 1002 a.2 treatment of unused pins table a.2 treatment of unused pins type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used xtal2 2 o open extal2 3 a2 i connect to vcc clock and oscillation related ra r a s3 s 3 /ptj[0], reserved /ptj[1], reserved /ptj[3], reserved /ptj[4], reserved /ptj[5] 129, 130, 133, 135, 136 w15, t16, w14, u14, t14 o/io open us u s b1_o b 1 _ o vr_ v r _ c rnt r n t /usbf_vbus 123 i/i pull up us u s b2_o b 2 _ o vr_ v r _ c rnt r n t 124 v17 i pull up usb related b4 bus functions w18 usb1_p(analog), usb1_m(analog), usb2_p(analog), usb2_m(analog) 226, 227, 229, 230 f3, f2, e4, e3 io open * 2 type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used xtal2 2 o open extal2 3 a2 i pull up (vcc- rtc) clock and oscillation related ra r a s /ptj[0], reserved /ptj[1], reserved /ptj[3], reserved /ptj[4], reserved /ptj[5] 129, 130, 133, 135, 136 w15, t16, w14, u14, t14 o/io open us u s b1_o b 1 _ o vr_ v r _ c urrent u r r e n t / usbf_vbus 123 i/i pull up us u s b2_o b 2 _ o vr_ v r _ c urrent u r r e n t 124 v17 i pull up usb related b4 bus functions w18 usb1_p(analog), usb1_m(analog), usb2_p(analog), usb2_m(analog) 226, 227, 229, 230 f3, f2, e4, e3 io open * 2 or pull down 1004, 1005 a.3 pin status when accessing address spaces table a.3 pin status (normal memory/little endian) ras3 ras 1006, 1007 table a.4 pin status (normal memory/big endian) ras3 ras
rev.6.00 mar. 27, 2009 page xvi of lvi rej09b0254-0600 page previous version revised version 1008, 1009 table a.5 pin status (burst rom/little endian) ras3 ras 1010, 1011 table a.6 pin status (burst rom/big endian) ras3l ras3 ras ras 1012 table a.7 pin status (synchronous dram/little endian) ras3 ras 1013 table a.8 pin status (synchronous dram/big endian) ras3 ras 1014, 1015 table a.9 pin status (pcmcia/little endian) ras3 ras 1016, 1017 table a.10 pin status (pcmcia/big endian) ras3 ras all trademarks and registered trademarks are the property of their respective owners.
rev.6.00 mar. 27, 2009 page xvii of lvi rej09b0254-0600 contents section 1 overview and pin functions ......................................................................... 1 1.1 features....................................................................................................................... ...... 1 1.2 block diagram .................................................................................................................. 8 1.3 pin description................................................................................................................ .. 9 1.3.1 pin arrangement .................................................................................................. 9 1.3.2 pin functions ....................................................................................................... 11 section 2 cpu ...................................................................................................................... 21 2.1 registers...................................................................................................................... ...... 21 2.1.1 general purpose registers ................................................................................... 25 2.1.2 control registers ................................................................................................. 27 2.1.3 system registers.................................................................................................. 31 2.1.4 dsp registers ...................................................................................................... 31 2.2 data format .................................................................................................................... .. 38 2.2.1 data format in register s (non-dsp type) ......................................................... 38 2.2.2 dsp-type data format........................................................................................ 38 2.2.3 data format in memory....................................................................................... 40 2.3 features of cpu core instructions ................................................................................... 40 2.4 instruction formats ........................................................................................................... 44 2.4.1 cpu instruction addr essing modes .................................................................... 44 2.4.2 dsp data addressing .......................................................................................... 48 2.4.3 cpu instruction formats ..................................................................................... 54 2.4.4 dsp instruction formats...................................................................................... 58 2.5 instruction set ................................................................................................................ ... 64 2.5.1 cpu instruction set ............................................................................................. 64 2.6 dsp extended-functio n instructions ................................................................................ 79 2.6.1 introductio n.......................................................................................................... 79 2.6.2 added cpu system cont rol instructions ............................................................ 80 2.6.3 single and double data transfer for dsp data instructions............................... 82 2.6.4 dsp operation inst ruction set............................................................................. 85 section 3 memory management unit (mmu) ........................................................... 97 3.1 overview....................................................................................................................... .... 97 3.1.1 features................................................................................................................ 97 3.1.2 role of mmu....................................................................................................... 97 3.1.3 SH7727 mmu ..................................................................................................... 99 3.1.4 register config uration......................................................................................... 103 3.2 register desc ription.......................................................................................................... 103 3.3 tlb functions .................................................................................................................. 105
rev.6.00 mar. 27, 2009 page xviii of lvi rej09b0254-0600 3.3.1 configuration of the tlb .................................................................................... 105 3.3.2 tlb indexing....................................................................................................... 107 3.3.3 tlb address comparison ................................................................................... 108 3.3.4 page management in formation............................................................................ 110 3.4 mmu functions................................................................................................................ 1 11 3.4.1 mmu hardware management ............................................................................. 111 3.4.2 mmu software management .............................................................................. 111 3.4.3 mmu instruction (ldtlb)................................................................................. 112 3.4.4 avoiding synonym problems .............................................................................. 113 3.5 mmu exceptions.............................................................................................................. 11 6 3.5.1 tlb miss excep tion ............................................................................................ 116 3.5.2 tlb protection viola tion exceptio n ................................................................... 117 3.5.3 tlb invalid ex ception ........................................................................................ 118 3.5.4 initial page write exception ................................................................................ 119 3.5.5 processing flow in event of mmu exception (same processing flow for address error) ................................................................................................ 121 3.5.6 mmu exception in re peat loop......................................................................... 123 3.6 memory-mappe d tlb...................................................................................................... 124 3.6.1 address array ...................................................................................................... 125 3.6.2 data array............................................................................................................ 125 3.6.3 usage examples................................................................................................... 127 3.7 usage notes .................................................................................................................... .. 128 section 4 exception handling ......................................................................................... 131 4.1 overview....................................................................................................................... .... 131 4.1.1 features................................................................................................................ 131 4.1.2 register config uration......................................................................................... 131 4.2 exception handling function ........................................................................................... 131 4.2.1 exception handlin g flow .................................................................................... 131 4.2.2 exception handling vect or addresses ................................................................ 132 4.2.3 acceptance of ex ceptions.................................................................................... 134 4.2.4 exception c odes .................................................................................................. 136 4.2.5 exception reques t masks .................................................................................... 137 4.2.6 returning from excep tion handling.................................................................... 138 4.3 register desc ription.......................................................................................................... 138 4.4 exception handling operation.......................................................................................... 139 4.4.1 reset .................................................................................................................... 139 4.4.2 interrupts.............................................................................................................. 139 4.4.3 general exceptions .............................................................................................. 140 4.5 individual exception operations....................................................................................... 140 4.5.1 resets ................................................................................................................... 140
rev.6.00 mar. 27, 2009 page xix of lvi rej09b0254-0600 4.5.2 general exceptions .............................................................................................. 141 4.5.3 interrupts.............................................................................................................. 146 4.6 usage notes .................................................................................................................... .. 147 section 5 cache .................................................................................................................... 149 5.1 overview....................................................................................................................... .... 149 5.1.1 features................................................................................................................ 149 5.1.2 cache structure.................................................................................................... 149 5.1.3 register config uration......................................................................................... 151 5.2 register desc ription.......................................................................................................... 151 5.2.1 cache control regist er (ccr) ............................................................................ 151 5.2.2 cache control regist er 2 (ccr2) ....................................................................... 152 5.3 cache operation................................................................................................................ 154 5.3.1 searching the cache............................................................................................. 154 5.3.2 read acces s......................................................................................................... 156 5.3.3 prefetch operations.............................................................................................. 156 5.3.4 write acces s ........................................................................................................ 156 5.3.5 write-back buffer ............................................................................................... 157 5.3.6 coherency of cache and external memory ......................................................... 157 5.4 memory-mapped cache ................................................................................................... 157 5.4.1 address array ...................................................................................................... 157 5.4.2 data array............................................................................................................ 158 5.5 usage examples................................................................................................................ 160 5.5.1 invalidating specifi c entries................................................................................ 160 5.5.2 reading the data of a specific entry................................................................... 160 section 6 x/y memory ...................................................................................................... 161 6.1 overview....................................................................................................................... .... 161 6.1.1 features................................................................................................................ 161 6.2 x/y memory access fr om the cpu ................................................................................. 162 6.3 x/y memory access from the dsp.................................................................................. 164 6.4 x/y memory access fr om the dmac ............................................................................. 164 section 7 interrupt controller (intc) ........................................................................... 165 7.1 overview....................................................................................................................... .... 165 7.1.1 features................................................................................................................ 165 7.1.2 block diagra m..................................................................................................... 166 7.1.3 pin configuration................................................................................................. 167 7.1.4 register config uration......................................................................................... 167 7.2 interrupt sources .............................................................................................................. . 169 7.2.1 nmi interrup ts ..................................................................................................... 169
rev.6.00 mar. 27, 2009 page xx of lvi rej09b0254-0600 7.2.2 irq interrupt........................................................................................................ 169 7.2.3 irl interrup ts ...................................................................................................... 170 7.2.4 pint interrupt...................................................................................................... 172 7.2.5 on-chip supporting modu le interrupts ............................................................... 172 7.2.6 interrupt exception hand ling and prio rity........................................................... 173 7.3 intc regi sters ................................................................................................................. 179 7.3.1 interrupt priority registers a to g (ipra to iprg) ............................................ 179 7.3.2 interrupt control regi ster 0 (icr0 )..................................................................... 180 7.3.3 interrupt control regi ster 1 (icr1 )..................................................................... 181 7.3.4 interrupt control regi ster 2 (icr2 )..................................................................... 184 7.3.5 interrupt control regi ster 3 (icr3 )..................................................................... 185 7.3.6 pint interrupt enable register (pinter).......................................................... 187 7.3.7 interrupt request regi ster 0 (irr0) .................................................................... 187 7.3.8 interrupt request regi ster 1 (irr1) .................................................................... 190 7.3.9 interrupt request regi ster 2 (irr2) .................................................................... 191 7.3.10 interrupt request regi ster 3 (irr3) .................................................................... 192 7.3.11 interrupt request regi ster 4 (irr4) .................................................................... 195 7.4 intc operation ................................................................................................................ 197 7.4.1 interrupt sequence ............................................................................................... 197 7.4.2 multiple interr upts ............................................................................................... 199 7.5 interrupt response time ................................................................................................... 199 section 8 user break controller ..................................................................................... 203 8.1 overview....................................................................................................................... .... 203 8.1.1 features................................................................................................................ 203 8.1.2 block diagra m..................................................................................................... 204 8.1.3 register config uration......................................................................................... 205 8.2 register desc riptions ........................................................................................................ 2 06 8.2.1 break address regist er a (bara) ..................................................................... 206 8.2.2 break address mask regi ster a (bamra)........................................................ 206 8.2.3 break bus cycle regist er a (bbra).................................................................. 207 8.2.4 break address regist er b (ba rb)...................................................................... 209 8.2.5 break address mask regi ster b (bam rb) ........................................................ 210 8.2.6 break data register b (bdrb) ........................................................................... 211 8.2.7 break data mask regi ster b (bdm rb).............................................................. 212 8.2.8 break bus cycle regi ster b ( bbrb) .................................................................. 213 8.2.9 break control regist er (brcr) .......................................................................... 215 8.2.10 execution times break re gister (betr)............................................................ 218 8.2.11 branch source regi ster (brs r).......................................................................... 219 8.2.12 branch destination re gister (brdr).................................................................. 220 8.2.13 break asid register a (basra)....................................................................... 221
rev.6.00 mar. 27, 2009 page xxi of lvi rej09b0254-0600 8.2.14 break asid register b (basrb) ....................................................................... 221 8.3 operation desc ription ....................................................................................................... 22 2 8.3.1 flow of the user break operation ....................................................................... 222 8.3.2 break on instruction fetch cycle......................................................................... 222 8.3.3 break by data a ccess cycle ................................................................................ 223 8.3.4 break on x/y-memory bus cycl e....................................................................... 224 8.3.5 sequential br eak .................................................................................................. 224 8.3.6 value of saved progr am counter ........................................................................ 224 8.3.7 pc trace .............................................................................................................. 225 8.3.8 usage examples................................................................................................... 227 8.3.9 usage note s ......................................................................................................... 231 section 9 power-down modes and software reset .................................................. 233 9.1 overview....................................................................................................................... .... 233 9.1.1 power-down m odes ............................................................................................ 233 9.1.2 pin configuration................................................................................................. 235 9.1.3 register config uration......................................................................................... 235 9.2 register desc ription.......................................................................................................... 236 9.2.1 standby control regi ster (st bcr)..................................................................... 236 9.2.2 standby control regist er 2 (stbcr2 )................................................................ 237 9.2.3 standby control regist er 3 (stbcr3 )................................................................ 239 9.2.4 module software reset re gister (srstr)......................................................... 241 9.3 sleep mode ..................................................................................................................... .. 243 9.3.1 transition to sl eep mode..................................................................................... 243 9.3.2 canceling slee p mode ......................................................................................... 243 9.4 standby mode ................................................................................................................... 243 9.4.1 transition to stan dby mode................................................................................. 243 9.4.2 canceling standby mode..................................................................................... 245 9.4.3 clock pause function .......................................................................................... 246 9.5 module standby fu nction................................................................................................. 247 9.5.1 transition to module standby functio n .............................................................. 247 9.5.2 clearing the module st andby functio n ............................................................... 249 9.6 timing of status pin changes ..................................................................................... 249 9.6.1 timing for resets................................................................................................. 249 9.6.2 timing for cancelin g standbys ........................................................................... 250 9.6.3 timing for canceling sleep mode....................................................................... 252 9.7 hardware standby mode .................................................................................................. 254 9.7.1 transition to hardware standby mo de ................................................................ 254 9.7.2 clearing the hardware standby mo de................................................................. 254 9.7.3 timing of hardware standby mode .................................................................... 255
rev.6.00 mar. 27, 2009 page xxii of lvi rej09b0254-0600 section 10 on-chip oscillation circuits ...................................................................... 257 10.1 overview....................................................................................................................... .... 257 10.1.1 features................................................................................................................ 257 10.2 overview of th e cpg........................................................................................................ 259 10.2.1 cpg block diagram ............................................................................................ 259 10.2.2 cpg pin configuration ........................................................................................ 261 10.2.3 cpg register conf iguration ................................................................................ 261 10.3 clock operating modes .................................................................................................... 262 10.4 register desc riptions ........................................................................................................ 2 67 10.4.1 frequency control regi ster (frqcr)................................................................. 267 10.4.2 ckio2 control regist er (ckio2cr).................................................................. 269 10.5 changing the frequency ................................................................................................... 270 10.5.1 changing the multipli cation rate ........................................................................ 270 10.5.2 changing the divi sion ratio ................................................................................ 270 10.6 overview of the wdt....................................................................................................... 271 10.6.1 block diagram of the wdt................................................................................. 271 10.6.2 register config urations ....................................................................................... 272 10.7 wdt regi sters.................................................................................................................. 272 10.7.1 watchdog timer coun ter (wtcnt)................................................................... 272 10.7.2 watchdog timer control/statu s register (w tcsr)........................................... 273 10.7.3 notes on register access..................................................................................... 275 10.8 using the wdt ................................................................................................................. 275 10.8.1 canceling standby mode..................................................................................... 275 10.8.2 changing the frequency ...................................................................................... 276 10.8.3 using watchdog ti mer mode.............................................................................. 276 10.8.4 using interval timer mode.................................................................................. 277 10.9 notes on board design ..................................................................................................... 277 section 11 extend clock pulse generator for usb (excpg) .............................. 279 11.1 overview....................................................................................................................... .... 279 11.1.1 excpg ................................................................................................................ 279 11.2 functio ns...................................................................................................................... ..... 279 11.2.1 block diagra m..................................................................................................... 279 11.2.2 pin configuration................................................................................................. 280 11.2.3 register config uration......................................................................................... 280 11.3 register desc riptions ........................................................................................................ 2 80 11.3.1 excpg control register (excpgcr) ............................................................... 280 11.4 usage notes .................................................................................................................... .. 281
rev.6.00 mar. 27, 2009 page xxiii of lvi rej09b0254-0600 section 12 bus state controller (bsc) ......................................................................... 283 12.1 overview....................................................................................................................... .... 283 12.1.1 features................................................................................................................ 283 12.1.2 block diagra m..................................................................................................... 285 12.1.3 pin configuration................................................................................................. 286 12.1.4 register config uration......................................................................................... 287 12.1.5 area overview..................................................................................................... 288 12.1.6 pc card support .................................................................................................. 292 12.2 bsc regi sters .................................................................................................................. . 293 12.2.1 bus control register 1 (bcr1) ........................................................................... 293 12.2.2 bus control register 2 (bcr2) ........................................................................... 297 12.2.3 wait state control regi ster 1 (wcr1)................................................................ 298 12.2.4 wait state control regi ster 2 (wcr2)................................................................ 299 12.2.5 individual memory control register (m cr)....................................................... 303 12.2.6 pcmcia control regi ster (pcr)........................................................................ 306 12.2.7 synchronous dram mode register (s dmr) .................................................... 310 12.2.8 refresh timer control/status register (rtcsr)................................................ 311 12.2.9 refresh timer counte r (rtcnt)........................................................................ 313 12.2.10 refresh time constant re gister (rtcor) ......................................................... 314 12.2.11 refresh count regist er (rfcr) .......................................................................... 314 12.2.12 cautions on accessing refresh c ontrol related registers.................................. 315 12.3 bsc oper ation .................................................................................................................. 316 12.3.1 endian/access size and da ta alignment............................................................. 316 12.3.2 description of areas ............................................................................................ 322 12.3.3 basic interf ace ..................................................................................................... 325 12.3.4 synchronous dram interface............................................................................. 331 12.3.5 burst rom interface............................................................................................ 347 12.3.6 pcmcia interface ............................................................................................... 350 12.3.7 waits between acces s cycles .............................................................................. 362 12.3.8 bus arbitration .................................................................................................... 363 12.3.9 bus pull-up.......................................................................................................... 364 section 13 li bus st ate controller (lbsc) ................................................................. 367 13.1 overview....................................................................................................................... .... 367 13.1.1 features................................................................................................................ 367 13.1.2 register config uration......................................................................................... 367 13.1.3 bus control register 1 (bcr1) ........................................................................... 368 13.1.4 bus control register 2 (bcr2) ........................................................................... 370 13.1.5 wait state control regi ster 1 (wcr1)................................................................ 371 13.1.6 wait state control regi ster 2 (wcr2)................................................................ 372 13.1.7 individual memory control register (m cr)....................................................... 373
rev.6.00 mar. 27, 2009 page xxiv of lvi rej09b0254-0600 13.2 lbsc operation................................................................................................................ 376 13.2.1 bus sharing arch itecture ..................................................................................... 376 13.2.2 usable system memory ....................................................................................... 376 13.2.3 bus arbitration .................................................................................................... 376 13.2.4 lcdc li bus access........................................................................................... 376 13.2.5 usbh li bus access........................................................................................... 377 13.2.6 setting of dma transfer with bus arbitration of other module........................ 377 section 14 direct memory access controller (dmac) .......................................... 379 14.1 overview....................................................................................................................... .... 379 14.1.1 features................................................................................................................ 379 14.1.2 block diagra m..................................................................................................... 381 14.1.3 pin configuration................................................................................................. 382 14.1.4 register config uration......................................................................................... 382 14.2 register desc riptions ........................................................................................................ 3 84 14.2.1 dma source address registers 0 to 3 (sar0 to sar3) .................................... 384 14.2.2 dma destination address register s 0 to 3 (dar0 to dar3)............................ 385 14.2.3 dma transfer count registers 0 to 3 (dmatcr0 to dmatcr3) .................. 386 14.2.4 dma channel control registers 0 to 3 (chcr0 to chcr3)............................. 387 14.2.5 dma channel request assign register (chrar) ............................................ 394 14.2.6 dma operation regist er (dmaor)................................................................... 396 14.3 operation...................................................................................................................... ..... 398 14.3.1 dma transfer flow ............................................................................................ 398 14.3.2 dma transfer re quests ...................................................................................... 400 14.3.3 channel prio rity ................................................................................................... 402 14.3.4 dma transfer types........................................................................................... 405 14.3.5 number of bus cycle states and dreq pin sampling timing .......................... 418 14.3.6 source address relo ad function......................................................................... 427 14.3.7 dma transfer ending ......................................................................................... 429 14.4 compare-match time r (cmt) ......................................................................................... 431 14.4.1 overview.............................................................................................................. 431 14.4.2 register descri ptions ........................................................................................... 432 14.4.3 operation ............................................................................................................. 435 14.4.4 compare-match ................................................................................................... 436 14.5 examples for use.............................................................................................................. 438 14.5.1 example of dma transfer between a/ d converter and external memory (address reload on) ............................................................................................ 438 14.5.2 example of dma transfer between exte rnal memory and scif transmitter (indirect address on) ........................................................................................... 439 14.6 usage notes .................................................................................................................... .. 441
rev.6.00 mar. 27, 2009 page xxv of lvi rej09b0254-0600 section 15 timer (tmu) ................................................................................................... 443 15.1 overview....................................................................................................................... .... 443 15.1.1 features................................................................................................................ 443 15.1.2 block diagra m..................................................................................................... 444 15.1.3 register config uration......................................................................................... 445 15.2 tmu regi sters.................................................................................................................. 446 15.2.1 timer start regist er (tstr)................................................................................ 446 15.2.2 timer control regi ster (tcr)............................................................................. 447 15.2.3 timer constant regi ster (tcor) ........................................................................ 448 15.2.4 timer counters (tcnt) ...................................................................................... 449 15.3 tmu operation................................................................................................................. 451 15.3.1 overview.............................................................................................................. 451 15.3.2 basic functio ns.................................................................................................... 451 15.4 interrupts ..................................................................................................................... ...... 453 15.4.1 status flag se t timing......................................................................................... 453 15.4.2 status flag clear timing ..................................................................................... 454 15.4.3 interrupt sources an d priorities............................................................................ 454 15.5 usage notes .................................................................................................................... .. 455 15.5.1 writing to regi sters ............................................................................................. 455 15.5.2 reading registers ................................................................................................ 455 section 16 realtime clock (rtc) .................................................................................. 457 16.1 overview....................................................................................................................... .... 457 16.1.1 features................................................................................................................ 457 16.1.2 block diagra m..................................................................................................... 458 16.1.3 pin configuration................................................................................................. 459 16.1.4 rtc register conf iguration ................................................................................ 460 16.2 register desc riptions ........................................................................................................ 4 61 16.2.1 64-hz counter (r 64cnt) ................................................................................... 461 16.2.2 second counter (rseccnt) .............................................................................. 461 16.2.3 minute counter (r mincnt) .............................................................................. 462 16.2.4 hour counter (rhrcnt).................................................................................... 462 16.2.5 day of the week counter (rwkcnt)................................................................ 463 16.2.6 date counter (rdaycnt) ................................................................................. 464 16.2.7 month counter (r moncnt) ............................................................................. 464 16.2.8 year counter (ryrcnt) .................................................................................... 465 16.2.9 second alarm regist er (rsecar) ..................................................................... 465 16.2.10 minute alarm register (rminar) ..................................................................... 466 16.2.11 hour alarm register (rhrar) .......................................................................... 466 16.2.12 day of the week alarm re gister (rwkar)....................................................... 467 16.2.13 date alarm register (rdayar) ........................................................................ 467
rev.6.00 mar. 27, 2009 page xxvi of lvi rej09b0254-0600 16.2.14 month alarm register (rmonar) .................................................................... 468 16.2.15 rtc control register 1 (rcr1).......................................................................... 469 16.2.16 rtc control register 2 (rcr2).......................................................................... 470 16.3 rtc oper ation.................................................................................................................. 473 16.3.1 initial settings of register s after powe r-on ........................................................ 473 16.3.2 setting the time................................................................................................... 473 16.3.3 reading the time................................................................................................. 475 16.3.4 alarm function .................................................................................................... 476 16.3.5 crystal oscillator circuit ..................................................................................... 477 16.4 usage notes .................................................................................................................... .. 478 16.4.1 writing registers during rt c count operation................................................. 478 16.4.2 rtc periodic in terrupts ....................................................................................... 478 16.4.3 using the adj bit in the real time clock (rtc) .............................................. 479 section 17 serial co mmunication interface (sci) .................................................... 481 17.1 overview....................................................................................................................... .... 481 17.1.1 features................................................................................................................ 481 17.1.2 block diagra m..................................................................................................... 482 17.1.3 pin configuration................................................................................................. 485 17.1.4 register config uration......................................................................................... 486 17.2 register desc riptions ........................................................................................................ 4 87 17.2.1 receive shift regist er (scrsr) .......................................................................... 487 17.2.2 receive data regist er (scrdr) ......................................................................... 487 17.2.3 transmit shift regist er (sctsr) ........................................................................ 488 17.2.4 transmit data regist er (sctdr)........................................................................ 488 17.2.5 serial mode regist er (scsmr)........................................................................... 489 17.2.6 serial control regi ster (scs cr)......................................................................... 491 17.2.7 serial status regist er (scssr)............................................................................ 495 17.2.8 port sc control register (scpcr)/por t sc data register (scpdr) ................. 499 17.2.9 bit rate regist er (scbrr) .................................................................................. 500 17.3 operation...................................................................................................................... ..... 509 17.3.1 overview.............................................................................................................. 509 17.3.2 operation in asynch ronous mode ....................................................................... 511 17.3.3 multiprocessor comm unication........................................................................... 521 17.3.4 clock synchronous operation ............................................................................. 529 17.4 sci interrupt sources........................................................................................................ 5 38 17.5 usage notes .................................................................................................................... .. 539 section 18 smart card interface ..................................................................................... 543 18.1 overview....................................................................................................................... .... 543 18.1.1 features................................................................................................................ 543
rev.6.00 mar. 27, 2009 page xxvii of lvi rej09b0254-0600 18.1.2 block diagra m..................................................................................................... 544 18.1.3 pin configuration................................................................................................. 545 18.1.4 register config uration......................................................................................... 545 18.2 register desc riptions ........................................................................................................ 5 46 18.2.1 smart card mode regi ster (scscm r) ............................................................... 546 18.2.2 serial status regist er (scssr)............................................................................ 547 18.3 operation...................................................................................................................... ..... 548 18.3.1 overview.............................................................................................................. 548 18.3.2 pin connections ................................................................................................... 549 18.3.3 data format ......................................................................................................... 549 18.3.4 register se ttings .................................................................................................. 551 18.3.5 clock.................................................................................................................... 552 18.3.6 data transmission an d receptio n........................................................................ 555 18.4 usage notes .................................................................................................................... .. 561 18.4.1 receive data timing and receive marg in in asynchronous mode.................... 561 18.4.2 retransmission (receive a nd transmit m odes)................................................... 563 section 19 serial communica tion interface with fifo (scif) ............................. 565 19.1 overview....................................................................................................................... .... 565 19.1.1 features................................................................................................................ 565 19.1.2 block diagra m..................................................................................................... 566 19.1.3 pin configuration................................................................................................. 568 19.1.4 register config uration......................................................................................... 569 19.2 register desc riptions ........................................................................................................ 5 70 19.2.1 receive shift register 2 (scrsr2)..................................................................... 570 19.2.2 receive fifo data regist er 2 (scfrdr2) ........................................................ 570 19.2.3 transmit shift regist er 2 (sctsr2) ................................................................... 571 19.2.4 transmit fifo data regi ster 2 (scftdr2) ....................................................... 571 19.2.5 serial mode register 2 (scsmr2)...................................................................... 572 19.2.6 serial control regist er 2 (scscr2).................................................................... 574 19.2.7 serial status regist er 2 (scssr2)....................................................................... 576 19.2.8 bit rate register 2 (scbrr2) ............................................................................. 580 19.2.9 fifo control register 2 (scfcr2) .................................................................... 586 19.2.10 fifo data count set regi ster 2 (scfdr2) ........................................................ 588 19.3 operation...................................................................................................................... ..... 589 19.3.1 overview.............................................................................................................. 589 19.3.2 serial operation ................................................................................................... 590 19.4 scif inte rrupts................................................................................................................ .. 600 19.5 usage notes .................................................................................................................... .. 601
rev.6.00 mar. 27, 2009 page xxviii of lvi rej09b0254-0600 section 20 serial io (siof) ............................................................................................. 605 20.1 overview....................................................................................................................... .... 605 20.1.1 features................................................................................................................ 605 20.1.2 block diagra m..................................................................................................... 606 20.1.3 terminal............................................................................................................... 607 20.1.4 register config uration......................................................................................... 607 20.2 register desc ription.......................................................................................................... 608 20.2.1 mode register (simdr)...................................................................................... 608 20.2.2 clock select regist er (siscr) ............................................................................ 610 20.2.3 transmit data assign re gister (sitdar) .......................................................... 612 20.2.4 receive data assign re gister (sirdar)............................................................ 613 20.2.5 control command assign re gister (sicdar) ................................................... 614 20.2.6 serial control regist er (sictr).......................................................................... 616 20.2.7 fifo control regist er (sifctr) ........................................................................ 618 20.2.8 status register (sistr)....................................................................................... 620 20.2.9 interrupt enable regi ster (siier)........................................................................ 624 20.2.10 transmit data regist er (sitdr) ......................................................................... 626 20.2.11 receive data regist er (sirdr) .......................................................................... 627 20.2.12 transmit control data re gister (sitcr) ............................................................ 628 20.2.13 receive control data re gister (si rcr).............................................................. 629 20.3 operation...................................................................................................................... ..... 630 20.3.1 serial cloc k.......................................................................................................... 630 20.3.2 serial timi ng ....................................................................................................... 631 20.3.3 transmit data format .......................................................................................... 632 20.3.4 register assignment fo r transfer data................................................................ 634 20.3.5 control data in terface.......................................................................................... 637 20.3.6 fifo..................................................................................................................... 639 20.3.7 procedures for transm it or receive..................................................................... 641 20.3.8 interrupt ............................................................................................................... 646 20.3.9 transmit or recei ve timing ................................................................................ 648 20.4 usage notes .................................................................................................................... .. 652 20.4.1 notes on using the siof with versi ons previous to the SH7727b..................... 654 section 21 analog front end interface (afeif) ....................................................... 657 21.1 overview....................................................................................................................... .... 657 21.1.1 features................................................................................................................ 657 21.1.2 block diagra m..................................................................................................... 658 21.1.3 pin configuration................................................................................................. 659 21.1.4 register config uration......................................................................................... 659 21.2 register desc ription.......................................................................................................... 660 21.2.1 afeif control register 1 and 2 (actr1, actr2) ........................................... 660
rev.6.00 mar. 27, 2009 page xxix of lvi rej09b0254-0600 21.2.2 make ratio count re gister (m rcr)................................................................... 663 21.2.3 minimum pause count re gister (mpcr)............................................................ 663 21.2.4 afeif status register 1 an d 2 (astr1, astr2)............................................... 664 21.2.5 dial pulse number queue (dpnq) ..................................................................... 669 21.2.6 ringing pulse coun ter (rcnt)........................................................................... 670 21.2.7 afe control data regi ster (acd r) ................................................................... 670 21.2.8 afe status data regi ster (asdr) ...................................................................... 670 21.2.9 transmit data fifo port (tdfp)........................................................................ 671 21.2.10 receive data fifo port (rdfp) ......................................................................... 671 21.3 operation...................................................................................................................... ..... 671 21.3.1 interrupt timing................................................................................................... 671 21.3.2 afe interface....................................................................................................... 673 21.3.3 daa interface...................................................................................................... 675 21.3.4 wake up ringing interrupt .................................................................................. 677 section 22 usb pin multiplex controller .................................................................... 679 22.1 feature ........................................................................................................................ ...... 679 22.1.1 block diagra m..................................................................................................... 680 22.1.2 pin configuration................................................................................................. 681 22.1.3 register config uration......................................................................................... 682 22.2 register desc ription.......................................................................................................... 683 22.2.1 extra pin function cont roller (expfc) .............................................................. 683 22.3 examples of extern al circuit ............................................................................................ 684 22.3.1 example of the connection between usb function controller and transceiver.................................................................................................... 684 22.3.2 example of the connection between usb ho st controller and transceiver....... 689 22.3.3 usage note s ......................................................................................................... 690 section 23 usb function controller ............................................................................. 691 23.1 features....................................................................................................................... ...... 691 23.2 block diagram .................................................................................................................. 692 23.3 pin configuration.............................................................................................................. 692 23.4 register config uration...................................................................................................... 69 3 23.5 register desc riptions ........................................................................................................ 6 94 23.5.1 usbep0i data register (usbepdr0i) .............................................................. 694 23.5.2 usbep0o data register (usbepdr0o)............................................................ 694 23.5.3 usbep0s data register (usbepdr0s) ............................................................. 694 23.5.4 usbep1 data register (usbepdr1)................................................................. 695 23.5.5 usbep2 data register (usbepdr2)................................................................. 695 23.5.6 usbep3 data register (usbepdr3)................................................................. 695 23.5.7 usb interrupt flag regist er 0 (usbifr0).......................................................... 695
rev.6.00 mar. 27, 2009 page xxx of lvi rej09b0254-0600 23.5.8 usb interrupt flag regist er 1 (usbifr1).......................................................... 697 23.5.9 usb trigger register (usbtrg) ....................................................................... 698 23.5.10 usbfifo clear register (usbfclr)................................................................ 699 23.5.11 usbep0o receive data size re gister (usbepsz0o) ....................................... 699 23.5.12 usb data status regist er (usbdasts) ............................................................ 700 23.5.13 usb endpoint stall regi ster (usbepstl) ........................................................ 700 23.5.14 usb interrupt enable regi ster 0 (usbier0)...................................................... 701 23.5.15 usb interrupt enable regi ster 1 (usbier1)...................................................... 701 23.5.16 usbep1 receive data size re gister (usbe psz1) ............................................ 701 23.5.17 usb interrupt select regi ster 0 (usbisr0) ....................................................... 702 23.5.18 usb interrupt select regi ster 1 (usbisr1) ....................................................... 702 23.5.19 usbdma setting register (usbdmar)........................................................... 703 23.6 operation...................................................................................................................... ..... 704 23.6.1 cable connection................................................................................................. 704 23.6.2 cable disconn ection ............................................................................................ 705 23.6.3 control tran sfer................................................................................................... 706 23.6.4 ep1 bulk-out transfer (dual fifos).................................................................. 713 23.6.5 ep2 bulk-in transfer (dual fifos) .................................................................... 714 23.6.6 ep3 interrupt-in transfer..................................................................................... 716 23.7 processing of usb standard commands and class/vendor commands.......................... 717 23.7.1 processing of commands transmit ted by control transfer ................................ 717 23.8 stall oper ations............................................................................................................... .. 718 23.8.1 overview.............................................................................................................. 718 23.8.2 forcible stall by application ............................................................................... 718 23.8.3 automatic stall by usb function modu le .......................................................... 720 23.9 usage notes .................................................................................................................... .. 722 23.9.1 receiving setu p data........................................................................................... 722 23.9.2 clearing the fifo ................................................................................................ 722 23.9.3 overreading and overwriting th e data registers ................................................ 722 23.9.4 assigning interrupt s ources to ep0 ..................................................................... 723 23.9.5 clearing the fifo when dma tr ansfer is enabled ............................................ 723 23.9.6 notes on tr interrupt .......................................................................................... 723 23.9.7 peripheral clock (p ) operation frequency ........................................................ 724 section 24 usb host module ...................................................................................... 725 24.1 general description .......................................................................................................... 7 25 24.1.1 features................................................................................................................ 725 24.1.2 pin configuration................................................................................................. 726 24.1.3 register config uration......................................................................................... 727 24.2 register desc ription.......................................................................................................... 728 24.2.1 hcrevision ........................................................................................................... 728
rev.6.00 mar. 27, 2009 page xxxi of lvi rej09b0254-0600 24.2.2 hccontrol ............................................................................................................. 729 24.2.3 hccommandstatus .............................................................................................. 732 24.2.4 hcinterruptsta tus ................................................................................................. 735 24.2.5 hcinterruptena ble................................................................................................ 737 24.2.6 hcinterruptdis able............................................................................................... 739 24.2.7 hchcca.............................................................................................................. 740 24.2.8 hcperiodcurrented............................................................................................. 740 24.2.9 hccontrolheaded............................................................................................... 741 24.2.10 hccontrolcurre nted ........................................................................................... 741 24.2.11 hcbulkheaded ................................................................................................... 741 24.2.12 hcbulkcurrented................................................................................................ 742 24.2.13 hcdonehead........................................................................................................ 742 24.2.14 hcfminterval ....................................................................................................... 743 24.2.15 hcfmremaining .................................................................................................. 744 24.2.16 hcfmnumber ...................................................................................................... 745 24.2.17 hcperiodicstart .................................................................................................... 746 24.2.18 hclsthreshold .................................................................................................... 746 24.2.19 hcrhdescriptora ................................................................................................ 747 24.2.20 hcrhdescriptorb................................................................................................. 749 24.2.21 hcrhstatus .......................................................................................................... 750 24.2.22 hcrhportstatus[1:2] ............................................................................................ 751 24.3 data storage format which require d by usb host co ntroller........................................ 757 24.3.1 storage format of the transferred data............................................................... 757 24.3.2 storage format of th e descript or......................................................................... 758 24.4 data alignment restriction of usb host cont roller........................................................ 758 24.4.1 restriction on the line boundary of the synchron ous dram ........................... 758 24.4.2 restriction on the memory access address ........................................................ 759 24.5 restrictions on the data tran sfer of usb co ntroller ....................................................... 759 24.5.1 restriction of the data si ze in in transfer.......................................................... 759 24.5.2 restrictions on the hub connec tion on nak/stall reception ....................... 759 24.5.3 restrictions when a low-speed device is discon nected .................................... 760 24.6 restrictions on the software reset and usb reset .......................................................... 760 24.7 notes on using usb host with versio ns previous to the SH7727c................................ 760 24.8 usage notes of resume operation of usb host controller (usbh) .............................. 761 section 25 lcd controller ............................................................................................... 763 25.1 overview....................................................................................................................... .... 763 25.1.1 features................................................................................................................ 763 25.1.2 block diagra m..................................................................................................... 764 25.1.3 pin configuration................................................................................................. 765 25.1.4 register config uration......................................................................................... 765
rev.6.00 mar. 27, 2009 page xxxii of lvi rej09b0254-0600 25.2 register desc riptions ........................................................................................................ 7 67 25.2.1 lcdc input clock regi ster (ldickr) .............................................................. 767 25.2.2 lcdc module type regi ster (ldmtr) ............................................................ 768 25.2.3 lcdc data format regi ster (lddfr)............................................................... 771 25.2.4 lcdc scan mode regi ster (ldsmr) ................................................................ 773 25.2.5 lcdc start address register for uppe r display data fetch (ldsaru) .......... 774 25.2.6 lcdc start address register for lowe r display data fetch (ldsarl) .......... 775 25.2.7 lcdc line address offset register fo r display data fetch (ldlaor) .......... 776 25.2.8 lcdc palette control regi ster (ldpalcr)...................................................... 777 25.2.9 palette data registers 00 to ff (ldpr00 to ldprff) ...................................... 778 25.2.10 lcdc horizontal character numb er register (ldhcnr) ................................ 779 25.2.11 lcdc horizontal sync signal register (ldhsynr) ........................................ 780 25.2.12 lcdc vertical display line numb er register (ldvdlnr)............................. 781 25.2.13 lcdc vertical total line numb er register (ldvtlnr)................................. 782 25.2.14 lcdc vertical sync signal register (ldvsynr) ............................................ 783 25.2.15 lcdc ac modulation signal toggle li ne number register (ldaclnr) ...... 784 25.2.16 lcdc interrupt control re gister (ldintr) ...................................................... 784 25.2.17 lcdc power management mode register (ldpmmr)..................................... 786 25.2.18 lcdc power-supply sequence peri od register (ldpspr) ............................... 788 25.2.19 lcdc control regist er (ldcntr).................................................................... 789 25.3 operation...................................................................................................................... ..... 790 25.3.1 lcd module sizes which can be displayed in th is lcdc ................................. 790 25.3.2 limits on the resolution of rotated displays, burst length, and connected memory (sdram).............................................................................................. 791 25.3.3 color palette speci fication................................................................................... 797 25.3.4 data format ......................................................................................................... 799 25.3.5 timing controller register .................................................................................. 802 25.3.6 power management registers.............................................................................. 802 25.3.7 operation for hardwa re rotatio n......................................................................... 807 25.4 clock and lcd data si gnal exampl es ............................................................................. 809 25.5 usage notes .................................................................................................................... .. 819 section 26 pin func tion controller (pfc) ................................................................... 821 26.1 overview....................................................................................................................... .... 821 26.2 register config uration...................................................................................................... 82 6 26.3 register desc riptions ........................................................................................................ 8 27 26.3.1 port a control regi ster (pacr) ......................................................................... 827 26.3.2 port b control regi ster (pbcr) .......................................................................... 828 26.3.3 port c control regi ster (pccr) .......................................................................... 829 26.3.4 port d control regi ster (pdcr) ......................................................................... 830 26.3.5 port e control regi ster (pecr) .......................................................................... 831
rev.6.00 mar. 27, 2009 page xxxiii of lvi rej09b0254-0600 26.3.6 port f control regi ster (pfcr)........................................................................... 832 26.3.7 port g control regi ster (pgcr) ......................................................................... 833 26.3.8 port h control regi ster (phcr) ......................................................................... 835 26.3.9 port j control regi ster (pjcr) ............................................................................ 836 26.3.10 port k control regi ster (pkcr) ......................................................................... 837 26.3.11 port l control regi ster (plcr) .......................................................................... 838 26.3.12 port m control regi ster (pm cr) ........................................................................ 839 26.3.13 sc port control regi ster (scp cr) ..................................................................... 840 section 27 i/o ports ............................................................................................................ 845 27.1 overview....................................................................................................................... .... 845 27.2 register config uration...................................................................................................... 84 6 27.3 ports a to c, e, j, k.......................................................................................................... 847 27.3.1 ports a to c, e, j, k data rgister (padr, pbdr, pcdr, pedr, pjdr, pkdr) ................................................... 847 27.4 port d......................................................................................................................... ....... 848 27.4.1 port d data register (pddr).............................................................................. 848 27.5 ports f, m ..................................................................................................................... .... 850 27.5.1 ports f, m data register (pfdr, pmdr)........................................................... 850 27.6 port g......................................................................................................................... ....... 851 27.6.1 port g data register (pgdr).............................................................................. 851 27.7 port h......................................................................................................................... ....... 852 27.7.1 port h data register (phdr).............................................................................. 852 27.8 port l ......................................................................................................................... ....... 854 27.8.1 port l data regist er (pldr)............................................................................... 854 27.9 sc port........................................................................................................................ ...... 855 27.9.1 port sc data regist er (scpdr).......................................................................... 855 section 28 a/d converter ................................................................................................. 857 28.1 overview....................................................................................................................... .... 857 28.1.1 features................................................................................................................ 857 28.1.2 block diagra m..................................................................................................... 858 28.1.3 input pins ............................................................................................................. 859 28.1.4 register config uration......................................................................................... 860 28.2 register desc riptions ........................................................................................................ 8 61 28.2.1 a/d data registers a to d (addra to addrd) ............................................. 861 28.2.2 a/d control/status regi ster (adcsr) ............................................................... 862 28.2.3 a/d control register (adcr) ............................................................................ 864 28.3 bus master in terface ......................................................................................................... 8 65 28.4 operation...................................................................................................................... ..... 867 28.4.1 single mode (multi = 0) .................................................................................. 867
rev.6.00 mar. 27, 2009 page xxxiv of lvi rej09b0254-0600 28.4.2 multi mode (multi = 1, scn = 0).................................................................... 869 28.4.3 scan mode (multi = 1, scn = 1) ..................................................................... 871 28.4.4 input sampling and a/d co nversion time ......................................................... 873 28.4.5 external trigger in put timing............................................................................. 874 28.5 interrupts ..................................................................................................................... ...... 875 28.6 definitions of a/d conv ersion accu racy......................................................................... 875 28.7 usage notes .................................................................................................................... .. 876 28.7.1 setting analog inpu t voltage .............................................................................. 876 28.7.2 processing of analog input pins .......................................................................... 876 28.7.3 access size and re ad data.................................................................................. 877 section 29 d/a converter ................................................................................................. 879 29.1 overview....................................................................................................................... .... 879 29.1.1 features................................................................................................................ 879 29.1.2 block diagra m..................................................................................................... 879 29.1.3 i/o pins ................................................................................................................ 880 29.1.4 register config uration......................................................................................... 880 29.2 register desc riptions ........................................................................................................ 8 81 29.2.1 d/a data registers 0 an d 1 (dadr0/1).............................................................. 881 29.2.2 d/a control register (dacr) ............................................................................ 881 29.3 operation...................................................................................................................... ..... 883 section 30 pc ca rd controller (pcc) ........................................................................... 885 30.1 overview....................................................................................................................... .... 885 30.1.1 features................................................................................................................ 885 30.1.2 block diagra m..................................................................................................... 886 30.1.3 register config uration......................................................................................... 887 30.1.4 pcmcia suppo rt................................................................................................. 888 30.2 register desc riptions ........................................................................................................ 8 91 30.2.1 area 6 interface status register (pcc0 isr) ....................................................... 891 30.2.2 area 6 general control re gister (pcc0 gcr) .................................................... 894 30.2.3 area 6 card status change register (p cc0cscr) ............................................. 896 30.2.4 area 6 card status change interrupt enable register (pcc0cscier) .............. 900 30.3 operation...................................................................................................................... ..... 903 30.3.1 pc card connection specification (interfa ce diagram, pin correspondence)..... 903 30.3.2 pc card interf ace timing .................................................................................... 907 30.3.3 usage note s ......................................................................................................... 912 section 31 user-debug ging interface (h-udi) .......................................................... 915 31.1 overview....................................................................................................................... .... 915 31.2 user debugging inte rface (h-udi ) .................................................................................. 915
rev.6.00 mar. 27, 2009 page xxxv of lvi rej09b0254-0600 31.2.1 pin description .................................................................................................... 915 31.2.2 block diagra m..................................................................................................... 916 31.3 register desc riptions ........................................................................................................ 9 16 31.3.1 bypass register (sdbpr) ................................................................................... 917 31.3.2 instruction regist er (sdir) ................................................................................. 917 31.3.3 boundary-scan regist er (sdbsr) ...................................................................... 918 31.4 h-udi operations............................................................................................................. 9 25 31.4.1 tap controller .................................................................................................... 925 31.4.2 reset configur ation ............................................................................................. 926 31.4.3 h-udi reset ........................................................................................................ 927 31.4.4 h-udi interrupt ................................................................................................... 927 31.4.5 bypass.................................................................................................................. 927 31.4.6 using h-udi to recover from sleep mode......................................................... 927 31.5 usage notes .................................................................................................................... .. 928 31.6 advanced user debugger (aud) ..................................................................................... 928 section 32 electri cal characteristics .............................................................................. 929 32.1 absolute maximum ratings ............................................................................................. 929 32.2 dc character istics ............................................................................................................ 931 32.3 ac character istics ............................................................................................................ 934 32.3.1 clock timing ....................................................................................................... 937 32.3.2 control signal timing ......................................................................................... 946 32.3.3 ac bus timing.................................................................................................... 949 32.3.4 basic timing........................................................................................................ 951 32.3.5 burst rom timing .............................................................................................. 954 32.3.6 synchronous dram timing ............................................................................... 957 32.3.7 pcmcia timing ................................................................................................. 968 32.3.8 peripheral module si gnal timing........................................................................ 975 32.3.9 h-udi-related pin timing.................................................................................. 978 32.3.10 lcdc timing ...................................................................................................... 980 32.3.11 siof module signa l timing................................................................................ 982 32.3.12 usb module signa l timing ................................................................................ 985 32.3.13 afeif module sign al timing ............................................................................. 987 32.3.14 ac characteristics measur ement conditio ns ...................................................... 989 32.3.15 delay time variation due to load capacitance ................................................. 990 32.4 a/d converter char acteristics .......................................................................................... 991 32.5 d/a converter char acteristics .......................................................................................... 991 appendix a pin functions ................................................................................................ 993 a.1 pin functions .................................................................................................................. .. 993 a.2 treatment of unused pins................................................................................................. 999
rev.6.00 mar. 27, 2009 page xxxvi of lvi rej09b0254-0600 a.3 pin status when accessing address sp aces ................................................................... 1004 appendix b control registers ....................................................................................... 1019 b.1 register addre ss map..................................................................................................... 1019 appendix c product lineup ........................................................................................... 1029 appendix d package dimensions ................................................................................ 1031 appendix e using versions previous to the SH7727c ......................................... 1033 e.1 determining the version number based on the markings on the chip.......................... 1033 appendix f using port g control regist er (pgcr) with versions previous to the SH7727c .......................................................................................... 1035
rev.6.00 mar. 27, 2009 page xxxvii of lvi rej09b0254-0600 figures section 1 overview and pin functions figure 1.1 bl ock diagram ....................................................................................................... 8 figure 1.2 pin arrangem ent (prqp02 40kc-b) ..................................................................... 9 figure 1.3 pin arrangem ent (plbg0240ja-a) ...................................................................... 10 section 2 cpu figure 2.1 register configuration in each processing mode (1) ............................................ 23 figure 2.2 register configuration in each processing mode (2) ............................................ 24 figure 2.3 general purpose regi ster (not in dsp mode) ....................................................... 25 figure 2.4 general purpose register (dsp mode) .................................................................. 26 figure 2.5 control registers (1) .............................................................................................. 29 figure 2.5 control registers (2) .............................................................................................. 30 figure 2.6 syst em registers .................................................................................................... 31 figure 2.7 ds p registers....................................................................................................... .. 35 figure 2.8 connections of ds p registers and buses .............................................................. 37 figure 2.9 longwo rd operand ................................................................................................ 38 figure 2.10 da ta format........................................................................................................ .... 39 figure 2.11 byte, word, and longword alignment .................................................................. 40 figure 2.12 x and y data transfer addressing ........................................................................ 49 figure 2.13 single data tr ansfer addressing............................................................................ 50 figure 2.14 modulo addressing ................................................................................................ 5 2 figure 2.15 dsp instru ction formats ........................................................................................ 58 figure 2.16 sample parallel instruction program...................................................................... 87 figure 2.17 examples of conditional operati ons and data transfer instructions .................... 95 section 3 memory management unit (mmu) figure 3.1 mmu functions ..................................................................................................... 9 9 figure 3.2 logical addr ess space mapp ing............................................................................ 101 figure 3.3 mmu regist er conten ts ........................................................................................ 104 figure 3.4 overall config uration of the tlb.......................................................................... 105 figure 3.5 logical address and tlb struct ure....................................................................... 106 figure 3.6 tlb indexi ng (ix = 1) ........................................................................................... 107 figure 3.7 tlb indexi ng (ix = 0) ........................................................................................... 108 figure 3.8 objects of a ddress comparison............................................................................. 109 figure 3.9 operation of ldtlb instruction............................................................................ 113 figure 3.10 syno nym problem .................................................................................................. 1 15 figure 3.11 mmu exception ge neration flowchart ................................................................. 120 figure 3.12 mmu exception signal s in instructio n fetch ........................................................ 121 figure 3.13 mmu exception sign als in data access ............................................................... 122
rev.6.00 mar. 27, 2009 page xxxviii of lvi rej09b0254-0600 figure 3.14 mmu exception in repeat loop ........................................................................... 123 figure 3.15 specifying address and data for memory-mapped tlb access .......................... 126 section 4 exception handling figure 4.1 v ector ta ble........................................................................................................ ... 132 figure 4.2 example of acceptance order of general exceptions ........................................... 135 figure 4.3 bit configurations of expevt, intevt, intevt2, and tra registers .......... 139 section 5 cache figure 5.1 cach e structure ..................................................................................................... . 150 figure 5.2 ccr register configuratio n .................................................................................. 152 figure 5.3 ccr2 register configura tion ................................................................................ 153 figure 5.4 cache se arch scheme ............................................................................................ 155 figure 5.5 write-back buffe r configurat ion........................................................................... 157 figure 5.6 specifying address and data for memory-mapped ca che access........................ 159 section 6 x/y memory figure 6.1 x/y memory logi cal address ma pping................................................................ 163 figure 6.2 x/y memory physi cal address ma pping .............................................................. 164 section 7 interrupt controller (intc) figure 7.1 intc bl ock diagram ............................................................................................. 166 figure 7.2 example of irl interrupt conn ection.................................................................... 171 figure 7.3 interrupt oper ation flowchart................................................................................ 198 figure 7.4 example of pipeline operations when irl interrupt is accepted ......................... 202 section 8 user break controller figure 8.1 block diagram of user break controller............................................................... 204 section 9 power-down modes and software reset figure 9.1 canceling standby mode with st bcr.stby....................................................... 246 figure 9.2 power-on reset (clock modes 0, 1, 2, and 7) status output ........................... 249 figure 9.3 manual reset status output.............................................................................. 250 figure 9.4 standby to inte rrupt status output.................................................................... 250 figure 9.5 standby to power-on reset status output ....................................................... 251 figure 9.6 standby to manual reset status output............................................................ 251 figure 9.7 sleep to interr upt status output........................................................................ 252 figure 9.8 sleep to power-on reset status output............................................................ 252 figure 9.9 sleep to manual reset status output................................................................ 253 figure 9.10 hardware standby mode timing (ca = low in normal operation) .................... 255
rev.6.00 mar. 27, 2009 page xxxix of lvi rej09b0254-0600 figure 9.11 hardware standby mode timing (ca = low during wdt operation while standby mode is cleared) ............................................................................ 256 section 10 on-chip oscillation circuits figure 10.1 block diagram of clock pulse generator .............................................................. 259 figure 10.2 block diag ram of the wdt ................................................................................... 271 figure 10.3 writing to wtcnt and wtcsr........................................................................... 275 figure 10.4 points for attention wh en using crystal resonator............................................... 277 figure 10.5 points for attention when using pll oscillator circ uit ....................................... 278 section 11 extend clock pulse generator for usb (excpg) figure 11.1 block di agram of excpg ..................................................................................... 279 section 12 bus state controller (bsc) figure 12.1 corresponding to logical address space and ph ysical addre ss space................. 285 figure 12.2 corresponding to logical address space and ph ysical addre ss space................. 289 figure 12.3 physical space alloca tion ...................................................................................... 291 figure 12.4 writing to rfcr, rt csr, rtcnt, and rtcor................................................. 315 figure 12.5 basic timing of basic inte rface ............................................................................. 326 figure 12.6 example of 32-bit data-w idth static ram connection ....................................... 327 figure 12.7 example of 16-bit data-w idth static ram connection ....................................... 328 figure 12.8 example of 8-bit data-w idth static ram connection ......................................... 328 figure 12.9 basic interface wait timing (software wait only)............................................... 329 figure 12.10 basic interface wait st ate timing (wait state insertion by wait signal waitsel = 1)....................................................................................................... 330 figure 12.11 example of 64-mb it synchronous dram connectio n (32-bit bus width) ......... 332 figure 12.12 example of 64-mbit synchr onous dram (16-bit bus width)............................. 333 figure 12.13 basic timing for sync hronous dram bu rst read ............................................... 336 figure 12.14 synchronous dram burst read wait specifica tion timing ................................ 337 figure 12.15 basic timing for sync hronous dram sing le read.............................................. 338 figure 12.16 basic timing for sync hronous dram bu rst write .............................................. 339 figure 12.17 basic timing for sync hronous dram sing le write............................................. 341 figure 12.18 auto-re fresh operation ......................................................................................... 34 2 figure 12.19 synchronous dram auto-refresh timing........................................................... 343 figure 12.20 synchronous dram self-refresh timing ............................................................ 344 figure 12.21 synchronous dram mode write timing ............................................................. 346 figure 12.22 burst rom wait access ti ming ........................................................................... 348 figure 12.23 burst rom ba sic access ti ming .......................................................................... 349 figure 12.24 example of pcmcia interface (if in ternal pc card controller is not used.)........ 351 figure 12.25 basic timing for pcmc ia memory card interface.............................................. 353 figure 12.26 wait timing for pcmcia memory card interface ............................................... 354
rev.6.00 mar. 27, 2009 page xl of lvi rej09b0254-0600 figure 12.27 basic timing for pcmcia me mory card interface burst acces s ........................ 355 figure 12.28 wait timing for pcmcia memo ry card interface bu rst access ......................... 356 figure 12.29 pcmcia sp ace assignment .................................................................................. 357 figure 12.30 basic timing for pc mcia i/o card interface ...................................................... 359 figure 12.31 wait timing for pcmc ia i/o card interface ....................................................... 360 figure 12.32 dynamic bus sizing timing for pcmcia i/o card interface .............................. 361 figure 12.33 waits betw een access cy cles ................................................................................ 363 figure 12.34 pins a25 to a0 pull-up timing............................................................................. 364 figure 12.35 pins d31 to d0 pu ll-up timing (rea d cycle)....................................................... 364 figure 12.36 pins d31 to d0 pull- up timing (write cycle)...................................................... 365 section 13 li bus state controller (lbsc) figure 13.1 block diagram of li bus architecture .................................................................. 377 section 14 direct memo ry access controller (dmac) figure 14.1 dmac bl ock diagra m .......................................................................................... 381 figure 14.2 dmac tran sfer flowchart .................................................................................... 399 figure 14.3 operation in round-robin mode........................................................................... 403 figure 14.4 channel priority or der in round-ro bin mode ...................................................... 404 figure 14.5 operation in direct addre ss mode......................................................................... 406 figure 14.6 example of dma transfer timing in the direct address mode (transfer source: ordinary memory, transfer destination: ordinary memory)... 407 figure 14.7 example of dma transfer timing in the direct address mode (16-byte transfer, transfer source: ordinary memory, transfer destination: ordinary memory) ................................................................................................. 408 figure 14.8 example of dma transfer timing in the direct address mode (16-byte transfer, transfer source: sy nchronous dram, transfer destination: ordinary memory) ................................................................................................. 408 figure 14.9 operation in indirect addre ss mode (when the external memory space is set to 16-b it width) ............................................................................................ 410 figure 14.10 example of transfer timing in indirect address mode (transfer between external memories, exte rnal memory with 16-bit width) ...... 411 figure 14.11 data flow in single addre ss mode........................................................................ 412 figure 14.12 example of dma transfer timing in single address mode ................................ 413 figure 14.13 example of dma transfer timing in single address mode (external memory space (ordinary memory) external device with dack) ................................ 414 figure 14.14 transfer exampl e in cycle-steal mode ................................................................. 415 figure 14.15 example of tran sfer in burst mode....................................................................... 415 figure 14.16 bus state in multip le channel oper ation............................................................... 417 figure 14.17 cycle-steal mode, level input (cpu access: 2 cycles) ....................................... 420 figure 14.18 cycle-steal mode, level input (cpu access: 3 cycles) ....................................... 421
rev.6.00 mar. 27, 2009 page xli of lvi rej09b0254-0600 figure 14.19 cycle-steal mode, level inpu t (cpu access: 2 cycles, dma rd access 4 cycles)................................................................................................................. 422 figure 14.20 cycle-steal mode, le vel input (cpu access: 2 cycles, dreq input delayed)... 423 figure 14.21 cycle-steal mode, edge input (cpu access: 2 cycles) ........................................ 424 figure 14.22 burst mode, level input ........................................................................................ 42 5 figure 14.23 burst mode, edge input ......................................................................................... 42 6 figure 14.24 source address re load function di agram ............................................................ 427 figure 14.25 timing chart of sour ce address reload function................................................. 428 figure 14.26 cmt bl ock diagram.............................................................................................. 43 1 figure 14.27 coun ter operation ................................................................................................. . 435 figure 14.28 count timing ...................................................................................................... ... 436 figure 14.29 timing of cmf setting .......................................................................................... 43 7 figure 14.30 timing of cmf clear by the cpu ......................................................................... 437 section 15 timer (tmu) figure 15.1 tmu bl ock diagram.............................................................................................. 444 figure 15.2 setting the count opera tion ................................................................................... 451 figure 15.3 auto-reload counter operat ion............................................................................. 452 figure 15.4 count timing when inte rnal clock is op erating ................................................... 452 figure 15.5 count timing when on-c hip rtc clock is operating ......................................... 453 figure 15.6 un f set timing ..................................................................................................... 453 figure 15.7 status fl ag clear timing........................................................................................ 45 4 section 16 realtime clock (rtc) figure 16.1 rtc block diagram............................................................................................... 45 8 figure 16.2(a) setting th e time .............................................................................................. ... 474 figure 16.2(b) setting th e time.............................................................................................. ... 474 figure 16.3 r eading the time ................................................................................................... 475 figure 16.4 using the alarm function ...................................................................................... 476 figure 16.5 example of crystal os cillator circuit c onnection................................................. 477 figure 16.6 periodic inte rrupt function setting ........................................................................ 478 section 17 serial commu nication interface (sci) figure 17.1 sci bl ock diagram ................................................................................................ 4 82 figure 17.2 scpt[1]/sck0 pin ................................................................................................ 48 3 figure 17.3 scpt[0]/txd0 pin................................................................................................. 4 84 figure 17.4 scpt[0]/rxd0 pin................................................................................................. 4 85 figure 17.5 data format in asynchronous communication (example with 8-bit data, pa rity, two stop bits)................................................. 511 figure 17.6 relationship between output clock and transfer data phase (asynchronous mo de)............................................................................................ 513
rev.6.00 mar. 27, 2009 page xlii of lvi rej09b0254-0600 figure 17.7 sample sci in itialization flow chart ...................................................................... 514 figure 17.8 sample serial transmission flowchart .................................................................. 515 figure 17.9 example of operation in transmission in asynchronous mode (example with 8-bit data, pa rity, one stop bit) ................................................... 517 figure 17.10 sample serial recep tion data flowch art (1) ......................................................... 518 figure 17.10 sample serial recep tion data flowch art (2) ......................................................... 519 figure 17.11 example of sc i operation in reception (example with 8-bit data, pa rity, one stop bit) ................................................... 521 figure 17.12 example of communication using multiprocessor format (transmission of data h'aa to receiving sta tion a) ........................................... 522 figure 17.13 sample multiprocessor se rial transmission flowchart ......................................... 523 figure 17.14 example of sci operation in transmission (example with 8-bit data, multipro cessor bit, one st op bit)............................... 525 figure 17.15 sample multiprocessor se rial reception flow chart (1)......................................... 526 figure 17.15 sample multiprocessor se rial reception flow chart (2)......................................... 527 figure 17.16 example of sc i operation in reception (example with 8-bit data, multipro cessor bit, one st op bit)............................... 528 figure 17.17 data format in cloc k synchronous comm unication............................................. 529 figure 17.18 sample sci in itialization flow chart ...................................................................... 531 figure 17.19 sample serial transmission flowchart .................................................................. 532 figure 17.20 sample sci transmission oper ation in clocked synchronous mode ................... 533 figure 17.21 sample serial reception flowchar t (1).................................................................. 534 figure 17.21 sample serial reception flowchar t (2).................................................................. 535 figure 17.22 example of sci operation in r eception ................................................................ 536 figure 17.23 sample flowchart of simultaneous serial transmit and receive operations ....... 537 figure 17.24 receive data sampling timing in asynch ronous mode ....................................... 540 section 18 smart card interface figure 18.1 smart card in terface block di agram ..................................................................... 544 figure 18.2 pin connection diagram for the smart card interface .......................................... 549 figure 18.3 data format fo r smart card in terface.................................................................... 550 figure 18.4 waveform of start char acter ................................................................................. 552 figure 18.5 initialization fl owchart (example)......................................................................... 556 figure 18.6 transmission fl owchart (example) ....................................................................... 558 figure 18.7 reception flow chart (examp le)............................................................................. 560 figure 18.8 receive data sampling timing in smart card mode ............................................ 562 figure 18.9 retransmission in sci receive mode.................................................................... 563 figure 18.10 retransmission in sci transmit mode .................................................................. 564 section 19 serial communicati on interface with fifo (scif) figure 19.1 scif block diagram.............................................................................................. 56 6
rev.6.00 mar. 27, 2009 page xliii of lvi rej09b0254-0600 figure 19.2 scpt[4]/txd2 pin................................................................................................. 5 67 figure 19.3 scpt[4]/rxd2 pin................................................................................................. 5 68 figure 19.4 sample scif in itialization flow chart .................................................................... 592 figure 19.5 sample serial transmission flowchart .................................................................. 593 figure 19.6 example of transmit operation (example with 8-bit data, pa rity, one stop bit) ................................................... 595 figure 19.7 example of operation using modem control ( cts2 )........................................... 595 figure 19.8 sample serial reception flowchar t (1).................................................................. 596 figure 19.9 sample serial reception flowchar t (2).................................................................. 597 figure 19.10 example of scif receive operation (example with 8-bit data, pa rity, one stop bit) ................................................... 599 figure 19.11 example of operation using modem control ( rts2 )........................................... 599 figure 19.12 receive data sampling timing in asynch ronous mode ....................................... 602 section 20 serial io (siof) figure 20.1 siof block diagram.............................................................................................. 60 6 figure 20.2 serial cloc k supply sy stem ................................................................................... 630 figure 20.3 siof serial da ta synchronized timing................................................................. 631 figure 20.4 siof transmit or receive ti ming ......................................................................... 632 figure 20.5 transmit or recei ve data bit a lignment ............................................................... 634 figure 20.6 control data bit alignment ................................................................................... 636 figure 20.7 control data in terface (slot po sition).................................................................... 637 figure 20.8 control data in terface (secondary fs) .................................................................. 638 figure 20.9 example of transm it operation in master ............................................................. 641 figure 20.10 example of receive operation in master............................................................... 642 figure 20.11 example of transm it operation in slave ............................................................... 643 figure 20.12 example of receive operation in slave................................................................. 644 figure 20.13 transmit or receive timing (8 bits monaural?1) ................................................ 648 figure 20.14 transmit or receive timing (8 bits monaural?2) ................................................ 648 figure 20.15 transmit or receive timing (16 bits monaural?1) .............................................. 649 figure 20.16 transmit or receive timing (16 bits st ereo?1).................................................... 649 figure 20.17 transmit or receive timing (16 bits st ereo?2).................................................... 650 figure 20.18 transmit or receive timing (16 bits st ereo?3).................................................... 650 figure 20.19 transmit or receive timing (16 bits monaural?2) .............................................. 651 section 21 analog front end interface (afeif) figure 21.1 block diagra m of afe interface ........................................................................... 658 figure 21.2 fifo interrupt timing............................................................................................ 6 72 figure 21.3 ringing interrupt occurrence timing .................................................................... 672 figure 21.4 interrupt generator................................................................................................ . 673 figure 21.5 afe serial interface............................................................................................... 673
rev.6.00 mar. 27, 2009 page xliv of lvi rej09b0254-0600 figure 21.6 afe cont rol sequence........................................................................................... 674 figure 21.7 daa block diagram.............................................................................................. 675 figure 21.8 ringing de tect sequen ce ....................................................................................... 676 section 22 usb pin multiplex controller figure 22.1 block diagram of usb pin multip lexer ............................................................... 680 figure 22.2 example 1 of transceiver connection for usb function controller (on-chip transceiver is used).................................................................................. 684 figure 22.3 example 2 of transceiver connection for usb function controller (on-chip transceiver is used).................................................................................. 685 figure 22.4 example 3 of transceiver connection for usb function controller (on-chip transceiver is not used)............................................................................ 686 figure 22.5 example 4 of transceiver connection for usb function controller (on-chip transceiver is not used)............................................................................ 687 figure 22.6 example 1 of transceiver connection for usb host controller (on-chip transceiver is used).................................................................................. 689 figure 22.7 example 2 of transceiver connection for usb host controller (on-chip transceiver is not used)............................................................................ 690 section 23 usb function controller figure 23.1 block di agram of ubc.......................................................................................... 692 figure 23.2 cable conne ction opera tion .................................................................................. 704 figure 23.3 cable disco nnection opera tion.............................................................................. 705 figure 23.4 transfer stage for control transfer ....................................................................... 706 figure 23.5 setup st age operation ............................................................................................ 7 07 figure 23.6 data stage op eration (contro l-in) ......................................................................... 708 figure 23.7 data stage op eration (contro l-out) ...................................................................... 710 figure 23.8 status stage op eration (contr ol-in)....................................................................... 711 figure 23.9 status stage op eration (control -out) .................................................................... 712 figure 23.10 ep1 bulk-out transfer operation.......................................................................... 713 figure 23.11 ep2 bulk-in tr ansfer operation ............................................................................ 714 figure 23.12 ep2 interrupt-in transfer operation ...................................................................... 716 figure 23.13 forcible sta ll by applica tion ................................................................................. 719 figure 23.14 automatic stall by usb function module............................................................. 721 figure 23.15 tr interrup t flag set ti ming ................................................................................. 723 section 25 lcd controller figure 25.1 bl ock diagram ...................................................................................................... . 764 figure 25.2 valid displa y and retrace pe riod .......................................................................... 786 figure 25.3 color-pale tte data format...................................................................................... 798 figure 25.4 power-supply control sequen ce and states of th e lcd module .......................... 803
rev.6.00 mar. 27, 2009 page xlv of lvi rej09b0254-0600 figure 25.5 power-supply control sequen ce and states of th e lcd module .......................... 803 figure 25.6 power-supply control sequen ce and states of th e lcd module .......................... 804 figure 25.7 power-supply control sequen ce and states of th e lcd module .......................... 804 figure 25.8 clock and lcd da ta signal ex ample.................................................................... 809 figure 25.9 clock and lcd da ta signal ex ample.................................................................... 810 figure 25.10 clock and lcd da ta signal ex ample.................................................................... 810 figure 25.11 clock and lcd da ta signal ex ample.................................................................... 811 figure 25.12 clock and lcd da ta signal ex ample.................................................................... 811 figure 25.13 clock and lcd da ta signal ex ample.................................................................... 812 figure 25.14 clock and lcd da ta signal ex ample.................................................................... 812 figure 25.15 clock and lcd da ta signal ex ample.................................................................... 813 figure 25.16 clock and lcd da ta signal ex ample.................................................................... 813 figure 25.17 clock and lcd da ta signal ex ample.................................................................... 814 figure 25.18 clock and lcd da ta signal ex ample.................................................................... 815 figure 25.19 clock and lcd da ta signal ex ample.................................................................... 816 figure 25.20 clock and lcd da ta signal ex ample.................................................................... 817 figure 25.21 clock and lcd da ta signal ex ample.................................................................... 818 section 26 pin function controller (pfc) figure 26.1 overview of the pin selection fu nction................................................................. 821 section 28 a/d converter figure 28.1 a/d converte r block diagram............................................................................... 858 figure 28.2 a/d data register acce ss operation (reading h'aa40)...................................... 866 figure 28.3 example of a/d converter opera tion (single mode, channe l 2 selected) ........... 868 figure 28.4 example of a/d converter operation (multi mode, channels an4 to an6 select ed) ..................................................... 870 figure 28.5 example of a/d converter operation (scan mode, channels an4 to an6 selected) ...................................................... 872 figure 28.6 a/d conv ersion timing......................................................................................... 873 figure 28.7 external tr igger input timing ............................................................................... 874 figure 28.8 definitions of a/ d conversion accuracy .............................................................. 876 figure 28.9 example of analog input protection circuit.......................................................... 877 figure 28.10 analog input pi n equivalent ci rcuit ...................................................................... 877 section 29 d/a converter figure 29.1 d/a converte r block diagram............................................................................... 879 figure 29.2 example of d/a converter oper ation.................................................................... 883 section 30 pc card controller (pcc) figure 30.1 pc card cont roller block diagram ....................................................................... 886
rev.6.00 mar. 27, 2009 page xlvi of lvi rej09b0254-0600 figure 30.2 continuous 32-mb area mode .............................................................................. 889 figure 30.3 continuous 16-mb area mode (area 6)................................................................ 890 figure 30.4 sh 7727 interface................................................................................................... . 903 figure 30.5 pcmcia memory ca rd interface basi c timing ................................................... 907 figure 30.6 pcmcia memory ca rd interface wait timing..................................................... 908 figure 30.7 pcmcia i/o card interface basic timing............................................................ 909 figure 30.8 pcmcia i/o card interface wait timing ............................................................. 910 figure 30.9 dynamic bus sizing timing for pcmcia i/ o card interface .............................. 911 section 31 user-debugging interface (h-udi) figure 31.1 h-udi bl ock diagra m ........................................................................................... 916 figure 31.2 tap controlle r state trans itions ........................................................................... 925 figure 31.3 h-udi reset........................................................................................................ ... 927 section 32 electrical characteristics figure 32.1 power-on sequence ............................................................................................... 93 0 figure 32.2 power supply voltage and operating frequency .................................................. 935 figure 32.3 extal cloc k input timi ng .................................................................................. 941 figure 32.4 ckio cloc k input timing ..................................................................................... 941 figure 32.5 ckio cloc k output timing................................................................................... 942 figure 32.6 power-on os cillation settling time ....................................................................... 942 figure 32.7 oscillation settling time at standby return (retur n by reset)............................. 943 figure 32.8 oscillation settling time at standby return (ret urn by nmi).............................. 943 figure 32.9 oscillation settling time at standb y return (return by ir q4 to irq0)............... 944 figure 32.10 pll synchronization settling ti me by reset or nm i interrup t ............................ 944 figure 32.11 pll synchronization settling time by irq/irl and pint0/ 1 interrupt .............. 945 figure 32.12 pll sync stabilization time at frequency multiplier factor change .................. 945 figure 32.13 rese t input timing................................................................................................ . 947 figure 32.14 interrupt si gnal input timing ................................................................................. 947 figure 32.15 bus release timing ............................................................................................... 948 figure 32.16 pin drive ti ming at sta ndby.................................................................................. 948 figure 32.17 basic bus cycle (no wait) .................................................................................... 951 figure 32.18 basic bus cycle (one wait) .................................................................................. 952 figure 32.19 basic bus cycle (ext ernal wait, wait sel = 1) .................................................. 953 figure 32.20 burst rom bu s cycle (no wait) .......................................................................... 954 figure 32.21 burst rom bus cycle (two wa its) ...................................................................... 955 figure 32.22 burst rom bus cycle (e xternal wait, wait sel = 1) ........................................ 956 figure 32.23 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0)..... 957 figure 32.24 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1)..... 958 figure 32.25 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1) ................................................................... 959
rev.6.00 mar. 27, 2009 page xlvii of lvi rej09b0254-0600 figure 32.26 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0) ................................................................... 960 figure 32.27 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0).............. 961 figure 32.28 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1).............. 962 figure 32.29 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0) ............................................................................. 963 figure 32.30 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0) ............................................................................. 964 figure 32.31 synchronous dram auto-re fresh cycle (tras = 1, tpc = 1).......................... 965 figure 32.32 synchronous dram sel f-refresh cycle (tpc = 0).............................................. 966 figure 32.33 synchronous dram m ode register write cycle ................................................. 967 figure 32.34 pcmcia memory bus cycle (ted = 0, teh = 0, no wait) ............................... 968 figure 32.35 pcmcia memory bus cycle (ted = 2, teh = 1, one wait, ex ternal wait, wait sel = 1) ............................ 969 figure 32.36 pcmcia memory bus cycle (burst read, ted = 0, teh = 0, no wait)............ 970 figure 32.37 pcmcia memory bus cycle (burst read, ted = 1, teh = 1, two waits, burst pitch = 3, waitsel = 1) .... 971 figure 32.38 pcmcia i/o bus cycle (t ed = 0, teh = 0, no wait)........................................ 972 figure 32.39 pcmcia i/o bus cycle (ted = 2, teh = 1, one wait, ex ternal wait, wait sel = 1) ............................ 973 figure 32.40 pcmcia i/o bus cycle (ted = 1, teh = 1, one wait, bus sizing, wait sel = 1) ................................. 974 figure 32.41 oscillation settling time at rtc crystal oscilla tor power-on ............................. 976 figure 32.42 sck inpu t clock timing ....................................................................................... 976 figure 32.43 sci i/o timing in clock synchronou s mode ........................................................ 976 figure 32.44 i/ o port timing ................................................................................................... ... 977 figure 32.45 dreq input timing............................................................................................... 977 figure 32.46 drak ou tput timing............................................................................................ 977 figure 32.47 tc k input timing.................................................................................................. 978 figure 32.48 trst input timing (res et hold)........................................................................... 979 figure 32.49 h-udi data transfer timing................................................................................. 979 figure 32.50 asemd0 input timing.......................................................................................... 979 figure 32.51 lcdc ac specification......................................................................................... 981 figure 32.52 siomclk input timing........................................................................................ 982 figure 32.53 siof transmit/receive timing (master mode 1: fall sampling time) ............... 983 figure 32.54 siof transmit/r eceive timing (master mode 1: rise sampling time)............... 983 figure 32.55 siof transmit/receive timing (master mode 2: fall sampling time) ............... 984 figure 32.56 siof transmit/r eceive timing (master mode 2: rise sampling time)............... 984 figure 32.57 siof transmit/receive timing (slave mode 1 and slave mode 2)...................... 985 figure 32.58 usb clock timing................................................................................................. 985 figure 32.59 afeif modu le ac timing .................................................................................... 988
rev.6.00 mar. 27, 2009 page xlviii of lvi rej09b0254-0600 figure 32.60 output load circuit ............................................................................................... 989 figure 32.61 load capacita nce vs. delay time.......................................................................... 990 appendix d package dimensions figure d.1 package dimensio ns (prqp0240k c-b).............................................................. 1031 figure d.2 package dimensio ns (plbg0240ja-a) .............................................................. 1032
rev.6.00 mar. 27, 2009 page xlix of lvi rej09b0254-0600 tables section 1 overview and pin functions table 1.1 SH7727 features .................................................................................................... 2 table 1.2 SH7727 pin function ............................................................................................. 11 section 2 cpu table 2.1 initial register values ............................................................................................ 24 table 2.2 detail behavior under ea ch sh3-dsp mode........................................................ 33 table 2.3 destination register of dsp instructions............................................................... 34 table 2.4 source register of dsp operations ....................................................................... 35 table 2.5 dsr register bits .................................................................................................. 36 table 2.6 word data sign extension ..................................................................................... 41 table 2.7 delayed branch instructions .................................................................................. 41 table 2.8 t bit ....................................................................................................................... 42 table 2.9 immediate data re ferencing.................................................................................. 42 table 2.10 absolute address referencing ............................................................................... 43 table 2.11 displacement refe rencing ..................................................................................... 43 table 2.12 addressing modes and effective ad dresses for cpu instructions ........................ 44 table 2.13 overview of data transfer instructions ................................................................. 48 table 2.14 cpu instruction formats........................................................................................ 55 table 2.15 double data transfer in struction formats ............................................................. 59 table 2.16 single data transfer in struction formats .............................................................. 60 table 2.17 a-field parallel data tran sfer instructions............................................................ 61 table 2.18 b-field alu operation instructions and multiply instructions ............................ 62 table 2.19 cpu instruction types ........................................................................................... 65 table 2.20 data transfer in structions ...................................................................................... 69 table 2.21 arithmetic operation instructions.......................................................................... 71 table 2.22 logic operation instructions.................................................................................. 73 table 2.23 shift instructions .................................................................................................... 74 table 2.24 branch instructions ................................................................................................ 75 table 2.25 system control in structions ................................................................................... 76 table 2.26 added cpu system cont rol instructions............................................................... 81 table 2.27 double data transfer instructions ......................................................................... 83 table 2.28 single data transfer instructions........................................................................... 84 table 2.29 correspondence between dsp data tran sfer operands and registers.................. 85 table 2.30 dsp operation instru ction formats ....................................................................... 86 table 2.31 correspondence between dsp instruc tion operands and registers....................... 87 table 2.32 dsp operation instructions.................................................................................... 88 table 2.33 dc bit update definitions ..................................................................................... 94 table 2.34 examples of nopx and nopy instruction codes ................................................ 96
rev.6.00 mar. 27, 2009 page l of lvi rej09b0254-0600 section 3 memory management unit (mmu) table 3.1 register config uration ........................................................................................... 103 table 3.2 access states designated by d, c, and pr bits..................................................... 110 section 4 exception handling table 4.1 register config uration ........................................................................................... 131 table 4.2 exception event vectors ........................................................................................ 133 table 4.3 exception c odes..................................................................................................... 136 table 4.4 types of re set........................................................................................................ 141 section 5 cache table 5.1 cache specifica tions .............................................................................................. 149 table 5.2 lru and way repl acement................................................................................... 151 table 5.3 register config uration ........................................................................................... 151 table 5.4 lru and way replacement (w hen w2lock=1)................................................. 153 table 5.5 lru and way replacement (w hen w3lock=1)................................................. 153 table 5.6 lru and way replacement (when w2 lock=1 and w3lock=1) .................... 154 section 6 x/y memory table 6.1 x/y memory speci fications................................................................................... 161 section 7 interrupt controller (intc) table 7.1 pin configuration ................................................................................................... 167 table 7.2 register config uration ........................................................................................... 168 table 7.3 irl3 to irl0 pins and interrupt levels................................................................. 171 table 7.4 interrupt exception handling sources and priority (irq mode)........................... 174 table 7.5 interrupt exception handling sources and priority (irl mode) ........................... 176 table 7.6 interrupt level and intevt code ........................................................................ 178 table 7.7 interrupt request sources and ipra to iprg........................................................ 179 table 7.8 interrupt response time ........................................................................................ 200 section 8 user break controller table 8.1 register config uration ........................................................................................... 205 table 8.2 data access cycle addresses and oper and size comparison conditions ............ 223 section 9 power-down modes and software reset table 9.1 power-down m odes............................................................................................... 234 table 9.2 pin configuration ................................................................................................... 235 table 9.3 register config uration ........................................................................................... 235 table 9.4 register states in standby mode............................................................................ 244
rev.6.00 mar. 27, 2009 page li of lvi rej09b0254-0600 section 10 on-chip oscillation circuits table 10.1 clock pulse generator pi ns and functions............................................................. 261 table 10.2 register config uration ........................................................................................... 261 table 10.3 clock operating modes.......................................................................................... 262 table 10.4 available combination of clock mode and frqcr values................................. 264 table 10.5 register config uration ........................................................................................... 272 section 11 extend clock pulse generator for usb (excpg) table 11.1 pin configuration ................................................................................................... 280 table 11.2 register config uration ........................................................................................... 280 section 12 bus state controller (bsc) table 12.1 pin configuration ................................................................................................... 286 table 12.2 register config uration ........................................................................................... 288 table 12.3 physical address space map ................................................................................. 290 table 12.4 correspondence between external pins (md4 and md3) and memory bus widt h in area0 ............................................................................. 291 table 12.5 SH7727 and pcmcia pins.................................................................................... 292 table 12.6 32-bit external device/big endian access and data a lignment .......................... 316 table 12.7 16-bit external device/big endian access and data a lignment .......................... 317 table 12.8 8-bit external device/big endian access and data alignment ............................ 318 table 12.9 32-bit external device/little endian access and data alignment ....................... 319 table 12.10 16-bit external device/little endian access and data alignment ....................... 320 table 12.11 8-bit external device/little endian access and data a lignment .......................... 321 table 12.12 relationship between synchronou s dram type, bus wi dth and amx ................ 334 table 12.13 relationship between lsi address pins and synchronous dram ad dress pins ........................................................................ 335 section 13 li bus state controller (lbsc) table 13.1 register config uration ........................................................................................... 367 section 14 direct memo ry access controller (dmac) table 14.1 pin configuration ................................................................................................... 382 table 14.2 dmac registers .................................................................................................... 382 table 14.3 selecting external request m odes with the rs bits.............................................. 400 table 14.4 selection of on-chip module request modes using rs3 to rs0 bits ................. 401 table 14.5 dma transfers ...................................................................................................... 405 table 14.6 relationship of request mo des and bus modes .................................................... 416 table 14.7 register config uration ........................................................................................... 432 table 14.8 transfer conditions and register settin gs for transfer between on-chip a/d converter and extern al memory ............................................................................ 438
rev.6.00 mar. 27, 2009 page lii of lvi rej09b0254-0600 table 14.9 dmac sate after the four th transfer ends........................................................... 439 table 14.10 transfer conditions and register settin gs for transfer between external memory and scif transmitter .............................................................................. 440 section 15 timer (tmu) table 15.1 tmu register conf iguration ................................................................................. 445 table 15.2 tmu interrupt sources .......................................................................................... 454 section 16 realtime clock (rtc) table 16.1 rtc pin configur ation .......................................................................................... 459 table 16.2 rtc register s ........................................................................................................ 460 table 16.3 day-of-week codes (rwkcnt) .......................................................................... 463 table 16.4 day-of-week codes (rwkar)............................................................................. 467 table 16.5 recommended oscillator circuit consta nts (recommended values) ................... 477 section 17 serial commu nication interface (sci) table 17.1 sci pins.................................................................................................................. 485 table 17.2 registers................................................................................................................. 486 table 17.3 scsmr settin gs..................................................................................................... 501 table 17.4 bit rates and scbrr settings in as ynchronous mode (1)................................... 502 table 17.4 bit rates and scbrr settings in as ynchronous mode (2)................................... 502 table 17.4 bit rates and scbrr settings in as ynchronous mode (3)................................... 503 table 17.4 bit rates and scbrr settings in as ynchronous mode (4)................................... 503 table 17.4 bit rates and scbrr settings in as ynchronous mode (5)................................... 504 table 17.4 bit rates and scbrr settings in as ynchronous mode (6)................................... 504 table 17.4 bit rates and scbrr settings in as ynchronous mode (7)................................... 505 table 17.5 bit rates and scbrr settings in clock synchronous mode ................................ 506 table 17.6 maximum bit rates for various frequencies with baud rate generator (asynchronous mo de)............................................................................................ 507 table 17.7 maximum bit rates during external cl ock input (asynchronous mode) ............. 508 table 17.8 maximum bit rates during external clock input (clock synchronous mode)..... 508 table 17.9 serial mode register settings an d sci communication formats .......................... 510 table 17.10 scsmr and scscr settings and sci clock source sel ection ............................ 510 table 17.11 serial communication formats (asynchronous mode) ......................................... 512 table 17.12 receive error conditions a nd sci opera tion ........................................................ 520 table 17.13 sci interrupt sources ............................................................................................. 538 table 17.14 scssr status flags and transf er of receive data................................................ 539 section 18 smart card interface table 18.1 sci pins.................................................................................................................. 545 table 18.2 registers................................................................................................................. 545
rev.6.00 mar. 27, 2009 page liii of lvi rej09b0254-0600 table 18.3 register settings for the sm art card inte rface....................................................... 551 table 18.4 relationship of n to cks1 and cks0 .................................................................... 553 table 18.5 examples of bit rate b (bit/s) for scbrr settings (n = 0).................................. 553 table 18.6 examples of scbrr settings for bit rate b (bit/s) (n = 0).................................. 553 table 18.7 maximum bit rates for frequencies (s mart card interf ace mode)....................... 554 table 18.8 register set values and sck0 pin......................................................................... 554 table 18.9 smart card mode operating stat e and interrupt sources ...................................... 561 section 19 serial communicati on interface with fifo (scif) table 19.1 scif pins ............................................................................................................... 568 table 19.2 registers................................................................................................................. 569 table 19.3 scsmr2 settings................................................................................................... 581 table 19.4 bit rates and scbrr2 settings............................................................................. 581 table 19.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mo de)............................................................................................ 585 table 19.6 scsmr2 settings and scif transmit/rece ive ..................................................... 589 table 19.7 settings for scsmr2 and scscr2 and sele ction of clock source of scif ........ 590 table 19.8 serial transmit/recei ve format s ........................................................................... 590 table 19.9 scif interrupt sources........................................................................................... 600 section 20 serial io (siof) table 20.1 siof pin list.......................................................................................................... 607 table 20.2 siof register conf iguration .................................................................................. 607 table 20.3 examples of siof clock frequency...................................................................... 630 table 20.4 serial transmit mode............................................................................................. 632 table 20.5 frame length ......................................................................................................... 633 table 20.6 transmit data so und mode ................................................................................... 635 table 20.7 receive data so und mode ..................................................................................... 635 table 20.8 control data channel numb er establishment ....................................................... 636 table 20.9 transmit request su bmit conditio n ...................................................................... 639 table 20.10 receive request subm it condition ........................................................................ 640 table 20.11 transmit or recei ve reset ..................................................................................... 645 table 20.12 siof interrupt factors............................................................................................ 646 table 20.13 setting conditions for the transmit or receive interr upt flag .............................. 647 section 21 analog front end interface (afeif) table 21.1 pins for afe interface............................................................................................ 659 table 21.2 afeif regist ers..................................................................................................... 659 table 21.3 telephone number and data.................................................................................. 669
rev.6.00 mar. 27, 2009 page liv of lvi rej09b0254-0600 section 22 usb pin multiplex controller table 22.1 pin configuration (digital tr ansceiver signal)...................................................... 681 table 22.2 pin configuration (analog tr ansceiver signal) ..................................................... 681 table 22.3 pin configuration (power control sign al).............................................................. 682 table 22.4 register config uration ........................................................................................... 682 section 23 usb function controller table 23.1 pin configuration an d functions............................................................................ 692 table 23.2 usb function module registers............................................................................ 693 table 23.3 command decoding on a pplication side .............................................................. 717 section 24 usb host module table 24.1 pin configuration ................................................................................................... 726 table 24.2 register config uration ........................................................................................... 727 section 25 lcd controller table 25.1 pin configuration ................................................................................................... 765 table 25.2 register config uration ........................................................................................... 765 table 25.3 limits on the resolution of rotated displays, burst length, and connected memory (3 2-bit bus sd ram) ...................................................... 792 table 25.4 limits on the resolution of rotated displays, burst length, and connected memory (1 6-bit bus sd ram) ...................................................... 795 table 25.5 available power-supply control-sequence pe riods at typical frame rates ........ 805 table 25.6 lcdc operating modes ........................................................................................ 806 table 25.7 lcd module power-su pply stat es ........................................................................ 806 section 26 pin function controller (pfc) table 26.1 list of multiple xed pins ......................................................................................... 821 table 26.2 pin function controlle r registers .......................................................................... 826 section 27 i/o ports table 27.1 pin function controlle r registers .......................................................................... 846 table 27.2 read/write operation of the ports a to c, e, j, k data register .......................... 847 table 27.3 read/write operation of the port d data register (pddr) .................................. 849 table 27.4 read/write operation of the ports f, m data register (pfdr, pmdr) ............... 850 table 27.5 read/write operation of the port g data register (pgdr) .................................. 851 table 27.6 read/write operation of the port h data register (phdr) .................................. 853 table 27.7 read/write operation of the port l data register (pldr)................................... 854 table 27.8 read/write operation of the sc po rt data register (scpdr) .............................. 856
rev.6.00 mar. 27, 2009 page lv of lvi rej09b0254-0600 section 28 a/d converter table 28.1 a/d co nverter pins ................................................................................................ 8 59 table 28.2 a/d converter re gisters ........................................................................................ 860 table 28.3 analog input channels and a/d data regi sters .................................................... 861 table 28.4 a/d conversion time (single mode) .................................................................... 874 table 28.5 analog input pin ratings ....................................................................................... 878 table 28.6 relationship between access size and read data ................................................. 878 section 29 d/a converter table 29.1 d/a converter pins ................................................................................................ 880 table 29.2 d/a converter re gisters ........................................................................................ 880 section 30 pc card controller (pcc) table 30.1 pc card controller registers ................................................................................. 887 table 30.2 features of the pcmc ia interface......................................................................... 888 table 30.3 pcmcia support interface.................................................................................... 904 section 31 user-debugging interface (h-udi) table 31.1 h-udi registers..................................................................................................... 917 table 31.2 h-udi commands ................................................................................................. 918 table 31.3 correspondence between SH7727 pins and boundary-scan register ................... 919 table 31.4 reset configur ation................................................................................................ 926 section 32 electrical characteristics table 32.1 absolute maximum ratings................................................................................... 929 table 32.2 dc characteristic s (1) ............................................................................................ 931 table 32.2 dc characteristic s (2) ............................................................................................ 933 table 32.3 permitted output cu rrent values ........................................................................... 934 table 32.4 maximum operating freq uencies (1 ) .................................................................... 936 table 32.4 maximum operating freq uencies (2 ) .................................................................... 936 table 32.5 clock timing (1).................................................................................................... 937 table 32.6 clock timing (2).................................................................................................... 938 table 32.7 clock timing (3).................................................................................................... 939 table 32.8 clock timing (4).................................................................................................... 940 table 32.9 control signal timing............................................................................................ 946 table 32.10 bus timing............................................................................................................. 949 table 32.11 peripheral module si gnal timing .......................................................................... 975 table 32.12 h-udi-related pin timing .................................................................................... 978 table 32.13 lcdc timing ........................................................................................................ 980 table 32.14 siof module signa l timing.................................................................................. 982 table 32.15 usb module signa l timing................................................................................... 985
rev.6.00 mar. 27, 2009 page lvi of lvi rej09b0254-0600 table 32.16 usb electrical characteris tics (full-speed) .......................................................... 986 table 32.17 usb electrical characteris tics (low-speed) ......................................................... 986 table 32.18 afeif module sign al timing ............................................................................... 987 table 32.19 a/d converter char acteristics ............................................................................... 991 table 32.20 d/a converter char acteristics ............................................................................... 991 appendix a pin functions table a.1 pin functio ns.......................................................................................................... 993 table a.2 treatment of unused pins ...................................................................................... 999 table a.3 pin status (normal memo ry/little endi an) ....................................................... 1004 table a.4 pin status (normal memo ry/big endi an) .......................................................... 1006 table a.5 pin status (burst rom/ little endian ) ............................................................... 1008 table a.6 pin status (burst ro m/big endian) .................................................................. 1010 table a.7 pin status (synchronous dr am/little endi an) ................................................ 1012 table a.8 pin status (synchronous dr am/big endi an) ................................................... 1013 table a.9 pin status (pcmcia/l ittle endian )................................................................... 1014 table a.10 pin status (pcmcia/ big endian )...................................................................... 1016 appendix b control registers table b.1 memory-mapped control regi sters (address map).......................................... 1019 appendix c product lineup table c.1 SH7727 group prod uct lineup .......................................................................... 1029
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 1 of 1036 rej09b0254-0600 section 1 overview and pin functions 1.1 features the SH7727 is a single-chip risc microprocessor that integrates a 32-bit risc-type superh risc engine architecture cpu with digital signal processing (dsp) extension as its core that has a cache memory, an on-chip x/y memory, and a memory management unit (mmu) as well as peripheral functions required for system configuration. the SH7727 includes data protection, virtual memory, and other functions provided by incorporating an mmu into a superh series microprocessor (sh-1 or sh-2). the SH7727 chip has the on-chip x/y memory w ith large capacitance, on-chip dsp module, and emulator support. the provision of on-chip dsp functions enables applications that previously required the use of two chips?a microprocesso r and a dsp?to be implemented with a single chip. high-speed data transfers with a direct me mory access controller (dmac) and an external memory access support function enables dire ct connection to each memory. the SH7727 microprocessor also supports an infrared communication function, a stereo audio recording and playback function, a usb host controller, a function controller, an lcd controller, a pcmcia interface, an a/d converter, and a d/a converter. the usb host controller and lcd controller have bus master functions, so that data supplied from an external memory (area 3) can be freely pr ocessed. because the usb host controller, in particular, conforms to open hci standards, it is extremely easy to transfer data from the pc of a device driver or other devices. also, low-power operation suitable for battery operation is possible because the lcd controller continues to display even in sleep mode. an internal usb transceiver is also provided, eliminating the need for attachments. a powerful built-in power management function keeps power consumption low, even during high- speed operation. in particular, power consumption can be significantly reduced by halting the x/y memory. because the lsi operates at a maximum speed eight times of the speed at which the system operates, it is ideal for electronic devices , which require both high speed and low power consumption. the features of this lsi are listed in table 1.1. th e specifications of this lsi are listed in table 1.2.
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 2 of 1036 rej09b0254-0600 table 1.1 SH7727 features item features cpu ? original renesas superh architecture ? object code level compatible with sh-1, sh-2 and sh-3 ? 32-bit internal data bus ? general-register ? sixteen 32-bit general registers (eight 32-bit shadow registers) ? eight 32-bit control registers ? four 32-bit system registers ? risc-type instruction set ? instruction length: 16-bit fixed length to improve code efficiency ? load-store architecture ? delayed branch instructions ? instruction set based on c language ? instruction execution time: one inst ruction/cycle for basic instructions ? logical address space: 4 gbytes ? space identifier asid: 8 bits, 256 logical address space ? five-stage pipeline
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 3 of 1036 rej09b0254-0600 item features dsp ? mixture of 16-bit and 32-bit instructions ? 32-/40-bit internal data bus ? multiplier, alu, barrel shifter and dsp register ? 16 bits x 16 bits 32-bit one cycle multiplier ? large dsp data register ? six 32-bit data registers ? two 40-bit data registers ? extended harvard architecture for dsp data bus ? two data buses ? one instruction bus ? max. four parallel operations: al u, multiply and two load or store ? two addressing units to generate addresses for two memory access ? dsp data addressing modes: increment, indexing (with or without modulo addressing) ? zero overhead repeat loop control ? conditional execution instructions ? user-dsp mode and privileged-dsp mode clock pulse generator (cpg) ? clock mode: an input clock can be selected from the external input (extal or ckio) or crystal resonator. ? three types of clocks generated: ? cpu clock: 1?16 times the input clock ? bus clock: 1?4 times the input clock ? peripheral clock: 1/4?4 times the input clock ? power-down modes: ? sleep mode ? standby mode ? module standby mode (x/y memory standby enabled) ? one-channel watchdog timer
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 4 of 1036 rej09b0254-0600 item features memory management unit (mmu) ? 4 gbytes of address space, 256 address spaces (asid 8 bits) ? page unit sharing ? supports multiple page sizes: 1 kbytes or 4 kbytes ? 128-entry, 4-way set associative tlb ? supports software selection of replacement method and random- replacement algorithms ? contents of tlb can directly be accessed according to the address mapping cache memory ? 16-kbyte cache, mixed instruction/data ? 256 entries, 4-way set associative, 16-byte block length ? write-back, write-through, least rec ently used (lru) replacement algorithm ? 1-stage write-back buffer ? maximum 2 ways of the cache can be locked x/y memory ? user-selectable mapping mechanism ? fixed mapping for mission-critical realtime applications ? automatic mapping through tlb for easy to use ? 3 independent read/write ports ? 8-/16-/32-bit access from the cpu ? maximum two 16-bit accesses from the dsp ? 8-/16-/32-bit access from the dmac ? 8-kbyte ram for x and y memory individually interrupt controller (intc) ? 7 external interrupt pins (nmi, irq5?irq0) ? on-chip peripheral interrupts: set priority levels for each module user break controller (ubc) ? 2 break channels ? addresses, data values, type of access, and data size can all be set as break conditions ? supports a sequential break function
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 5 of 1036 rej09b0254-0600 item features bus state controller (bsc) ? physical address space divided into six areas (area 0, areas 2 to 6), each of up to 64 mbytes, with the following features settable for each area: ? bus size (8, 16, or 32 bits) ? number of wait cycles (hardware wait function also waited) ? direct connection of sram, synchronous dram, and burst rom possible by designating memory to be connected to each area ? supports pcmcia interface (2 channels) ? chip select signals (cs0, cs2?cs6) for relevant area ? synchronous dram refresh function ? programmable refresh interval ? supports cas-before-ras refresh and self-refresh modes ? supports power-down dram ? synchronous dram burst access function ? big endian or little endian can be specified li bus state controller (lbsc) ? bus state controller for lcdc or usb host ? supports synchronous dram ? synchronous dram access function (area 3) user debug interface (h-udi) ? e10a emulator support ? pin arrangement conforming to jtag specification ? realtime branch trace timer (tmu) ? 3-channel auto-reload-type 32-bit timer ? choice of six counter input clocks ? maximum resolution: 2 mhz realtime clock (rtc) ? built-in clock, calendar functions, and alarm functions ? on-chip 32-khz crystal oscillator ci rcuit with a maximum resolution (cycle interrupt) of 1/256 second serial communi- cation interface (sci) ? asynchronous mode or clock synchronous mode can be selected ? full-duplex communication ? supports smart card interface
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 6 of 1036 rej09b0254-0600 item features serial i/o (siof) ? synchronous 16 step, 8/16/32 bit word fifo for transmission/reception ? supports 8-bit/16-bit mono/ster eo sound playback or recording ? dma can be transferred ? supports frame sync signal serial communi- cation interface (scif) ? 16-byte fifo for transmission/reception ? dma can be transferred ? on-chip modem control function direct memory access controller (dmac) ? 4 channels ? burst mode and cycle-steal mode ? external request operating mode ? 1-channel 16-bit compare match timer pc card controller ? supports control signals for one slot ? interchangeable with sh7709 when not in use (2 slots) usb host controller (usbh) ? conforms to ohci rev. 1.0 ? usb rev. 1.1 compatible ? up to 127 endpoints ? supports int/bulk/control/iso modes ? bus master controller (can access area 3 synchronous dram) ? 2 ports with analog transceiver (1of 2 is common with usb function) ? external clock input function usb function controller (usbf) ? usb rev. 1.1 compatible ? up to 4 endpoints ? supports int/bulk/control modes (iso mode not supported) ? 1 port with analog transceiver (common with host), 12 mbps only ? external clock input function
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 7 of 1036 rej09b0254-0600 item features lcd controller (lcdc) ? from 16 x 1 to 1024 x 1024 pixels can be supported ? 4/8/15/16 bpp (bit per pixel) color modes ? 1/2/4/6 bpp (bit per pixel) gray scale ? 8-bit frame rate controller ? tft/dstn/stn ? signal polarity setting function ? hardware panel rotation ? power control function ? selectable clock source (lclk, bus clock (b ), or peripheral clock (p )) afe i/f ? st7550 direct interface ? telephone line control ? 128-word fifo for transfer ? 128-word fifo for receive i/o port ? thirteen 8-bit i/o ports a/d converter (adc) ? 10 bits 4 lsb, 6 channels ? conversion time: 15 s ? input range: 0?vcc (max. 3.6 v) d/a converter (dac) ? 8 bits 4 lsb, 2 channels ? conversion time: 10 s ? output range: 0?vcc (max. 3.6 v) product lineup power supply voltage SH7727 i/o internal operating frequency model name package 160 mhz products 3.0 v to 3.6 v 1.70 v to 2.05 v 160 mhz hd6417727f160c 240-pin plastic hqfp (prqp0240kc-b) hd6417727bp160c 240-pin csp (plbg0240ja-a) 100 mhz products 2.6 v to 3.6 v 1.60 v to 2.05 v 100 mhz hd6417727f100c 240-pin plastic hqfp (prqp0240kc-b) hd6417727bp100c 240-pin csp (plbg0240ja-a)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 8 of 1036 rej09b0254-0600 1.2 block diagram superh cpu core dsp core internal sram (xy ram) instruction/data for cpu/dsp 16 kbytes cache access controller (ccn) serial/ smart card (sci) real time clock (rtc) timer (tmu) bridge analog front end interface (afeif) 2.4-kbyte line buffer sram lcd display controller (lcdc) 512-byte pallet sram usb host controller (usbh) li bus state controller (lbsc) arbitration audio codec interface (siof) pc card controller (pcc) usb function controller (usbf) bus state controller (bsc) 512-byte sram 128-byte sram 288-byte sram internal bus (i bus) peripheral bus (p bus) peripheral bus 1 (p1 bus) peripheral bus 2 (p2 bus) li bus internal bus 2 (i2 bus) cpu bus (l bus) direct memory access controller (dmac) interrupt controller (intc) peripheral bus controller serial communication interface (scif) a/d converter (adc) d/a converter (dac) user debug interface (h-udi) user break controller (ubc) clock pulse generator (cpg) cache memory 16 kbytes memory management unit (mmu) figure 1.1 block diagram
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 9 of 1036 rej09b0254-0600 1.3 pin description 1.3.1 pin arrangement 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ptm[5]/pint[5]/afe_txout/usb1d_txse0 ptm[6]/pint[6]/afe_rxin/usb1d_speed ptm[7]/pint[7]/afe_fs/usb1d_rcv vccq afe_sclk/usb1d_txdpls vssq afe_rlycnt /usb1d_dmns/ptk[1] afe_hc1/usb1d_dpls/ptk[0] ce2b /pte[5] ce2a /pte[4] cs6 / ce1b cs5 / ce1a/ ptk[3] cs4 /ptk[2] cs3 cs2 cs0 pte[7]/pcc0rdy/ audsync rd/ wr vccq we3 /dqmuu/ iciowr /ptk[7] vssq we2 /dqmul/ iciord /ptk[6] we1 /dqmlu/ we we0 /dqmll rd bs /ptk[4] a25 vcc a24 vss a23 a22 vccq a21 vssq a20 a19 a18 a17 a16 a15 a14 a13 vccq a12 vssq a11 a10 a9 a8 a7 a6 a5 a4 vccq a3 vssq a2 a1 a0 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 lcd15/ptm[3]/pint[10] lcd14/ptm[2]/pint[9] lcd13/ptm[1]/pint[8] lcd12/ptm[0] status0/ptj[6] status1/ptj[7] cl2/pth[7] vssq ckio vccq txd0/scpt[0] sck0/scpt[1] txd_sio/scpt[2] siomclk/scpt[3] txd2/scpt[4] sck_sio/scpt[5] siofsync/scpt[6] rxd0/scpt[0] rxd_sio/scpt[2] vss rxd2/scpt[4] vcc scpt[7]/ cts2 /irq5 lcd11/ptc[7]/pint[3] lcd10/ptc[6]/pint[2] lcd9/ptc[5]/pint[1] vssq lcd8/ptc[4]/pint[0] vccq lcd7/ptd[3] lcd6/ptd[2] lcd5/ptc[3] lcd4/ptc[2] lcd3/ptc[1] lcd2/ptc[0] lcd1/ptd[1] lcd0/ptd[0] dreq0 /ptd[4] lclk/uclk/ptd[6] resetp ca md3 md4 scan_testen avcc_usb usb1_p(analog) usb1_m(analog) avss_usb usb2_p(analog) usb2_m(analog) avcc-usb avss an[2]/ptl[2] an[3]/ptl[3] an[4]/ptl[4] an[5]/ptl[5] avcc an[6]/ptl[6]/da[1] an[7]/ptl[7]/da[0] avss sh-7727 prqp0240kc-b (top view) vcc-rtc xtal2 extal2 vss-rtc md1 md2 nmi irq0/ irl0 /pth[0] irq1/ irl1 /pth[1] irq2/ irl2 /pth[2] irq3/ irl3 /pth[3] irq4/pth[4] vepwc vcpwc md5 breq back vssq ckio2 vccq d31/ptb[7] d30/ptb[6] d29/ptb[5] d28/ptb[4] d27/ptb[3] d26/ptb[2] d25/ptb[1] d24/ptb[0] vssq d23/pta[7] vccq d22/pta[6] d21/pta[5] d20/pta[4] vss d19/pta[3] vcc d18/pta[2] d17/pta[1] d16/pta[0] d15 vssq d14 vccq d13 d12 d11 d10 d9 d8 d7 d6 vssq d5 vccq d4 d3 d2 d1 d0 extal xtal vcc vss pcc0wait /pth[6]/audck vcc-pll2 cap2 vss-pll2 vss-pll1 cap1 vcc-pll1 md0 pcc0vs2 /ptf[0]/reserved pcc0vs1 /ptf[1]/reserved pccreg /ptf[2]/reserved ptf[3]/pint[11]/reserved ptf[4]/ pint[12]/tck ptf[5]/pint[13]/tdi ptf[6]/pint[14]/tms vccq ptf[7]/pint[15]/ trst vssq pcc0cd1 /ptg[0]/audata[0] vcc pcc0cd2 /ptg[1]/audata[1] vss pcc0bvd1/ptg[2]/audata[2] pcc0bvd2/ptg[3]/audata[3] ptg[4] ptg[5]/ asebrkak asemd0 iois16 /ptg[7] adtrg /pth[5] resetm wait pcc0drv /dack0 pcc0reset/drak0 pte[0]/tdo pte[3]/flm pte[6]/m_disp ptd[7]/don vcc ptd[5]/cl1 vss reserved/ptj[5] reserved/ptj[4] vccq reserved/ptj[3] vssq reserved/ cas /ptj[2] reserved/ptj[1] ras /ptj[0] cke/ptk[5] pte[1]/usb2_pwr_en pte[2]/usb1_pwr_en rts2 /usb1d_txenl usb2_ovr_current usb1_ovr_current /usbf_vbus reserved/usb1d_suspend ptm[4]/pint[4]/ afe_rdet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 vcc = 1.9 v, vss = gnd for cpu core vccq = 3.3 v, vssq = gnd for i/o buffer digital and pll gnd must be separated and isolated from the other signals the order of pin name and default pin name has no relation. please refer to pin table. figure 1.2 pin arrangement (prqp0240kc-b)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 10 of 1036 rej09b0254-0600 vcc- rtc ext al2 md1 nmi irq1 vep wc back d31 d27 vssq d19 d16 vccq d10 d6 d5 d4 d2 a0 an6 avss vss- rtc xtal2 md2 vcp wc vssq d30 d26 d22 vss d17 d14 d11 vccq d1 d3 d0 a2 an5 avcc avcc_ usb irq0 irq3 md5 ckio2 d29 d24 vccq d21 d18 vssq d12 d8 vssq d7 vssq a3 an3 an7 an2 irq2 irq4 breq vccq d28 d25 d23 d20 vcc d15 d13 d9 a7 a5 a1 a4 avss an4 usb 2_m usb 2_p a9 a8 vccq a6 avss_ usb usb 1_m usb 1_p avcc_ usb a12 vssq a11 a10 scan_ testen md4 md3 ca a15 a14 a13 vccq res etp lclk dre q0 lcd0 a19 a18 a17 a16 lcd1 lcd2 lcd4 lcd3 a21 vccq vssq a20 vccq lcd5 lcd6 lcd7 a23 vss a24 a22 lcd10 lcd9 lcd8 vssq a25 vcc bs rd rxd2 vcc scpt7 lcd11 we0 we1 we2 vssq siof sync rxd0 rxd_ sio vss we3 vccq rd/ wr pte7 txd_ sio siom clk txd2 sck_ sio cs0 cs2 cs3 cs4 ckio sta tus1 txd0 sck0 cs5 cs6 vssq ce2b cl2 lcd14 vssq vccq md0 ptf3 vccq vcc pcc0 bvd1 asem d0 rese tm pcc0 reset ptd7 ptj5 vssq ptj1 afe_ hc1 ptm6 afe_ rlycnt sta tus0 lcd12 cap1 vss- pll2 vcc- pll1 pcc reg ptf6 pcc0 cd1 pcc0 bvd2 ptg5 adt rg pte0 vcc ptj4 cas cke ce2a vccq afe_ sclk lcd13 extal vss xtal vcc- pll2 pcc0 vs1 ptf5 vssq vss ptg4 wait pte3 ptd5 vccq pte2 usb1d_ suspend usb2_ ovr_ current usb1_ ovr_ current ptm5 ptm7 lcd15 vcc pcc0 wait cap2 vss- pll1 pcc0 vs2 ptf4 ptf7 pcc0 cd2 iois16 pcc0 drv pte6 vss ptj3 ras pte1 rts2 ptm4 a 12345678910111213141516171819 b c d e f g h j k l m n p r t u v w SH7727 plbg0240ja-a (top view) figure 1.3 pin arrangement (plbg0240ja-a)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 11 of 1036 rej09b0254-0600 1.3.2 pin functions table 1.2 SH7727 pin function pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 1 a1 vcc-rtc * 1 ? rtc power supply (1.9 v) 2 b4 xtal2 o on-chip rtc crystal oscillator pin 3 a2 extal2 i on-chip rtc crystal oscillator pin 4 b3 vss-rtc * 1 ? rtc power supply (0 v) 5 a3 md1 i clock mode setting 6 b5 md2 i clock mode setting 7 a4 nmi i nonmaskable interrupt request 8 c4 irq0/ irl0 /pth[0] i/i/i external interrupt / external interrupt / input port h 9 a5 irq1/ irl1 /pth[1] i/i/i external interrupt / external interrupt / input port h 10 d4 irq2/ irl2 /pth[2] i/i/i external interrupt / external interrupt / input port h 11 c5 irq3/ irl3 /pth[3] i/i/i external interrupt / external interrupt / input port h 12 d5 irq4/pth[4] i/i external interrupt request / input port h 13 a6 vepwc o lcd panel v ee control 14 b6 vcpwc o lcd panel v cc control 15 c6 md5 i endian setting 16 d6 breq i bus request 17 a7 back o bus acknowledge 18 b7 vssq ? input/output power supply (0 v) 19 c7 ckio2 o system clock output 20 d7 vccq ? input/output power supply (3.3 v) 21 a8 d31/ptb[7] io/io data bus / i/o port b 22 b8 d30/ptb[6] io/io data bus / i/o port b 23 c8 d29/ptb[5] io/io data bus / i/o port b 24 d8 d28/ptb[4] io/io data bus / i/o port b 25 a9 d27/ptb[3] io/io data bus / i/o port b 26 b9 d26/ptb[2] io/io data bus / i/o port b 27 d9 d25/ptb[1] io/io data bus / i/o port b
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 12 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 28 c9 d24/ptb[0] io/io data bus / i/o port b 29 a10 vssq ? input/output power supply (0 v) 30 d10 d23/pta[7] io/io data bus / i/o port a 31 c10 vccq ? input/output power supply (3.3 v) 32 b10 d22/pta[6] io/io data bus / i/o port a 33 c11 d21/pta[5] io/io data bus / i/o port a 34 d11 d20/pta[4] io/io data bus / i/o port a 35 b11 vss ? power supply (0 v) 36 a11 d19/pta[3] io/io data bus / i/o port a 37 d12 vcc ? power supply (1.9 v) 38 c12 d18/pta[2] io/io data bus / i/o port a 39 b12 d17/pta[1] io/io data bus / i/o port a 40 a12 d16/pta[0] io/io data bus / i/o port a 41 d13 d15 io data bus 42 c13 vssq ? input/output power supply (0 v) 43 b13 d14 io data bus 44 a13 vccq ? input/output power supply (3.3 v) 45 d14 d13 io data bus 46 c14 d12 io data bus 47 b14 d11 io data bus 48 a14 d10 io data bus 49 d15 d9 io data bus 50 c15 d8 io data bus 51 c17 d7 io data bus 52 a15 d6 io data bus 53 c16 vssq ? input/output power supply (0 v) 54 a16 d5 io data bus 55 b15 vccq ? input/output power supply (3.3 v) 56 a17 d4 io data bus 57 b17 d3 io data bus 58 a18 d2 io data bus 59 b16 d1 io data bus 60 b18 d0 io data bus
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 13 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 61 a19 a0 o address bus 62 d18 a1 o address bus 63 b19 a2 o address bus 64 c18 vssq ? input/output power supply (0 v) 65 c19 a3 o address bus 66 e18 vccq ? input/output power supply (3.3 v) 67 d19 a4 o address bus 68 d17 a5 o address bus 69 e19 a6 o address bus 70 d16 a7 o address bus 71 e17 a8 o address bus 72 e16 a9 o address bus 73 f19 a10 o address bus 74 f18 a11 o address bus 75 f17 vssq ? input/output power supply (0 v) 76 f16 a12 o address bus 77 g19 vccq ? input/output power supply (3.3 v) 78 g18 a13 o address bus 79 g17 a14 o address bus 80 g16 a15 o address bus 81 h19 a16 o address bus 82 h18 a17 o address bus 83 h17 a18 o address bus 84 h16 a19 o address bus 85 j19 a20 o address bus 86 j18 vssq ? input/output power supply (0 v) 87 j16 a21 o address bus 88 j17 vccq ? input/output power supply (3.3 v) 89 k19 a22 o address bus 90 k16 a23 o address bus 91 k17 vss ? power supply (0 v) 92 k18 a24 o address bus 93 l17 vcc ? power supply (1.9 v)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 14 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 94 l16 a25 o address bus 95 l18 bs /ptk[4] o/io bus cycle start signal / i/o port k 96 l19 rd o read strobe 97 m16 we0 /dqmll o/o d7?d0 select signal / dqm (sdram) 98 m17 we1 /dqmlu/ we o/o/o d15?d8 select signal / dqm (sdram) / pcmcia we 99 m18 we2 /dqmul/ iciord /ptk[6] o/o/ o/io d23?d16 select signal / dqm (sdram) / pcmcia i/o read / i/o port k 100 m19 vssq ? input/output power supply (0 v) 101 n16 we3 /dqmuu/ iciowr /ptk[7] o/o/ o/io d31?d24 select signal / dqm (sdram) / pcmcia i/o write / i/o port k 102 n17 vccq ? input/output power supply (3.3 v) 103 n18 rd/ wr o read/write 104 n19 pte[7]/pcc0rdy/ audsync io/i/o i/o port e / pcmcia0 ready / aud synchronization 105 p16 cs0 o chip select 0 106 p17 cs2 o chip select 2 107 p18 cs3 o chip select 3 108 p19 cs4 /ptk[2] o/io chip select 4 / i/o port k 109 r16 cs5 / ce1a /ptk[3] o/o/io chip select 5 / ce1 (area 5 pcmcia) / i/o port k 110 r17 cs6 / ce1b o/o chip select 6 / ce1 (area 6 pcmcia) 111 u17 ce2a /pte[4] o/io area 5 pcmcia card enable / i/o port e 112 r19 ce2b /pte[5] o/io area 6 pcmcia card enable / i/o port e 113 t17 afe_hc1/ usb1d_dpls/ ptk[0] o/i/io afe hardware control signal / d+ signal input / i/o port k 114 t19 afe_rlycnt / usb1d _dmns/ ptk[1] o/i/io afe relay control signal / d- signal input / i/o port k 115 r18 vssq ? input/output power supply (0 v) 116 u19 afe_sclk/ usb1d _txdpls i/o afe clock / d+ transmit output 117 u18 vccq ? input/output power supply (3.3 v)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 15 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 118 v19 ptm[7]/pint[7]/ afe_fs/ usb1d_rcv i/i/i/i input port m / port interrupt / afe frame synchronization / receive data input 119 t18 ptm[6]/pint[6]/ afe_rxin/ usb1d_speed i/i/i/o input port m / port interrupt / afe receive data / transceiver speed control 120 v18 ptm[5]/pint[5]/ afe_txout/ usb1d_txse0 i/i/o/o input port m / port interrupt / afe transmit data / se0 output 121 w19 ptm[4]/pint[4]/ afe_rdet i/i/i input port m / port interrupt / afe ringing detection 122 v16 reserved/ usb1d_suspend o/o reserved/transceiver suspend state output 123 w18 usb1_ovr_current / usbf_vbus i/i usb host 1 overcurrent detection / usb function vbus 124 v17 usb2_ovr_current i usb host 2 overcurrent detection 125 w17 rts2 / usb1d_txenl o/o scif rts pin / usb output enable pin 126 v15 pte[2]/ usb1_pwr_en io/o i/o port e / usb1 voltage control 127 w16 pte[1]/ usb2_pwr_en io/o i/o port e / usb2 voltage control 128 u16 cke/ptk[5] o/io ck enable (sdram) / i/o port k 129 w15 ras /ptj[0] o/io ras for sdram / i/o port j 130 t16 reserved/ptj[1] o/io reserved / i/o port j 131 u15 reserved/ cas / ptj[2] o/o/io reserved / cas for sdram / i/o port j 132 t15 vssq ? input/output power supply (0 v) 133 w14 reserved/ptj[3] o/io reserved / i/o port j 134 v14 vccq ? input/output power supply (3.3 v) 135 u14 reserved/ptj[4] o/io reserved / i/o port j 136 t14 reserved/ptj[5] o/io reserved / i/o port j 137 w13 vss ? power supply (0 v) 138 v13 ptd[5]/cl1 io/o i/o port d / lcd line clock 139 u13 vcc ? power supply (1.9 v) 140 t13 ptd[7]/don io/o i/o port d / lcd display on 141 w12 pte[6]/m_disp io/o i/o port e / lcd alternating signal / disp signal
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 16 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 142 v12 pte[3]/flm io/o i/o port e / lcd frame line marker 143 u12 pte[0]/tdo io/o i/o port e / test data output 144 t12 pcc0reset/ drak0 o/o pcc reset / dma request receive 145 w11 pcc0drv /dack0 o/o pcc buffer control / dma acknowledge 0 146 v11 wait i hardware wait request 147 t11 resetm i manual reset request 148 u11 adtrg /pth[5] i/i analog trigger / input port h 149 w10 iois16 /ptg[7] i/i iois16 (pcmcia) / input port g 150 t10 asemd0 i ase mode 151 u10 ptg[5]/ asebrkak i/o input port g / ase break acknowledge 152 v10 ptg[4] i input port g 153 u9 pcc0bvd2/ptg[3]/ audata[3] i/i/o pcc bvd2 pin / input port g / aud data 154 t9 pcc0bvd1/ptg[2]/ audata[2] i/i/o pcc bvd1 pin / input port g / aud data 155 v9 vss ? power supply (0 v) 156 w9 pcc0cd2 /ptg[1]/ audata[1] i/i/o pcmcia0 cd2 pin / input port g / aud data 157 t8 vcc ? power supply (1.9 v) 158 u8 pcc0cd1 /ptg[0]/ audata[0] i/i/o pcc cd1 pin / input port g / aud data 159 v8 vssq ? input/output power supply (0 v) 160 w8 ptf[7]/pint[15]/ trst i/i/i input port f / port interrupt / test reset 161 t7 vccq ? input/output power supply (3.3 v) 162 u7 ptf[6]/pint[14]/ tms i/i/i input port f / port interrupt / test mode switch 163 v7 ptf[5]/pint[13]/ tdi i/i/i input port f / port interrupt / test data input 164 w7 ptf[4]/pint[12]/ tck i/i/i input port f / port interrupt / test clock 165 t6 ptf[3]/pint[11]/ reserved i/i/o input port f / port interrupt / reserved 166 u6 pccreg /ptf[2]/ reserved o/i/o pcc reg pin / input port f/ reserved
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 17 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 167 v6 pcc0vs1 /ptf[1]/ reserved i/i/o pcc vs1 pin / input port f/ reserved 168 w6 pcc0vs2 /ptf[0]/ reserved i/i/io pcc vs2 pin / input port f/ reserved 169 t5 md0 i clock mode setting 170 u5 vcc-pll1 * 2 ? pll1 power supply (1.9 v) 171 u3 cap1 ? pll1 external capacitance pin 172 w5 vss-pll1 * 2 ? pll1 power supply (0 v) 173 u4 vss-pll2 * 2 ? pll2 power supply (0 v) 174 w4 cap2 ? pll2 external capacitance pin 175 v5 vcc-pll2 * 2 ? pll2 power supply (1.9v) 176 w3 pcc0wait /pth[6]/ audck i/i/i pcc hardware wait request / input port h / aud clock 177 v3 vss ? power supply (0 v) 178 w2 vcc ? power supply (1.9 v) 179 v4 xtal o crystal resonator 180 v2 extal i external clock / crystal resonator 181 w1 lcd15/ptm[3]/ pint[10] o/i/i lcd data output / input port m / port interrupt 182 t2 lcd14/ptm[2]/ pint[9] o/i/i lcd data output / input port m / port interrupt 183 v1 lcd13/ptm[1]/ pint[8] o/i/i lcd data output / input port m / port interrupt 184 u2 lcd12/ptm[0] o/i lcd data output / input port m 185 u1 status0/ptj[6] o/io pr ocessor status / i/o port j 186 r2 status1/ptj[7] o/io pr ocessor status / i/o port j 187 t1 cl2/pth[7] o/io lcd clock output / i/o port h 188 t3 vssq ? input/output power supply (0 v) 189 r1 ckio io system clock input/output 190 t4 vccq ? input/output power supply (3.3 v) 191 r3 txd0/scpt[0] o/o transmit data 0 / sci output port 192 r4 sck0/scpt[1] io/io serial clock 0 / sci i/o port 193 p1 txd_sio/scpt[2] o/o siof transmit data / sci output port 194 p2 siomclk/scpt[3] i/io siof clock input / sci i/o port 195 p3 txd2/scpt[4] o/o transmit data 2 / sci output port
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 18 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 196 p4 sck_sio/scpt[5] io/io siof communication clock / sci i/o port 197 n1 siofsync/scpt[6] io/io siof frame synch. / sci i/o port 198 n2 rxd0/scpt[0] i/i receive data 0 / sci input port 199 n3 rxd_sio/scpt[2] i/i siof receive data / sci input port 200 n4 vss ? power supply (0 v) 201 m1 rxd2/scpt[4] i/i receive data 2 / sci input port 202 m2 vcc ? power supply (1.9 v) 203 m3 scpt[7]/ cts2 /irq5 i/i/i sci input port / scif clear to send / external interrupt request 204 m4 lcd11/ptc[7]/ pint[3] o/io/i lcd data out / i/o port c / port interrupt 205 l1 lcd10/ptc[6]/ pint[2] o/io/i lcd data out / i/o port c / port interrupt 206 l2 lcd9/ptc[5]/ pint[1] o/io/i lcd data out / i/o port c / port interrupt 207 l4 vssq ? input/output power supply (0 v) 208 l3 lcd8/ptc[4]/ pint[0] o/io/i lcd data out / i/o port c / port interrupt 209 k1 vccq ? input/output power supply (3.3 v) 210 k4 lcd7/ptd[3] o/io lcd data out / i/o port d 211 k3 lcd6/ptd[2] o/io lcd data out / i/o port d 212 k2 lcd5/ptc[3] o/io lcd data out / i/o port c 213 j3 lcd4/ptc[2] o/io lcd data out / i/o port c 214 j4 lcd3/ptc[1] o/io lcd data out / i/o port c 215 j2 lcd2/ptc[0] o/io lcd data out / i/o port c 216 j1 lcd1/ptd[1] o/io lcd data out / i/o port d 217 h4 lcd0/ptd[0] o/io lcd data out / i/o port d 218 h3 dreq0 /ptd[4] i/i dma request / input port d 219 h2 lclk/uclk/ptd[6] i/i/i lcd clock / usb clock / input port d 220 h1 resetp i power-on reset request 221 g4 ca i hardware standby request 222 g3 md3 i area 0 bus width setting 223 g2 md4 i area 0 bus width setting 224 g1 scan_testen i test pin (pull up to vccq) 225 f4 avcc_usb ? usb analog power supply (3.3 v)
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 19 of 1036 rej09b0254-0600 pin no. (prqp0240kc-b) pin no. (plbg0240ja-a) name i/o function 226 f3 usb1_p(analog) io usb1 data i/o (plus) 227 f2 usb1_m(analog) io usb1 data i/o (minus) 228 f1 avss_usb ? usb analog power supply (0 v) 229 e4 usb2_p(analog) io usb2 data i/o (plus) 230 e3 usb2_m(analog) io usb2 data i/o (minus) 231 c3 avcc_usb ? usb analog power supply (3.3 v) 232 e1 avss ? analog power supply (0 v) 233 d3 an[2]/ptl[2] i/i a/d converter input / input port l 234 d1 an[3]/ptl[3] i/i a/d converter input / input port l 235 e2 an[4]/ptl[4] i/i a/d converter input / input port l 236 c1 an[5]/ptl[5] i/i a/d converter input / input port l 237 c2 avcc ? analog power supply (3.3 v) 238 b1 an[6]/ptl[6]/da[1] i/i/o a/d converter input / input port l / d/a converter output 239 d2 an[7]/ptl[7]/da[0] i/i/o a/d converter input / input port l / d/a converter output 240 b2 avss ? analog power supply (0 v) notes: all vcc/vss should be connected to the all system power supply (so that power is supplied at all times). 1. always supply power to the vcc- rtc, even if rtc is not being used. 2. always supply power to the vcc-pll, even if the internal pll is not being used. 3. drive high when using the user system alone, and not using an emulator or the h-udi. when this pin is low or open, resetp may be masked.
section 1 overview and pin functions rev.6.00 mar. 27, 2009 page 20 of 1036 rej09b0254-0600
section 2 cpu rev.6.00 mar. 27, 2009 page 21 of 1036 rej09b0254-0600 section 2 cpu 2.1 registers the SH7727 has the same registers as in sh-3. in addition, the SH7727 also support the same dsp-related registers seen in sh-dsp. the basi c software-accessible registers are divided into four distinct groups: ? general-purpose registers ? control registers ? system registers ? dsp registers with the exception of a number of dsp registers, all of these registers are 32-bit width. the general-purpose registers are accessi ble from the user mode, with r0 to r7 banked to provide each processor mode access to a separate set of the r0 to r7 registers (i.e. r0 to r7_bank0, and r0 to r7_bank1). in the privileged mode, the register bank (rb) bit in the status register (sr) defines which set of banked registers (r0 to r7_bank0 or r0 to r7_bank1) is accessed as general-purpose registers, and which are accessed only by the ldc/stc instructions. the control registers can be accessed by the ldc/stc instructions. the gbr, rs, re, and mod registers can also be accessed in user mode. control registers are: ? sr: status register ? ssr: saved status register ? spc: saved program counter ? gbr: global base register ? vbr: vector base register ? rs: repeat start register (dsp mode only) ? re: repeat end register (dsp mode only) ? mod: modulo register (dsp mode only) the system registers are accessed by the lds/st s instructions (the pc cannot be accessed by software, but is included here because its cont ents are saved in, and restored from, spc). the system registers are: ? mach: multiply and accumulate high register ? macl: multiply and accumulate low register ? pr: procedure register
section 2 cpu rev.6.00 mar. 27, 2009 page 22 of 1036 rej09b0254-0600 ? pc: program counter this section explains the usage of these registers in different modes. figures 2.1 and 2.2 show the register configuration in each processing mode. switching between user mode and privileged mode is carried out by means of the processing operation mode bit (md) in the status register. the dsp mode is switched by means of the dsp bit in the status register.
section 2 cpu rev.6.00 mar. 27, 2009 page 23 of 1036 rej09b0254-0600 31 r0_bank0 * 1 * 2 r1_bank0 * 2 r2_bank0 * 2 r3_bank0 * 2 r4_bank0 * 2 r5_bank0 * 2 r6_bank0 * 2 r7_bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc 0 31 r0_bank1 * 1 * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r0_bank0 * 1 * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 31 r0_bank0 * 1 * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r0_bank1 * 1 * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 (a) user mode register configuration (b) privileged mode register configuration (rb = 1) (c) privileged mode register configuration (rb = 0) notes: 1. the r0 register is used as an index register in indexed register indirect addressing mode and indexed gbr indirect addressing mode. 2. bank register 3. bank register accessed as a general register when the rb bit is set to 1 in the sr register. accessed only by ldc/stc instructions when the rb bit is cleared to 0. 4. bank register accessed as a general register when the rb bit is cleared to 0 in the sr register. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.1 register configuration in each processing mode (1)
section 2 cpu rev.6.00 mar. 27, 2009 page 24 of 1036 rej09b0254-0600 a0g a1g 32 31 a0 a1 m0 m1 x0 x1 y0 y1 dsr ms me mod 0 (d) dsp mode register configuration (dsp = 1) figure 2.2 register configuration in each processing mode (2) register values after a reset are shown in table 2.1. table 2.1 initial register values type registers initial value * general registers r0 to r15 undefined control registers sr md bit = 1, rb bit = 1, bl bit = 1, i3 to i0 = 1111 (h'f), reserved bits = 0, others undefined gbr, ssr, spc undefined vbr h'00000000 rs, re undefined mod undefined system registers mach, macl, pr undefined pc h'a0000000 dsp registers a0, a0g, a1, a1g, m0, m1, x0, x1, y0, y1 undefined dsr h'00000000 note: * initialized by a power-on or manual reset.
section 2 cpu rev.6.00 mar. 27, 2009 page 25 of 1036 rej09b0254-0600 2.1.1 general purpose registers there are sixteen 32-bit general registers (rn), designated r0 to r15. the general registers are used for data processing and address calculation. with superh microcomputer type instructions, r0 is used as an index register. with a number of instructions, r0 is the only register that can be used. r15 is used as the stack pointer (sp). in exception handling, r15 is used to reference the stack when saving and restoring the status register (sr) and program counter (pc). with dsp type instructions, eight of the sixteen general registers are used for addressing of x and y data memory and data memory (single data) that uses the l-bus. to access x memory, r4 and r5 are used as x addr ess register [ax] and r8 is used as x index register [ix]. to access y memory, r6 and r7 are us ed as y address register [ay] and r9 is used as y index register [iy]. to access single data that uses the l-bus, r2, r3, r4, and r5 are used as single data address register [as] and r8 is used as single data index register [is]. figure 2.3 shows the general purpose registers, which are identical to sh-3?s, when dsp extension is disabled. 31 r0 * 1 * 2 r1 * 2 r2 * 2 r3 * 2 r4 * 2 r5 * 2 r6 * 2 r7 * 2 r8 r9 r10 r11 r12 r13 r14 r15 0 general registers (when not in dsp mode) notes: 1. r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source register or destination register. 2. r0 to r7 are banked registers. in user mode, bank0 is used. in privileged mode, sr.rb specifies bank. sr.rb = 0; bank0 is used sr.rb = 1; bank1 is used figure 2.3 general purpose register (not in dsp mode)
section 2 cpu rev.6.00 mar. 27, 2009 page 26 of 1036 rej09b0254-0600 on the other hand, r2 to r9 registers are also used for the dsp data address calculations, see figure 2.4, when dsp extension is enabled. another symbol that represents the purpose of the registers in dsp type instruction is [ ]. 31 r0 r1 r2 [as] r3 [as] r4 [as, ax] r5 [as, ax] r6 [ay] r7 [ay] r8 [ix, is] r9 [iy] r10 r11 r12 r13 r14 r15 0 general registers (dsp mode enabled) x or y data transfer operation r4, r5 [ax]: address register set for x data memory. r8 [x]: index register for address register set ax. r6, r7 [ay]: address register set for y data memory. r9 [iy]: index register for address register set ay. single data transfer operation r2 to r5 [as]: address register set for memory. r8 [is]: index register for address register set as. figure 2.4 general purpose register (dsp mode) dsp type instructions can access x and y data me mory simultaneously. to specify addresses for x and y data memory, two address poin ter sets are prepared. these are: r8[ix], r4, r5[ax] for x memory access, and r9[iy], r6, r7[ay] for y memory access. the names (symbol) r2 to r9 are used in the assembler, but users can use other register names that represent the purpose of the register in the dsp instruction explicitly. in the assembly program, user can use an alias for the regist er. the coding in assembler is as follows. ix: .reg (r8)
section 2 cpu rev.6.00 mar. 27, 2009 page 27 of 1036 rej09b0254-0600 the name ix is the alias for r8. other aliases are as follows. ax0: .reg (r4) ax1: .reg (r5) ix: .reg (r8) ay0: .reg (r6) ay1: .reg (r7) iy: .reg (r9) as0: .reg (r4) ; this is optional. if you need another alias for single data transfer. as1: .reg (r5) ; this is optional. if you need another alias for single data transfer. as2: .reg (r2) as3: .reg (r3) is: .reg (r8) ; this is optional. if you need another alias for single data transfer. 2.1.2 control registers SH7727 has eight control registers: sr, ssr, spc, gbr, vbr, rs, re, and mod (figure 2.5). ssr, spc, gbr and vbr are the same as the sh-3 registers. the dsp mode is activated only when sr.dsp = 1. repeat start register rs, repeat end register re, and repeat counter rc (12-bit part of the sr) and repeat control bits rf0 and rf1 are new registers and control bits which are used for repeat control. modulo register mod and modulo control bits dmx and dmy in the sr are also new register and control bits. in the sr, there are six additional control bits: rc[11:0], rf0, rf1, dmx, dmy and dsp. bits dmx, dmy, rc[11:0], and rf[1:0] can be modified in supervisor mode, dsp supervisor mode, and dsp user mode. the dmx and dmy are used for modulo addressing control. if the dmx is 1 then the modulo addressing mode is effective for the x memory address pointer, ax (r4 or r5). if the dmy is 1 then it is effective for the y memory address pointer, ay (r6 or r7). however, both x and y address pointer cannot be operated under the modulo addressing mode even though both dmx and dmy bits are set. the case of dmx = dmy = 1 is reserved for future expansion. when both dmx and dmy are set simultaneousl y, the hardware will preliminary treat only address pointer as the modulo addressing mode. modulo addressing is available for x and y data transfer operation (movx and m ovy), but not for single data transfer operation (movs). the rf1 and rf0 hold information of the number of repeat steps and they are set when a setrc instruction is executed. when rf[1:0] shows 00, th e current repeat module consists of one-step instruction. when rf[1:0] = 01, it means two-step instructions. when rf[1:0] = 11, it means
section 2 cpu rev.6.00 mar. 27, 2009 page 28 of 1036 rej09b0254-0600 three-step instruction. when rf[1:0] = 10, it means the current repeat module consists of four or more instructions. although rc[11:0] and rf[1:0] can be changed by a store/load to sr, use of the dedicated manipulation instruction setrc is recommended. the sr also has a 12-bit repeat counter rc which is used for efficient loop control. repeat start register (rs) and repeat end register (re) are al so introduced for the loop control. they keep the start and end addresses of a loop (the contents of the registers, rs and re are slightly different from the actual loop start and end address). modulo register, mod is introduced to realize modulo addressing for circular data buffering. mod keeps the modulo start address (ms) and the modulo end address (me). in order to access rs, re and mod, load/store (control register) instructions for them are introduced. an example for rs is as follows: ldc rm,rs; rm rs ldc.l @rm+,rs; (rm) rs, rm+4 rm stc rs,rn; rs rn stc.l rs,@-rn; rn-4 rn, rs (rn) address set instructions for the rs and re are also prepared. ldrs @(disp,pc); disp 2 + pc rs ldre @(disp,pc); disp 2 + pc re
section 2 cpu rev.6.00 mar. 27, 2009 page 29 of 1036 rej09b0254-0600 31 0 md rc 0-0 dsp dmy dmx m q i3 i2 i1 i0 rf1 rf0 st rb bl 28 27 16 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sr (status register) md bit: processor operation mode md = 1: privileged mode md = 0: user mode rb bit: register bank bit; used to define the general registers in privileged mode. rb = 1: r0_bank1 to r7_bank1 are used as general registers. r0_bank0 to r7_bank0 accessed by ldc/stc instructions. rb = 0: r0_bank0 to r7_bank0 are used as general registers. r0_bank1 to r7_bank1 accessed by ldc/stc instructions. bl bit: block bit; used to mask exception in privileged mode. bl = 1: interrupts are masked (not accepted) bl = 0: interrupts are accepted rc [11:0]: 12-bit repeat counter dsp bit: dsp operation mode dsp = 1: dsp instructions (lds rm, dsr/a0/x0/x1/y0/y1, lds.l @rm+, dsr/a0/x0/x1/y0/y1, sts dsr/a0/x0/x1/y0/y1, rn, sts.l dsr/a0/x0/x1/y0/y1, @ ? rn, ldc rm, rs/re/mod, ldc.l @rm+, rs/re/mod, stc rs/re/mod,rn, stc.l rs/re/mod, @ ? rn, ldrs, ldre, setrc, movs, movx, movy, pxxx) are enabled. dsp = 0: all dsp instructions are treated as illegal instructions; only sh3 instructions are supported. dmy bit: modulo addressing enable for y side dmx bit: modulo addressing enable for x side q, m bit: used by div0u/s and div1 instructions. i [3:0]: 4-bit field indicating the interrupt request mask level. rf [1:0]: used for repeat control s bit: used by the mac instructions and dsp data. t bit: the movt, cmp/cond, tas, tst, bt, bf, sett, clrt and dt instructions use the t bit to indicate true (logic one) or false (logic zero). the addv/c, subv/c, div0u/s, div1, negc, shar/l, shlr/l, rotr/l and rotcr/l instructions also use the t bit to indicate a carry, borrow, overflow, or underflow. reserved bits: always read as 0, and should always be written with 0 (bit 31, bits 15 to 13). figure 2.5 control registers (1)
section 2 cpu rev.6.00 mar. 27, 2009 page 30 of 1036 rej09b0254-0600 ssr 31 0 saved status register (ssr) spc 31 0 saved program counter (spc) gbr 31 0 global base register vbr 31 0 vector base register rs 31 0 repeat start register re 31 0 repeat end register me ms 31 16 15 0 modulo register mod me: modulo end address, ms: modulo start address saved status register (ssr) stores current sr value at time of exception to indicate processor status when returning to instruction stream from exception handler. saved program counter (spc) stores current pc value at time of exception to indicate return address on completion of exception handling. global base register (gbr) stores base address of gbr-indirect addressing mode. the gbr-indirect addressing mode is used for data transfer and logical operations on the on-chip peripheral module register area. vector base register (vbr) stores base address of exception vector area. repeat start register (rs) used in dsp mode only. indicates start address of repeat loop. repeat end register (re) used in dsp mode only. indicates address of repeat loop end. modulo register (mod) used in dsp mode only. mod[31:16]: me: modulo end address, mod[15:0]: ms: modulo start address. in x/y operand address generation, the cpu compares the address with me, and if it is the same, loads ms in either the x or y operand address register (depending on bits dmx and dmy in the sr register). figure 2.5 control registers (2)
section 2 cpu rev.6.00 mar. 27, 2009 page 31 of 1036 rej09b0254-0600 2.1.3 system registers the SH7727 has four system registers, macl, mach, pr and pc (figure 2.6). mach macl 31 0 pr 31 0 pc 31 0 multiply and accumulate high and low registers (mach/l) store the results of multiplicationand accumulation operations. procedure register (pr) stores the subroutine procedure return address. program counter (pc) indicates the starting address that is four addresses ahead. figure 2.6 system registers dsr, a0, x0, x1, y0 and y1 registers are also tr eated as system registers. so, data transfer instructions between general registers and system registers are supported for them. 2.1.4 dsp registers the SH7727 has eight data registers and one control register (figure 2.7). the data registers are 32-bit width with the exception of registers a0 and a1. registers a0 and a1 include 8 guard bits (fields a0g and a1g), giving them a total width of 40 bits. three types of operations access the dsp data regi sters. first one is the dsp data. when a dsp fixed-point data operation uses a0 or a1 for source register, it uses the guard bits (bits 39 to 32). when it uses a0 or a1 for destination register, bits 39 to 32 in the guard bit are valid. when a dsp fixed-point data operation uses the dsp registers other than a0 and a1 for source register, it sign-extends the source value to bits 39 to 32. when it uses them for destination register, the bits 39 to 32 of the result is discard. second one is x and y data transfer operation, ? movx.w movy.w?. th is operation accesses the x and y memories through 16-bit x and y data buses (figure 2.8). registers to be loaded or stored by this operation are always upper 16 bits (bits 31 to 16). x0 and x1 can be destination of the x memory load and y0 and y1 can be destination of y memory load, but other register cannot be destination register of this operation.
section 2 cpu rev.6.00 mar. 27, 2009 page 32 of 1036 rej09b0254-0600 when data is read into the upper 16 bits of a re gister (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automa tically cleared. a0 and a1 can be stored to the x or y memory by this operation, but other registers cannot be stored. there are some rules to access sr by stc/ldc instruction. 1. when dsp is disabled, same as sh-3 behavior 2. when sdp supervisor mode, same as supervisor mode 3. in user dsp mode, sr can be read by stc instruction 4. in user dsp mode, ldc to sr is allowed but no dsp related bits are protected from write. table 2.2 shows detail behavior under each sh3-dsp mode.
section 2 cpu rev.6.00 mar. 27, 2009 page 33 of 1036 rej09b0254-0600 table 2.2 detail behavior under each sh3-dsp mode supervisor mode user mode dsp supervisor mode dsp user mode fields md = 1 & dsp = 0 md = 0 & dsp = 0 md = 1 & dsp = 1 md = 0 & dsp = 1 access to dsp related bits by dedicated instruction initial value after reset md s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng 1 rb s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng 1 bl s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng 1 rc [11:0] s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ok setrc instruction 0b000000000000 dsp s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng 0 dmx s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ok 0 dmy s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ok 0 q s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng x m s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng x i [3:0] s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng 1111 rf [1:0] s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ok setrc instruction x s s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng x t s: ok, l: ok s, l: illegal instruction s: ok, l: ok s: ok, l: ng x (s) stc: store sr to rn, sr rn (l) ldc: load rn to sr, rn sr ok: allowed to stc/lsc operation illegal instruction: treated as illegal in struction, exception should be occurred ng: keep previous value, nothing changed third one is single-data transfer instructio n, ?movs.w? and ?movs.l?. this instruction accesses any memory location through ldb (figure 2.8). all dsp registers connect to the ldb and be able to be source and destination register of the data transfer. it has word and longword access modes. in the word mode, registers to be load ed or stored by this instruction are upper 16 bits (bits 31 to 16) for the dsp registers except a0 g and a1g. when data is loaded into a register
section 2 cpu rev.6.00 mar. 27, 2009 page 34 of 1036 rej09b0254-0600 other than a0g and a1g in the word mode, lower half of the register is cl eared. when it is a0 or a1, the data is sign-extended to bits 39 to 32 and lower half of it is cleared. when a0g or a1g is a destination register in the word mode, data is loaded into 8-bit register, but a0 or a1 is not cleared. in the longword mode, when a destination register is a0 or a1, it is sign-extended to bits 39 to 32. tables 2.3 and 2.4 show the data type of registers used in the dsp instructions. some instructions cannot use some registers shown in the tables beca use of instruction code limitation. for example, pmuls can use a1 for source registers, but can not use a0. these tables ignore details of the register selectability. table 2.3 destination register of dsp instructions guard bits register bits registers instructions 39 32 31 16 15 0 a0, a1 dsp fixed-point, psha, pmuls sign-extended 40-bit result integer, pdmsb sign-extended 24-bit result cleared logical, pshl cleared 16-bit result cleared data transfer movs.w sign-extended 16-bit data cleared movs.l sign-extended 32-bit data a0g, a1g data movs.w data no update transfer movs.l data no update x0, x1 y0, y1 dsp fixed-point, psha, pmuls 32-bit result m0, m1 integer, logical, pdmsb, pshl 16-bit result cleared data movx/y.w, movs.w 16-bit result cleared transfer movs.l 32-bit data
section 2 cpu rev.6.00 mar. 27, 2009 page 35 of 1036 rej09b0254-0600 table 2.4 source register of dsp operations guard bits register bits registers instructions 39 32 31 16 15 0 a0, a1 dsp fixed-point, pdmsb, psha 40-bit data integer 24-bit data logical, pshl, pmuls 16-bit data data movx/y.w, movs.w 16-bit data transfer movs.l 32-bit data a0g, a1g data movs.w data transfer movs.l data x0, x1 y0, y1 dsp fixed-point, pdmsb, psha sign * 32-bit data m0, m1 integer sign * 16-bit data logical, pshl, pmuls 16-bit data data movs.w 16-bit data transfer movs.l 32-bit data note: * sign-extend the data and feed to the alu 31 32 39 a0 a0g a1g a1 m0 m1 x0 x1 y0 y1 0 1 2 3 4 5 6 7 dc cs [2:0] v n z gt 8 31 0 (a) dsp data registers (b) dsp status register (dsr) reset status dsr: all zeros others: undefined figure 2.7 dsp registers
section 2 cpu rev.6.00 mar. 27, 2009 page 36 of 1036 rej09b0254-0600 table 2.5 dsr register bits bit name (abbreviation) function 31?8 reserved bits 0: always read out; always use 0 as a write value 7 signed greater than bit (gt) indicates that the operat ion result is positive (excepting 0), or that operand 1 is greater than operand 2 1: operation result is posit ive, or operand 1 is greater 6 zero bit (z) indicates that the oper ation result is zero (0), or that operand 1 is equal to operand 2 1: operation result is zero (0), or equivalence 5 negative bit (n) indicates that the op eration result is negative, or that operand 1 is smaller than operand 2 1: operation result is negative, or operand 1 is smaller 4 overflow bit (v) indicates that the operation result has overflowed 1: operation result has overflowed 3?1 status selection bits (cs) designate th e mode for selecting the operation result status set in the dc bit do not set either 110 or 111 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater mode 101: signed above mode 0 dsp status bit (dc) sets the status of the operation result in the mode designated by the cs bits 0: designated mode status not realized (unrealized) 1: designated mode status realized
section 2 cpu rev.6.00 mar. 27, 2009 page 37 of 1036 rej09b0254-0600 a0g 32 0 39 31 16 a0 a1 m0 m1 x0 x1 y0 y1 0 7 a1g dsr 16 bit 16 bit 8 bit 32 bit ldb xdb ydb movx.w movs.w, movs.l movs.w, movs.l movy.w figure 2.8 connections of dsp registers and buses the dsp unit has dsp status register (dsr). th e dsr has conditions of the dsp data operation result (zero, negative, and so on) and a dc bit which is similar to the t bit in the cpu. the dc bit indicates the one of the conditional flags. a conditional dsp data processing instruction controls its execution based on the dc bit. this control affects only the operations in the dsp unit; it controls the update of dsp registers only. it cannot control operations in cpu, such as address register updating and load/store operations. the control bit cs[2:0] specifies the condition to be reflect to the dc bit. the unconditional dsp type data operations, except pmuls, movx, movy and movs, update the conditional flags and dc bit, but no cpu instructions, including mac instructions, update the dc bit. the conditional dsp type instructions do not update the dsr either. dsr is assigned as a system register and load /store instructions ar e prepared as follows: sts dsr,rn; sts.l dsr,@-rn; lds rn,dsr; lds.l @rn+,dsr; when dsr is read by the sts instructions, the upper bits (bit 31 to bit 8) are all 0.
section 2 cpu rev.6.00 mar. 27, 2009 page 38 of 1036 rej09b0254-0600 2.2 data format 2.2.1 data format in registers (non-dsp type) register operands are always longwords (32 bits) (figure 2.9). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword figure 2.9 longword operand 2.2.2 dsp-type data format the SH7727 has several different data formats that depend on operations. this section explains the data formats for dsp type instructions. figure 2.10 shows three dsp-type data formats w ith different binary point positions. a cpu-type data format with the binary point to the right of bit 0 is also shown for reference. the dsp-type fixed point data format has the binary point between bit 31 and bit 30. the dsp- type integer format has the binary point between bit 16 and bit 15. the dsp-type logical format does not have a binary point. the valid data lengths of the data formats depend on the operations and the dsp registers.
section 2 cpu rev.6.00 mar. 27, 2009 page 39 of 1036 rej09b0254-0600 39 s 31 30 0 ? 2 8 to +2 8 ? 2 ? 31 39 s 32 31 0 ? 2 23 to +2 23 ? 1 39 s s 31 30 16 15 16 15 0 ? 1 to +1 ? 2 ? 15 39 31 16 15 0 s 31 0 ? 2 15 to +2 15 ? 1 16 15 31 22 0 ? 32 to +32 16 15 s 31 21 0 ? 16 to +16 16 15 s 31 30 0 ? 1 to +1 ? 2 ? 31 s 31 0 ? 2 31 to +2 31 ? 1 dsp type fixed point with guard bits without guard bits multiplier input dsp type integer dsp type logical with guard bits cpu type integer s: sign bit longword : binary point : does not affect the operations without guard bits shift amount for arithmetic shift (psha) shift amount for logical shift (pshl) figure 2.10 data format shift amount for arithmetic shift (psha) instructio n has 7 bits filed that could represent ?64 to +63, however ?32 to +32 is the valid number for the operation. also the shift amount for logical shift operation has 6-bits field, however ?16 to +16 is the valid number for the instruction.
section 2 cpu rev.6.00 mar. 27, 2009 page 40 of 1036 rej09b0254-0600 2.2.3 data format in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address, but an address error will occur if the word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. in such cases, the data accessed cannot be guara nteed (figure 2.11). 31 0 15 23 7 byte 0 byte 1 byte 2 byte 3 word 1 word 0 a ddress a + 4 a ddress a + 8 longword address a address a address a + 2 address a + 1 address a + 3 big-endian mode 31 0 15 23 7 byte 3 byte 2 byte 1 byte 0 word 0 word 1 address a + 4 address a longword address a + 8 address a + 11 address a + 9 address a + 10 address a + 8 little-endian mode figure 2.11 byte, word , and longword alignment as the data format, either big endian or little endian byte order can be selected, according to the md5 pin at reset. when md5 is low at reset, the processor operates in big endian. when md5 is high at reset, the processor operates in little endian. 2.3 features of cpu core instructions the cpu core instructions are risc-type in structions with the following features: fixed 16-bit length: all instructions have a fixed length of 16 bits. this improves program code efficiency. one instruction per state: pipelining is used, and basic instructio ns can be executed in one state. at 160-mhz operation, one state is 6.25 ns. data size: the basic data size for operations is longword. byte, word, or longword can be selected as the memory access size. memory byte or word data is sign-e xtended and operated on as longword data. immediate data is sign-extended to longword size for arithmetic operations or zero-extended to longword size for logical operations.
section 2 cpu rev.6.00 mar. 27, 2009 page 41 of 1036 rej09b0254-0600 table 2.6 word data sign extension SH7727 cpu description example of other cpu mov.w @(disp,pc),r1 add r1,r0 ........ .data.w h'1234 sign-extended to 32 bits, r1 becomes h'00001234, and is then operated on by the add instruction. add.w #h'1234,r0 note: immediate data is re ferenced by @(disp,pc). load/store architecture: basic operations are executed be tween registers. in operations involving memory, data is first loaded into a register (load/store architecture). however, bit manipulation instructions such as and are executed directly on memory. delayed branching: unconditional branch instructions, etc ., are executed as delayed branches. with a delayed branch instruction, the branch is made after execution of th e instruction (called the slot instruction) immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. with a delayed branch, the actual br anch operation occurs after execution of the slot instruction. however, instruction execution for register upda ting, etc., excluding the branch operation, is performed in delayed branch instruction delay slot instruction order. for example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. table 2.7 delayed branch instructions SH7727 cpu description example of other cpu bra trget add r1,r0 add is executed before branch to trget. add.w r1,r0 bra trget multiply/multiply-and-ac cumulate operations: a 16 16 32 multiply operation is executed in 1 to 3 states, and a 16 16 + 64 64 multiply-and-accumulate operation in 2 to 3 states. a 32 32 64 multiply operation and a 32 32 + 64 64 multiply-and-accumulate operation are each executed in 2 to 5 states. t bit: the result of a comparison is indicated by th e t bit in the status register (sr), and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum.
section 2 cpu rev.6.00 mar. 27, 2009 page 42 of 1036 rej09b0254-0600 table 2.8 t bit SH7727 cpu description example of other cpu cmp/ge r1,r0 bt trget0 bf trget1 if r0 r1, the t bit is set. a branch is made to trget0 if r0 r1, or to trget1 if r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add #?1,r0 cmp/eq #0,r0 bt trget the t bit is not set by add. if r0 = 0, the t bit is set. a branch is made if r0 = 0. sub.w #1,r0 beq trget immediate data: byte immediate data is placed inside the instruction code. word and longword immediate data is not placed inside the instructi on code, but in a table in memory. the table in memory is referenced with an immediate data transfer instruction (mov) using pc-relative addressing mode with displacement. table 2.9 immediate data referencing type SH7727 cpu example of other cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ........ .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ........ .data.l h'12345678 mov.l #h'12345678,r0 note: immediate data is re ferenced by @(disp,pc).
section 2 cpu rev.6.00 mar. 27, 2009 page 43 of 1036 rej09b0254-0600 absolute addresses: when data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand. using the method whereby imme diate data is loaded when an instruction is executed, this value is tran sferred to a register and the data is referenced using register indirect addressing mode. table 2.10 absolute address referencing type SH7727 cpu example of other cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 ........ .data.l h'12345678 mov.b @h'12345678,r0 16-bit/32-bit displacement: when data is referenced with a 16- or 32-bit di splacement, the displacement value is placed in a table in memory beforehand. using the method whereby immediate data is loaded when an instruction is ex ecuted, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. table 2.11 displacement referencing type SH7727 cpu example of other cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 ........ .data.w h'1234 mov.w @(h'1234,r1),r2
section 2 cpu rev.6.00 mar. 27, 2009 page 44 of 1036 rej09b0254-0600 2.4 instruction formats 2.4.1 cpu instruction addressing modes the following table shows addressing modes and effective address calculation methods for instructions executed by the cpu core. table 2.12 addressing modes and effe ctive addresses for cpu instructions addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post- increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn register indirect with pre- decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn 1/2/4 rn ? 1/2/4 ? rn ? 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation)
section 2 cpu rev.6.00 mar. 27, 2009 page 45 of 1036 rej09b0254-0600 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn 1/2/4 + disp (zero-extended) rn + disp 1/2/4 byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 + disp (zero-extended) gbr + disp 1/2/4 byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4
section 2 cpu rev.6.00 mar. 27, 2009 page 46 of 1036 rej09b0254-0600 addressing mode instruction format effective address calculation method calculation formula indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0 pc-relative with displacement @(disp:8, pc) effective address is pc with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc h'fffffffc + 2/4 x & * * : with longword operand disp (zero-extended) pc + disp 2 or pc&h'fffffffc + disp 4 word: pc + disp 2 longword: pc&h'fffffffc + disp 4
section 2 cpu rev.6.00 mar. 27, 2009 page 47 of 1036 rej09b0254-0600 addressing mode instruction format effective address calculation method calculation formula pc-relative disp:8 effective address is pc with 8-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 effective address is pc with 12-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 rn effective address is sum of pc and rn. pc rn + pc + rn pc + rn immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate dat a imm of trapa instruction is zero-extended and multiplied by 4. ?
section 2 cpu rev.6.00 mar. 27, 2009 page 48 of 1036 rej09b0254-0600 2.4.2 dsp data addressing two different memory accesses are made with dsp in structions. the two kind s of instructions are x and y data transfer instructions (movx.w, mo vy.w) and single data transfer instructions (movs.w, movsl). the data addressing is diff erent for these two kinds of instruction. an overview of the data transfer instructions is given in table 2.13. table 2.13 overview of da ta transfer instructions x/y data transfer processing (movx.w, movy.w) single data transfer processing (movs.w, movs.l) address register ax: r4, r5, ay : r6, r7 as: r2, r3, r4, r5 index register ix: r8, iy: r9 is: r8 addressing nop/inc (+2)/index addition: post-increment nop/inc (+2, +4)/ index addition: post-increment ? dec (?2, ?4): pre-decrement modulo addressing possible not possible data bus xdb, ydb ldb data length 16 bits (word) 16/32 bits (word/longword) bus contention no yes memory x/y data memory entire memory space source register dx, dy: a0, a1 ds : a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g destination register dx: x0/x1, dy: y0 /y1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g x/y data addressing: with dsp instructions, the x and y data memory can be accessed simultaneously using the movx.w and movy.w instructions. two address pointers are provided for dsp instructions to enable si multaneous access to x and y data memory. only pointer addressing can be used with dsp instructions; immediate addressing is not available. address registers are divided into two, with register r4 or r5 functioning as the x memory address register (ax), and register r6 or r7 as the y memory address register (ay). the following three kinds of addressing can be used w ith x and y data transfer instructions. 1. non-update address register addressing: the ax and ay registers are addres s pointers. they are not updated.
section 2 cpu rev.6.00 mar. 27, 2009 page 49 of 1036 rej09b0254-0600 2. addition index register addressing: the ax and ay registers are addr ess pointers. after a data transfer, the value of the ix or iy register is added to each (post-increment). 3. increment address register addressing: the ax and ay registers are addr ess pointers. after a data tran sfer, they are each incremented by 2 (post- increment). there is an index register for each address pointer. the r8 register is the index register (ix) for the x memory address register (ax), and the r9 register is the index register (iy) for the y memory address register (ay). the x and y data transfer instructions perform word-length processing, and use 16-bit access to the x/y data memory. a value of 2 is therefore added to the address register in the increment processing. to perform decrementing, ?2 is set in the index register and addition index register addressing is specified. in x/y data addressing, on ly bits 1 to 15 of the address pointer are valid. when using x/y data addressing, 0 must always be written to bit 0 of the address pointer and index register. x/y data transfer addressing is shown in figu re 2.12. when accessing x and y memory using the x and y buses, the upper word of ax (r4 or r5) and ay (r6 or r7) is ignored. the result of @ay+ or @ay + iy is stored in the lower word of ay, while the upper word retains its original value. alu au r8[ix] r4[ax] r5[ax] r9[iy] r6[ay] r7[ay] +2 (inc) +0 (no update) +2 (inc) +0 (no update) note: three address processing methods: 1. increment 2. index register addition (ix/iy) 3. no increment post-updating is used in all cases. the address pointer can be decremented by setting ? 2/ ? 4 in the index register. au: adder provided for dsp addressing figure 2.12 x and y da ta transfer addressing
section 2 cpu rev.6.00 mar. 27, 2009 page 50 of 1036 rej09b0254-0600 single data addressing: dsp instructions include two single data transfer instructions (movs.w, movs.l) that load data into, or store data from, a dsp register. with these instructions, one of registers r2 to r5 is used as the single data transfer address register (as). the following four kinds of addressing can be used with single data transfer instructions. 1. non-update address register addressing: the as register is an address pointer. it is not updated. 2. addition index register addressing: the as register is an address pointer. after a data transfer, the value of the is register is added to the as register (post-increment). 3. increment address register addressing: the as register is an address pointer. after a data transfer, the as register is incremented by 2 or 4 (post-increment). 4. decrement address register addressing: the as register is an address pointer. before a data transfer, ?2 or ?4 is added to the as register (i.e. 2 or 4 is subtracted) (pre-decrement). the r8 register is the index register (is) for the address pointer (as). single data transfer addressing is shown in figure 2.13. alu r8[is] r4[as] r5[as] ? 2/ ? 4 (dec) +2/+4 (inc) +0 (no update) r3[as] r2[as] 31 0 31 0 mab cab 31 0 note: four address processing methods: 1. no update 2. index register addition (is) 3. increment 4. decrement post-increment pre-decrement figure 2.13 single data transfer addressing
section 2 cpu rev.6.00 mar. 27, 2009 page 51 of 1036 rej09b0254-0600 modulo addressing: like other dsps, the SH7727 has a modulo addressing mode. address registers are updated in the same way in this mode. when the address pointer value reaches the preset modulo end address, the address point er value becomes the mo dulo start address. modulo addressing is only available for the x and y data transfer instructions (movx.w, movy.w). modulo addressing mode is specified for the x address register by setting the dmx bit in the sr register, and for the y address register by setting the dmy bit. modulo addressing is valid for either the x or the y address register, only; it cannot be set for both at the same time. therefore, dmx and dmy cannot both be set si multaneously (if they are, the dmy setting will be valid). the mod register is provided to set the start and end addresses of the modulo address area. the mod register contains ms (modulo start) and me (modulo end). an example of the use of the mod register (ms and me fields) is shown below. mov.l modaddr,rn; rn=modend, modstart ldc rn,mod; me=modend, ms=modstart modaddr: .data.w mend; modend .data.w mstart; modstart modstart: .data : modend: .data the start and end addresses are specified in ms and me, then the dmx or dmy bit is set to 1. the address register contents are compared with me , and if they match, start address ms is stored in the address register. the lower 16 bits of the address register are compared with me. the maximum modulo size is 64 kbytes. this is sufficient to access the x and y data memory. a block diagram of modulo addressing is shown in figure 2.14.
section 2 cpu rev.6.00 mar. 27, 2009 page 52 of 1036 rej09b0254-0600 alu au r8[ix] r9[iy] r6[ay] r7[ay] +2 +0 31 0 r4[ax] r5[ax] 31 16 15 0 15 1 abx xab +2 +0 31 0 31 16 15 0 15 1 aby yab dmx dmy cont ms cmp me 15 1 15 1 instruction (movx/movy) figure 2.14 modulo addressing an example of modulo addressing is given below. ms = h'7008; me=h'700c; r4=h'a5007008; dmx = 1; dmy = 0: (modulo addressing setting for address register ax (r4, r5)) as a result of the above settings, the r4 register changes as follows. r4: h'a5007008 inc. r4: h'a500700a inc. r4: h'a500700c inc. r4: h'a5007008 (reaches modulo end address, so becomes modulo start address) place the data so that the upper 16 bits of the m odulo start and end addresses are the same. this is because the modulo start addre ss overwrites only the lower 15 bits of the address register, excluding bit 0. note: when addition indexing is used for dsp data addressing, the address pointer may exceed the me value without actually r eaching it. in this case, the ad dress pointer w ill not return to the modulo start address. not only with modulo addressing, but when x and y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, ms, and me.
section 2 cpu rev.6.00 mar. 27, 2009 page 53 of 1036 rej09b0254-0600 dsp addressing operations: dsp addressing operations in the pipeline execution stage (ex), including modulo addressing, are shown below. if ( operation is movx.w movy.w ) { abx=ax; aby=ay; /* memory access cycle uses abx and aby. the addresses to be used have not been updated */ /* ax is one of r4,r5 */ if ( dmx==0 || dmx==1 && dmy == 1 )} ax=ax+(+2 or r8[ix] or +0); /* inc,index,not-update */ else if (! not-update) ax=modulo( ax, (+2 or r8[ix]) ); /* ay is one of r6,r7 */ if ( dmy==0 ) ay=ay+(+2 or r9[iy] or +0); /* inc,index,not-update */ else if (! not-update) ay=modulo( ay, (+2 or r9[iy]) ); } else if ( operation is movs.w or movs.l ) { if ( addressing is nop, inc, add-index-reg ) { mab=as; /* memory access cycle uses mab. the address to be used has not been updated */ /* as is one of r2 to r5 */ as=as+(+2 or +4 or r8[is] or +0); /* inc,index,not-update */ else { /* decrement, pre-update */ /* as is one of r2 to r5 */ as=as+(-2 or -4); mab=as; /* memory access cycle uses mab. the address to be used has been updated */ }
section 2 cpu rev.6.00 mar. 27, 2009 page 54 of 1036 rej09b0254-0600 /* the value to be added to the address register depends on addressing operations. for example, (+2 or r8[ix] or +0) means that +2 : if operation is increment r8[ix] : if operation is add-index-reg +0 : if operation is not-update */ function modulo ( addrreg, index ) { if ( adrreg[15:0]==me ) adrreg[15:0]==ms; else adrreg=adrreg+index; return addrreg; } 2.4.3 cpu instruction formats table 2.14 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the cpu core. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement
section 2 cpu rev.6.00 mar. 27, 2009 page 55 of 1036 rej09b0254-0600 table 2.14 cpu instruction formats instruction format source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 ? ? nop ? nnnn : register direct movt rn control register or system register nnnn: register direct sts mach,rn n type xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn : pre- decrement register indirect stc.l sr,@-rn mmmm : register direct control register or system register ldc rm,sr mmmm : post- increment register indirect control register or system register ldc.l @rm+,sr mmmm : register indirect ? jmp @rm m type xxxx mmmm xxxx xxxx 15 0 pc-relative using rm ? braf rm
section 2 cpu rev.6.00 mar. 27, 2009 page 56 of 1036 rej09b0254-0600 instruction format source operand destination operand sample instruction mmmm : register direct nnnn : register direct add rm,rn mmmm : register indirect nnnn : register indirect mov.l rm,@rn nm type nnnn xxxx xxxx 15 0 mmmm mmmm : post- increment register indirect (multiply- and-accumulate operation) nnnn : * post- increment register indirect (multiply- and-accumulate operation) mach, macl mac.w @rm+,@rn+ mmmm : post- increment register indirect nnnn : register direct mov.l @rm+,rn mmmm : register direct nnnn : pre- decrement register indirect mov.l rm,@-rn mmmm : register direct nnnn : indexed register indirect mov.l rm,@(r0,rn) md type xxxx dddd 15 0 mmmm xxxx mmmmdddd : register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type dddd nnnn xxxx 15 0 xxxx r0 (register direct) nnnndddd : register indirect with displacement mov.b r0,@(disp,rn) nmd type nnnn xxxx dddd 15 0 mmmm mmmm : register direct nnnndddd : register indirect with displacement mov.l rm,@(disp,rn) mmmmdddd : register indirect with displacement nnnn : register direct mov.l @(disp,rm),rn
section 2 cpu rev.6.00 mar. 27, 2009 page 57 of 1036 rej09b0254-0600 instruction format source operand destination operand sample instruction dddddddd : gbr indirect with displacement r0 (register direct) mov.l @@(disp,gbr),r0 r0 (register direct) dddddddd : gbr indirect with displacement mov.l @r0,@(disp,gbr) dddddddd : pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 d type dddd xxxx 15 0 xxxx dddd dddddddd : pc-relative ? bf label d12 type dddd xxxx 15 0 dddd dddd dddddddddddd : pc-relative ? bra label (label=disp+pc) nd8 type dddd nnnn xxxx 15 0 dddd dddddddd : pc-relative with displacement nnnn : register direct mov.l @(disp,pc),rn iiiiiiii : immediate indexed gbr indirect and.b #imm,@(r0,gbr) iiiiiiii : immediate r0 (register direct) and #imm,r0 i type i i i i xxxx 15 0 xxxx i i i i iiiiiiii : immediate ? trapa #imm ni type nnnn i i i i xxxx 15 0 i i i i iiiiiiii : immediate nnnn : register direct add #imm,rn note: * in multiply-and-accumulate instru ctions, nnnn is the source register.
section 2 cpu rev.6.00 mar. 27, 2009 page 58 of 1036 rej09b0254-0600 2.4.4 dsp instruction formats the SH7727 includes new instructions for digital signal processing. the new instructions are of the following two kinds. 1. memory and dsp register double and single data transfer instructions (16-bit length) 2. parallel processing instructions processed by the dsp unit (32-bit length) the instruction formats ar e shown in figure 2.15. 15 16 25 26 31 0 0 0 0 15 15 15 9 9 10 10 a field a field a field b field 111110 111101 111100 0000 1110 cpu core instructions double data transfer instructions single data transfer instructions parallel processing instructions . . . figure 2.15 dsp instruction formats
section 2 cpu rev.6.00 mar. 27, 2009 page 59 of 1036 rej09b0254-0600 double and single data transfer instructions: the format of double data transfer instructions is shown in table 2.15, and that of single data transfer instructions in table 2.16. table 2.15 double data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x memory nopx 1 1 1 1 0 0 0 0 0 0 0 data movx.w @ax,dx ax dx 0 0 1 transfer movx.w @ax+,dx 1 0 movx.w @ax+ix,dx 1 1 movx.w da,@ax da 1 0 1 movx.w da,@ax+ 1 0 movx.w da,@ax+ix 1 1 y memory nopy 1 1 1 1 0 0 0 0 0 0 0 data movy.w @ay,dy ay dy 0 0 1 transfer movy.w @ay+,dy 1 0 movy.w @ay+iy,dy 1 1 movy.w da,@ay da 1 0 1 movy.w da,@ay+ 1 0 movy.w da,@ay+iy 1 1 note: ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1
section 2 cpu rev.6.00 mar. 27, 2009 page 60 of 1036 rej09b0254-0600 table 2.16 single data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 single movs.w @-as,ds 1 1 1 1 0 1 as ds 0:( * ) 0 0 0 0 data movs.w @as,ds 0:r4 1:( * ) 0 1 transfer movs.w @as+,ds 1:r5 2:( * ) 1 0 movs.w @as+is,ds 2:r2 3:( * ) 1 1 movs.w ds,@-as 3:r3 4:( * ) 0 0 0 1 movs.w ds,@as 5:a1 0 1 movs.w ds,@as+ 6:( * ) 1 0 movs.w ds,@as+is 7:a0 1 1 movs.l @-as,ds 8:x0 0 0 1 0 movs.l @as,ds 9:x1 0 1 movs.l @as+,ds a:y0 1 0 movs.l @as+is,ds b:y1 1 1 movs.l ds,@-as c:m0 0 0 1 1 movs.l ds,@as d:a1g 0 1 movs.l ds,@as+ e:m1 1 0 movs.l ds,@as+is f:a0g 1 1 note: * codes reserved for system use. parallel processing instructions: parallel processing instructions are provided for efficient execution of digital signal processing using the ds p unit. they are 32 bits long and allow four simultaneous processes, an alu operation, multiplication, and two data transfers. parallel processing instructions are divided into an a field and a b field. the a field defines data transfer instructions and the b field an alu operation instruction and multiply instruction. these instructions can be defined independently, and the processing is executed in parallel, independently and simultaneously. a-field parallel da ta transfer instructions are shown in table 2.17, and b-field alu operation instructions and multiply instructions in table 2.18.
section 2 cpu rev.6.00 mar. 27, 2009 page 61 of 1036 rej09b0254-0600 table 2.17 a-field parallel data transfer instructions nopx movx.w @ax, dx movx.w @ax+, dx movx.w @ax+ix, dx movx.w da, @ax movx.w da, @ax+ movx.w da, @ax+ix nopy movy.w @ay, dy movy.w @ay+, dy movy.w @ay+iy, dy movy.w da, @ay movy.w da, @ay+ movy.w da, @ay+iy mnemonic x memory data transfer type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 y memory data transfer 111110 111110 note: ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1 0 ax 0 ay 0 dx da 0 dy da 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 b field b field
section 2 cpu rev.6.00 mar. 27, 2009 page 62 of 1036 rej09b0254-0600 table 2.18 b-field alu op eration instructions and multiply instructions pshl #imm, dz psha #imm, dz reserved pmuls se, sf, dg reserved psub sx, sy, du pmuls se, sf, dg padd sx, sy, du pmuls se, sf, dg reserved psubc sx, sy, dz paddc sx, sy, dz pcmp sx, sy reserved reserved reserved pabs sx, dz prnd sx, dz pabs sy, dz prnd sy, dz reserved mnemonic imm. shift type 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6-operand parallel instructions 3-operand instructions 111110 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 ? 16 < = imm < = +16 ? 32 < = imm < = +32 se sf sx sy dg du 0:x0 1:x1 2:y0 3:a1 0:y0 1:y1 2:x0 3:a1 0:x0 1:x1 2:a0 3:a1 0:y0 1:y1 2:m0 3:m1 0:m0 1:m1 2:a0 3:a1 0:x0 1:y0 2:a0 3:a1 0 0 1 1 0 1 0 1 00 dz dz note: 1. codes reserved for system use. a field
section 2 cpu rev.6.00 mar. 27, 2009 page 63 of 1036 rej09b0254-0600 [if cc] pshl sx, sy, dz [if cc] psha sx, sy, dz [if cc] psub sx, sy, dz [if cc] padd sx, sy, dz reserved [if cc] pand sx, sy, dz [if cc] pxor sx, sy, dz [if cc] por sx, sy, dz [if cc] pdec sx, dz [if cc] pinc sx, dz [if cc] pdec sy, dz [if cc] pinc sy, dz [if cc] pclr dz [if cc] pdmsb sx, dz reserved [if cc] pdmsb sy, dz [if cc] pneg sx, dz [if cc] pcopy sx, dz [if cc] pneg sy, dz [if cc] pcopy sy, dz reserved [if cc] psts mach, dz [if cc] psts macl, dz [if cc] plds dz, mach [if cc] plds dz, macl ( * 2) reserved reserved mnemonic type if cc 01: 10: dct 11: dcf 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 conditional 3-operand instructions 111110 11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sx 0:x0 1:x1 2:a0 3:a1 0 0 1 1 1 1 0 0 1 0 1 0 1 * 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) dz 111111 0 0 0 0 sy 0:y0 1:y1 2:m0 3:m1 uncon- ditional if cc notes: 1. codes reserved for system use. 2. [if cc]: dct (dc bit true), dcf (dc bit false) or none (unconditional instruction) a field
section 2 cpu rev.6.00 mar. 27, 2009 page 64 of 1036 rej09b0254-0600 2.5 instruction set 2.5.1 cpu instruction set the sh-1/sh-2/sh-3 compatible instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.19. tables 2.20 to 2.25 show the instruction notation, machine code, execution time, and function.
section 2 cpu rev.6.00 mar. 27, 2009 page 65 of 1036 rej09b0254-0600 table 2.19 cpu instruction types type kinds of instruction op code function number of instructions data transfer instructions 5 mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t bit transfer swap upper/lower swap xtrct extraction of middle of linked registers 21 add binary addition 33 addc binary addition with carry arithmetic operation instructions addv binary addition with overflow check cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double- precision multiply-and-accumulate mul double-precision multiplication (32 32 bits) muls signed multiplication (16 16 bits) mulu unsigned multiplication (16 16 bits) neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with carry subv binary subtraction with underflow
section 2 cpu rev.6.00 mar. 27, 2009 page 66 of 1036 rej09b0254-0600 type kinds of instruction op code function number of instructions 6 and logical and 14 not bit inversion logic operation instructions or logical or tas memory test and bit setting tst logical and and t bit setting xor exclusive logical or 12 rotl 1-bit left shift 16 shift instructions rotr 1-bit right shift rotcl 1-bit left shift with t bit rotcr 1-bit right shift with t bit shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shlrn logical n-bit right shift shad arithmetic dynamic shift shld logical dynamic shift branch instructions 9 bf conditional branch, delayed conditional branch (t = 0) 11 bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure
section 2 cpu rev.6.00 mar. 27, 2009 page 67 of 1036 rej09b0254-0600 type kinds of instruction op code function number of instructions 15 clrt t bit clear 75 clrmac mac register clear system control instructions clrs s bit clear ldc load into control register lds load into system register ldtlb pteh/ptel load into tlb nop no operation pref data prefetch to cache rte return from exception handling sets s bit setting sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register trapa trap exception handling total: 68 189
section 2 cpu rev.6.00 mar. 27, 2009 page 68 of 1036 rej09b0254-0600 the instruction code, operation, and number of exec ution states of the cpu instructions are shown in the following tables, classified by instruction type, using the format shown below. instruction instruction c ode operation privilege execution states t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement indicated in msb ? lsb order. explanation of symbols mmmm: source register nnnn: destination register 0000: r0 0001: r1 ......... 1111: r15 iiii: immediate data dddd: displacement * 2 indicates summary of operation. explanation of symbols , : transfer direction (xx): memory operand m/q/t: flag bits in the sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ~: logical not of each bit <>n: n-bit right shift indicates a privileged instruction. value when no wait states are inserted. * 1 value of t bit after instruction is executed. explanation of symbols ?: no change notes: 1. the table shows the minimum number of execution states. in practice, the number of instruction execution states will be incr eased in cases such as the following: (1) when there is contention between an instruction fetch and a data access (2) when the destination register of a load instruction (memory register) is also used by the following instruction 2. scaled (x1, x2, or x4) according to the instruction operand size, etc.
section 2 cpu rev.6.00 mar. 27, 2009 page 69 of 1036 rej09b0254-0600 data transfer instructions table 2.20 data transfer instructions instruction operation code privileged mode cycles t bit mov #imm,rn imm sign extension rn 1110nnnniiiiiiii ? 1 ? mov.w @(disp,pc),rn (disp 2 + pc) sign extension rn 1001nnnndddddddd ? 1 ? mov.l @(disp,pc),rn (disp 4 + pc) rn 1101nnnndddddddd ? 1 ? mov rm,rn rm rn 0110nnnnmmmm0011 ? 1 ? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 ? 1 ? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 ? 1 ? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 ? 1 ? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 ? 1 ? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 ? 1 ? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 ? 1 ? mov.b rm,@ ? rn rn?1 rn, rm (rn) 0010nnnnmmmm0100 ? 1 ? mov.w rm,@ ? rn rn?2 rn, rm (rn) 0010nnnnmmmm0101 ? 1 ? mov.l rm,@ ? rn rn?4 rn, rm (rn) 0010nnnnmmmm0110 ? 1 ? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 ? 1 ? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 ? 1 ? mov.l @rm+,rn (rm) rn,rm + 4 rm 0110nnnnmmmm0110 ? 1 ? mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd ? 1 ? mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd ? 1 ? mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd ? 1 ? mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd ? 1 ? mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd ? 1 ? mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd ? 1 ? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 ? 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 70 of 1036 rej09b0254-0600 instruction operation code privileged mode cycles t bit mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 ? 1 ? mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 ? 1 ? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 ? 1 ? mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 ? 1 ? mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 ? 1 ? mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd ? 1 ? mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd ? 1 ? mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd ? 1 ? mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd ? 1 ? mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd ? 1 ? mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd ? 1 ? mova @(disp,pc),r0 disp 4 + pc r0 11000111dddddddd ? 1 ? movt rn t rn 0000nnnn00101001 ? 1 ? swap.b rm,rn rm swap the bottom two bytes reg 0110nnnnmmmm1000 ? 1 ? swap.w rm,rn rm swap two consecutive words rn 0110nnnnmmmm1001 ? 1 ? xtrct rm,rn rm: middle 32 bits of rn rn 0010nnnnmmmm1101 ? 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 71 of 1036 rej09b0254-0600 arithmetic operation instructions table 2.21 arithmetic operation instructions instruction operation code privileged mode cycles t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 ? 1 ? add #imm,rn rn + imm rn 0111nnnniiiiiiii ? 1 ? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 ? 1 carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 ? 1 overflow cmp/eq #imm,r0 if r0 = imm, 1 t 10001000iiiiiiii ? 1 comparison result cmp/eq rm,rn if rn = rm, 1 t 0011nnnnmmmm0000 ? 1 comparison result cmp/hs rm,rn if rn rm with unsigned data, 1 t 0011nnnnmmmm0010 ? 1 comparison result cmp/ge rm,rn if rn rm with signed data, 1 t 0011nnnnmmmm0011 ? 1 comparison result cmp/hi rm,rn if rn > rm with unsigned data, 1 t 0011nnnnmmmm0110 ? 1 comparison result cmp/gt rm,rn if rn > rm with signed data, 1 t 0011nnnnmmmm0111 ? 1 comparison result cmp/pz rn if rn 0, 1 t 0100nnnn00010001 ? 1 comparison result cmp/pl rn if rn > 0, 1 t 0100nnnn00010101 ? 1 comparison result cmp/str rm,rn if rn and rm have an equivalent byte, 1 t 0010nnnnmmmm1100 ? 1 comparison result div1 rm,rn single-step division (rn/rm) 0011nnnnmmmm0100 ? 1 calculation result div0s rm,rn msb of rn q, msb of rm m, m ^ q t 0010nnnnmmmm0111 ? 1 calculation result div0u 0 m/q/t 0000000000011001 ? 1 0 dmuls.l rm,rn signed operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm1101 ? 2 (to 5) * 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 72 of 1036 rej09b0254-0600 instruction operation code privileged mode cycles t bit dmulu.l rm,rn unsigned operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm0101 ? 2 (to 5) * 1 ? dt rn rn ? 1 rn, if rn = 0, 1 t, else 0 t 0100nnnn00010000 ? 1 comparison result exts.b rm,rn a byte in rm is sign- extended rn 0110nnnnmmmm1110 ? 1 ? exts.w rm,rn a word in rm is sign- extended rn 0110nnnnmmmm1111 ? 1 ? extu.b rm,rn a byte in rm is zero- extended rn 0110nnnnmmmm1100 ? 1 ? extu.w rm,rn a word in rm is zero- extended rn 0110nnnnmmmm1101 ? 1 ? mac.l @rm+,@rn+ signed operation of (rn) (rm) + mac mac, rn + 4 rn, rm + 4 rm, 32 32 + 64 64 bits 0000nnnnmmmm1111 ? 2 (to 5) * 1 ? mac.w @rm+,@rn+ signed operation of (rn) (rm) + mac mac, rn + 2 rn, rm + 2 rm, 16 16 + 64 64 bits 0100nnnnmmmm1111 ? 2 (to 5) * 1 ? mul.l rm,rn rn rm macl, 32 32 32 bits 0000nnnnmmmm0111 ? 2 (to 5) * 1 ? muls.w rm,rn signed operation of rn rm macl, 16 16 32 bits 0010nnnnmmmm1111 ? 1 (to 3) * 2 ? mulu.w rm,rn unsigned operation of rn rm macl, 16 16 32 bits 0010nnnnmmmm1110 ? 1 (to 3) * 2 ? neg rm,rn 0?rm rn 0110nnnnmmmm1011 ? 1 ? negc rm,rn 0?rm?t rn, borrow t 0110nnnnmmmm1010 ? 1 borrow sub rm,rn rn?rm rn 0011nnnnmmmm1000 ? 1 ? subc rm,rn rn?rm?t rn, borrow t 0011nnnnmmmm1010 ? 1 borrow subv rm,rn rn?rm rn, underflow t 0011nnnnmmmm1011 ? 1 underflow
section 2 cpu rev.6.00 mar. 27, 2009 page 73 of 1036 rej09b0254-0600 notes: 1. the normal minimum number of executio n cycles is two, but five cycles are required when the operation result is read from the mac register im mediately after the instruction. 2. the normal minimum number of execution cy cles is one, but three cycles are required when the operation result is read from t he mac register immediately after the mul instruction. logic operation instructions table 2.22 logic operation instructions instruction operation code privileged mode cycles t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 ? 1 ? and #imm,r0 r0 & imm r0 11001001iiiiiiii ? 1 ? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii ? 3 ? not rm,rn ~rm rn 0110nnnnmmmm0111 ? 1 ? or rm,rn rn | rm rn 0010nnnnmmmm1011 ? 1 ? or #imm,r0 r0 | imm r0 11001011iiiiiiii ? 1 ? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii ? 3 ? tas.b @rn * if (rn) is 0, 1 t; 1 msb of (rn) 0100nnnn00011011 ? 4 test result tst rm,rn rn & rm; if the result is 0, 1 t 0010nnnnmmmm1000 ? 1 test result tst #imm,r0 r0 & imm; if the result is 0, 1 t 11001000iiiiiiii ? 1 test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; if the result is 0, 1 t 11001100iiiiiiii ? 3 test result xor rm,rn rn ^ rm rn 0010nnnnmmmm1010 ? 1 ? xor #imm,r0 r0 ^ imm r0 11001010iiiiiiii ? 1 ? xor.b #imm,@(r0,gbr) (r0 + gbr) ^ imm (r0 + gbr) 11001110iiiiiiii ? 3 ? note: * an on-chip dmac bus cycle is not inserted between a tas instruction operand read cycle and write cycle. also, bus release is not performed by breq .
section 2 cpu rev.6.00 mar. 27, 2009 page 74 of 1036 rej09b0254-0600 shift instructions table 2.23 shift instructions instruction operation code privileged mode cycles t bit rotl rn t rn msb 0100nnnn00000100 ? 1 msb rotr rn lsb rn t 0100nnnn00000101 ? 1 lsb rotcl rn t rn t 0100nnnn00100100 ? 1 msb rotcr rn t rn t 0100nnnn00100101 ? 1 lsb shad rm,rn rn 0: rn << rm rn rn < 0: rn >> rm [msb rn] 0100nnnnmmmm1100 ? 1 ? shal rn t rn 0 0100nnnn00100000 ? 1 msb shar rn msb rn t 0100nnnn00100001 ? 1 lsb shld rm,rn rn 0: rn << rm rn rn < 0: rn >> rm [0 rn] 0100nnnnmmmm1101 ? 1 ? shll rn t rn 0 0100nnnn00000000 ? 1 msb shlr rn 0 rn t 0100nnnn00000001 ? 1 lsb shll2 rn rn << 2 rn 0100nnnn00001000 ? 1 ? shlr2 rn rn >> 2 rn 0100nnnn00001001 ? 1 ? shll8 rn rn << 8 rn 0100nnnn00011000 ? 1 ? shlr8 rn rn >> 8 rn 0100nnnn00011001 ? 1 ? shll16 rn rn << 16 rn 0100nnnn00101000 ? 1 ? shlr16 rn rn >> 16 rn 0100nnnn00101001 ? 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 75 of 1036 rej09b0254-0600 branch instructions table 2.24 branch instructions instruction operation code privileged mode cycles t bit bf label if t = 0, disp 2 + pc pc; if t = 1, nop (where label is disp + pc) 10001011dddddddd ? 3/1 * ? bf/s label delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 10001111dddddddd ? 2/1 * ? bt label delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 10001001dddddddd ? 3/1 * ? bt/s label if t = 1, disp 2 + pc pc; if t = 0, nop 10001101dddddddd ? 2/1 * ? bra label delayed branch, disp 2 + pc pc 1010dddddddddddd ? 2 ? braf rm delayed branch, rm + pc pc 0000mmmm00100011 ? 2 ? bsr label delayed branch, pc pr, disp 2 + pc pc 1011dddddddddddd ? 2 ? bsrf rm delayed branch, pc pr, rm + pc pc 0000mmmm00000011 ? 2 ? jmp @rm delayed branch, rm pc 0100mmmm00101011 ? 2 ? jsr @rm delayed branch, pc pr, rm pc 0100mmmm00001011 ? 2 ? rts delayed branch, pr pc 0000000000001011 ? 2 ? note: * one state when the branch is not executed.
section 2 cpu rev.6.00 mar. 27, 2009 page 76 of 1036 rej09b0254-0600 system control instructions table 2.25 system control instructions instruction operation code privileged mode cycles t bit clrmac 0 mach, macl 0000000000101000 ? 1 ? clrs 0 s 0000000001001000 ? 1 ? clrt 0 t 0000000000001000 ? 1 0 ldc rm,sr rm sr 0100mmmm00001110 5 lsb ldc rm,gbr rm gbr 0100mmmm00011110 ? 3 ? ldc rm,vbr rm vbr 0100mmmm00101110 3 ? ldc rm,ssr rm ssr 0100mmmm00111110 3 ? ldc rm,spc rm spc 0100mmmm01001110 3 ? ldc rm,r0_bank rm r0_bank 0100mmmm10001110 3 ? ldc rm,r1_bank rm r1_bank 0100mmmm10011110 3 ? ldc rm,r2_bank rm r2_bank 0100mmmm10101110 3 ? ldc rm,r3_bank rm r3_bank 0100mmmm10111110 3 ? ldc rm,r4_bank rm r4_bank 0100mmmm11001110 3 ? ldc rm,r5_bank rm r5_bank 0100mmmm11011110 3 ? ldc rm,r6_bank rm r6_bank 0100mmmm11101110 3 ? ldc rm,r7_bank rm r7_bank 0100mmmm11111110 3 ? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 7 lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 ? 5 ? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 5 ? ldc.l @rm+,ssr (rm) ssr, rm + 4 rm 0100mmmm00110111 5 ? ldc.l @rm+,spc (rm) spc, rm + 4 rm 0100mmmm01000111 5 ? ldc.l @rm+, r0_bank (rm) r0_bank, rm + 4 rm 0100mmmm10000111 5 ? ldc.l @rm+, r1_bank (rm) r1_bank, rm + 4 rm 0100mmmm10010111 5 ? ldc.l @rm+, r2_bank (rm) r2_bank, rm + 4 rm 0100mmmm10100111 5 ? ldc.l @rm+, r3_bank (rm) r3_bank, rm + 4 rm 0100mmmm10110111 5 ? ldc.l @rm+, r4_bank (rm) r4_bank, rm + 4 rm 0100mmmm11000111 5 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 77 of 1036 rej09b0254-0600 instruction operation code privileged mode cycles t bit ldc.l @rm+, r5_bank (rm) r5_bank, rm + 4 rm 0100mmmm11010111 5 ? ldc.l @rm+, r6_bank (rm) r6_bank, rm + 4 rm 0100mmmm11100111 5 ? ldc.l @rm+, r7_bank (rm) r7_bank, rm + 4 rm 0100mmmm11110111 5 ? lds rm,mach rm mach 0100mmmm00001010 ? 1 ? lds rm,macl rm macl 0100mmmm00011010 ? 1 ? lds rm,pr rm pr 0100mmmm00101010 ? 1 ? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 ? 1 ? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 ? 1 ? lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 ? 1 ? ldtlb pteh/ptel tlb 0000000000111000 1 ? nop no operation 0000000000001001 ? 1 ? pref @rm (rm) cache 0000mmmm10000011 ? 2 ? rte delayed branch, ssr/spc sr/pc 0000000000101011 4 ? sets 1 s 0000000001011000 ? 1 ? sett 1 t 0000000000011000 ? 1 1 sleep sleep 0000000000011011 4 * ? stc sr,rn sr rn 0000nnnn00000010 1 ? stc gbr,rn gbr rn 0000nnnn00010010 ? 1 ? stc vbr,rn vbr rn 0000nnnn00100010 1 ? stc ssr,rn ssr rn 0000nnnn00110010 1 ? stc spc,rn spc rn 0000nnnn01000010 1 ? stc r0_bank,rn r0_bank rn 0000nnnn10000010 1 ? stc r1_bank,rn r1_bank rn 0000nnnn10010010 1 ? stc r2_bank,rn r2_bank rn 0000nnnn10100010 1 ? stc r3_bank,rn r3_bank rn 0000nnnn10110010 1 ? stc r4_bank,rn r4_bank rn 0000nnnn11000010 1 ? stc r5_bank,rn r5_bank rn 0000nnnn11010010 1 ? stc r6_bank,rn r6_bank rn 0000nnnn11100010 1 ? stc r7_bank,rn r7_bank rn 0000nnnn11110010 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 78 of 1036 rej09b0254-0600 instruction operation code privileged mode cycles t bit stc.l sr,@ ? rn rn?4 rn, sr (rn) 0100nnnn00000011 2 ? stc.l gbr,@ ? rn rn?4 rn, gbr (rn) 0100nnnn00010011 ? 2 ? stc.l vbr,@ ? rn rn?4 rn, vbr (rn) 0100nnnn00100011 2 ? stc.l ssr,@ ? rn rn?4 rn, ssr (rn) 0100nnnn00110011 2 ? stc.l spc,@ ? rn rn?4 rn, spc (rn) 0100nnnn01000011 2 ? stc.l r0_bank, @ ? rn rn?4 rn, r0_bank (rn) 0100nnnn10000011 2 ? stc.l r1_bank, @ ? rn rn?4 rn, r1_bank (rn) 0100nnnn10010011 2 ? stc.l r2_bank, @ ? rn rn?4 rn, r2_bank (rn) 0100nnnn10100011 2 ? stc.l r3_bank, @ ? rn rn?4 rn, r3_bank (rn) 0100nnnn10110011 2 ? stc.l r4_bank, @ ? rn rn?4 rn, r4_bank (rn) 0100nnnn11000011 2 ? stc.l r5_bank, @ ? rn rn?4 rn, r5_bank (rn) 0100nnnn11010011 2 ? stc.l r6_bank, @ ? rn rn?4 rn, r6_bank (rn) 0100nnnn11100011 2 ? stc.l r7_bank, @ ? rn rn?4 rn, r7_bank (rn) 0100nnnn11110011 2 ? sts mach,rn mach rn 0000nnnn00001010 ? 1 ? sts macl,rn macl rn 0000nnnn00011010 ? 1 ? sts pr,rn pr rn 0000nnnn00101010 ? 1 ? sts.l mach,@ ? rn rn?4 rn, mach (rn) 0100nnnn00000010 ? 1 ? sts.l macl,@ ? rn rn?4 rn, macl (rn) 0100nnnn00010010 ? 1 ? sts.l pr,@ ? rn rn?4 rn, pr (rn) 0100nnnn00100010 ? 1 ? trapa #imm pc spc, sr ssr, imm << 2 tra, vbr + h'0100 pc 11000011iiiiiiii ? 8 ? note: * number of states before the chip enters the sleep state. the table shows the minimum number of cloc ks required for execution. in practice, the number of execution cycles will be increased if there is contention between an instruction fetch and a data access, or if the destinati on register of a load instruction (memory register) is also used by the following instruction.
section 2 cpu rev.6.00 mar. 27, 2009 page 79 of 1036 rej09b0254-0600 2.6 dsp extended-function instructions 2.6.1 introduction the newly added instructions are classi fied into the following three groups: 1. additional system control instructions for the cpu unit 2. dsp unit memory-register sing le and double data transfer 3. dsp unit parallel processing group 1 instructions are provided to support loop control and data transfer between cpu core registers or memory and new control registers added to the cpu core. dsp operations employ a multi-level nested-loop structure. with a single-l evel loop, use of the decrement and test, dtrn, and conditional delayed branch bf/s instructions supported by the sh-3 is adequate. however, with nested loops, dsp performance can be improved by means of a zero-overhead loop control function. the rs, re, and mod registers have been added to support loop control and modulo addressing functions. instructions are supported for data tr ansfer between these ne w control registers and general registers or memory. in addition, the ld rs and ldre address cal culation registers have been added to reduce the code size for the initial settings for zero-overhead loop control. an independent control register, dsr, is provided for the dsp engine. this register is treated as a system register such as macl and mach. the a0 , x0, x1, y0, and y1 registers are treated as system registers from the cpu side, and lds/sts instructions are supported for the same purpose. table 2.26 shows the instruction code map for the new system control instructions for the cpu core. group 2 instructions are provided to reduce dsp operation program code size. data transfer instructions that perform no data processing are frequently executed by the dsp engine. in this case, a 32-bit instructio n code is unnecessarily long, and wastes space in the program memory area. all instructions in this class have a 16-b it code length, the same as conventional sh core instructions. single data transfer instructions have greater flexibility in terms of operands than the double data transfer instruction or parallel instruction class. group 3 instructions are provided for fast execution of digital signal processing operations using the dsp unit. these instructions have a 32-bit instruction code, so that a maximum of four instructions?an alu operation, multiplication, and two data transfer instructions?can be executed in parallel.
section 2 cpu rev.6.00 mar. 27, 2009 page 80 of 1036 rej09b0254-0600 2.6.2 added cpu system control instructions the new instructions in this class are treated as part of the cpu core functions, and therefore all the added instructions have a 16-bit code length. all the additional instructions belong to the system control instruction group. table 2.26 summarizes the added sy stem instructions. new control registers?rs, re, and mod?have been added to the cpu core to support loop control and modulo addressing functions, and ldc and sts type instructions have been provided for these registers. the dsp engine?s dsr, a0, x0, x1, y0, and y1 regi sters are treated as system registers such as mach and macl, and therefore sts and lds instructions are supported for these registers. as digital signal processing operations usually employ a multi-level nested-loop structure, dsp performance can be improved by means of a zero-overhead loop control function. setrc type instructions are provided to set the repeat count in the rc field in sr[27:16]. when an immediate operand type setrc instruction is executed, the 8-bit immediate operand data is set in sr[23:16], and 0 is set in the remaining bits, sr[27:24]. when a register operand type setrc instruction is executed, rn[11:0] is set in sr[27:16]. the start address and end address of the repeat loop are set in the rs register and re register. there are two ways of setting the addresses: by using an ldc type instruction, or by using the ldrs and ldre instructions.
section 2 cpu rev.6.00 mar. 27, 2009 page 81 of 1036 rej09b0254-0600 table 2.26 added cpu system control instructions instruction instruction code operation execu- tion states t bit setrc #imm 10000010iiiiiiii imm rc (of sr) 3 ? setrc rn 0100nnnn00010100 rn[11:0] r c (of sr) 3 ? ldrs @(disp,pc) 10001100dddddddd (disp 2 + pc) rs 3 ? ldre @(disp,pc) 10001110dddddddd (disp 2 + pc) re 3 ? stc mod,rn 0000nnnn01010010 mod rn 1 ? stc rs,rn 0000nnnn01100010 rs rn 1 ? stc re,rn 0000nnnn01110010 re rn 1 ? sts dsr,rn 0000nnnn01101010 dsr rn 1 ? sts a0,rn 0000nnnn01111010 a0 rn 1 ? sts x0,rn 0000nnnn10001010 x0 rn 1 ? sts x1,rn 0000nnnn10011010 x1 rn 1 ? sts y0,rn 0000nnnn10101010 y0 rn 1 ? sts y1,rn 0000nnnn10111010 y1 rn 1 ? sts.l dsr,@-rn 0100nnnn01100010 rn ? 4 rn, dsr (rn) 1 ? sts.l a0,@-rn 0100nnnn01110010 rn ? 4 rn, a0 (rn) 1 ? sts.l x0,@-rn 0100nnnn10000010 rn ? 4 rn, x0 (rn) 1 ? sts.l x1,@-rn 0100nnnn10010010 rn ? 4 rn, x1 (rn) 1 ? sts.l y0,@-rn 0100nnnn10100010 rn ? 4 rn, y0 (rn) 1 ? sts.l y1,@-rn 0100nnnn10110010 rn ? 4 rn, y1 (rn) 1 ? stc.l mod,@-rn 0100nnnn01010011 rn ? 4 rn, mod (rn) 2 ? stc.l rs,@-rn 0100nnnn01100011 rn ? 4 rn, rs (rn) 2 ? stc.l re,@-rn 0100nnnn01110011 rn ? 4 rn, re (rn) 2 ? lds.l @rn+,dsr 0100nnnn01100110 (rn) dsr, rn + 4 rn 1 ? lds.l @rn+,a0 0100nnnn01110110 (rn) a0, rn + 4 rn 1 ? lds.l @rn+,x0 0100nnnn10000110 (rn) x0, rn + 4 rn 1 ? lds.l @rn+,x1 0100nnnn10010110 (rn) x1, rn + 4 rn 1 ? lds.l @rn+,y0 0100nnnn10100110 (rn) y0, rn + 4 rn 1 ? lds.l @rn+,y1 0100nnnn10110110 (rn) y1, rn + 4 rn 1 ? ldc.l @rn+,mod 0100nnnn01010111 (rn) mod, rn + 4 rn 5 ? ldc.l @rn+,rs 0100nnnn01100111 (rn) rs, rn + 4 rn 5 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 82 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states t bit ldc.l @rn+,re 0100nnnn01110111 (rn) re, rn + 4 rn 5 ? lds rn,dsr 0100nnnn01101010 rn dsr 1 ? lds rn,a0 0100nnnn01111010 rn a0 1 ? lds rn,x0 0100nnnn10001010 rn x0 1 ? lds rn,x1 0100nnnn10011010 rn x1 1 ? lds rn,y0 0100nnnn10101010 rn y0 1 ? lds rn,y1 0100nnnn10111010 rn y1 1 ? ldc rn,mod 0100nnnn01011110 rn mod 3 ? ldc rn,rs 0100nnnn01101110 rn rs 3 ? ldc rn,re 0100nnnn01111110 rn re 3 ? 2.6.3 single and double data tran sfer for dsp data instructions the new instructions in this class are prov ided to reduce the program code size for dsp operations. all the new instructions in this class have a 16-bit code length. instructions in this class are divided into two groups: single data transfer instructions and double data transfer instructions. the operand flexibility of the double data transfer instructions is the same as with the a field in parallel instruction class data transfer instructions described in section 2.6.4, dsp operation instruction set. however, conditional load instructions cannot be used with these 16-bit instructions. in single transfer, the ax pointer an d two other pointers are used as the as pointer, but the ay pointer is not used. tables 2.27 and 2.28 list the single and double data transfer instructions. with double data tran sfer group instructions, x memory and y memory can be accessed in parallel. the ax pointer can only be used by x memory access instructions, and the ay pointer only by y memory access instructions. double da ta transfer instructions can only access the on- chip x and y memory areas. single data transfer in structions use a 16-bit instruction code, and can access any memory address space. rn (n = 2 to 7) registers are normally used as the ax, ay, and as pointers. the pointer names themselves can be changed with the assembler rename function. the following renaming scheme is recommended. r2:as2, r3:as3, r4:ax0 (as0), r5:ax1 (as1), r6:ay0, r7:ay1, r8:ix, r9:iy
section 2 cpu rev.6.00 mar. 27, 2009 page 83 of 1036 rej09b0254-0600 table 2.27 double data transfer instructions instruction instruction code operation execu- tion states dc nopx 1111000*0*0*00** x memory no access 1 ? x memory data transfer movx.w @ax,dx 111100a*d*0*01** (ax) msw of dx, 0 lsw of dx 1 ? movx.w @ax+,dx 111100a*d*0*10** (ax) msw of dx, 0 lsw of dx, ax + 2 ax 1 ? movx.w @ax+ix,dx 111100a*d*0*11** (ax) msw of dx, 0 lsw of dx, ax + ix ax 1 ? movx.w da,@ax 111100a*d*1*01** msw of da (ax) 1 ? movx.w da,@ax+ 111100a*d*1*10** msw of da (ax), ax + 2 ax 1 ? movx.w da,@ax+ix 111100a*d*1*11** msw of da (ax), ax + ix ax 1 ? nopy 111100*0*0*0**00 y memory no access 1 ? y memory data transfer movy.w @ay,dy 111100*a*d*0**01 (ay) msw of dy, 0 lsw of dy 1 ? movy.w @ay+,dy 111100*a*d*0**10 (ay) msw of dy, 0 lsw of dy, ay + 2 ay 1 ? movy.w @ay+iy,dy 111100*a*d*0**11 (ay) msw of dy, 0 lsw of dy, ay + iy ay 1 ? movy.w da,@ay 111100*a*d*1**01 msw of da (ay) 1 ? movy.w da,@ay+ 111100*a*d*1**10 msw of da (ay), ay + 2 ay 1 ? movy.w da,@ay+iy 111100*a*d*1**11 msw of da (ay), ay + iy ay 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 84 of 1036 rej09b0254-0600 table 2.28 single data transfer instructions instruction instruction code operation execu- tion states dc movs.w @-as,ds 111101aadddd0000 as ? 2 as, (as) msw of ds, 0 lsw of ds 1 ? movs.w @as,ds 111101aadddd0100 (as) msw of ds, 0 lsw of ds 1 ? movs.w @as+,ds 111101aadddd1000 (as) msw of ds, 0 lsw of ds, as + 2 as 1 ? movs.w @as+ix,ds 111101aadddd1100 (asc) msw of ds, 0 lsw of ds, as + ix as 1 ? movs.w ds,@-as * 111101aadddd0001 as ? 2 as, msw of ds (as) 1 ? movs.w ds,@as * 111101aadddd0101 msw of ds (as) 1 ? movs.w ds,@as+ * 111101aadddd1001 msw of ds (as), as + 2 as 1 ? movs.w ds,@as+ix * 111101aadddd1101 msw of ds (as), as + ix as 1 ? movs.l @-as,ds 111101aadddd0010 as ? 4 as, (as) ds 1 ? movs.l @as,ds 111101aadddd0110 (as) ds 1 ? movs.l @as+,ds 111101aadddd1010 (as) ds, as + 4 as 1 ? movs.l @as+ix,ds 111101aadddd1110 (as) ds, as + ix as 1 ? movs.l ds,@-as 111101aadddd0011 as ? 4 as, ds (as) 1 ? movs.l ds,@as 111101aadddd0111 ds (as) 1 ? movs.l ds,@as+ 111101aadddd1011 ds (as), as + 4 as 1 ? movs.l ds,@as+ix 111101aadddd1111 ds (as), as + ix as 1 ? note: * if guard bit registers a0g and a1g are specifi ed in source operand ds, the data is output to the ldb[7:0] bus and the sign bit is copied into the upper bits, [31:8].
section 2 cpu rev.6.00 mar. 27, 2009 page 85 of 1036 rej09b0254-0600 the correspondence between dsp da ta transfer operands and registers is shown in table 2.29. cpu core registers are used as a pointer address that indicates a memory address. table 2.29 correspondence between dsp data transf er operands and registers register ax ix dx ay iy dy da as ds r0 cpu register r1 r2 (as2) yes r3 (as3) yes r4 (ax0) yes yes r5 (ax1) yes yes r6 (ay0) yes r7 (ay1) yes r8 (ix) yes r9 (iy) yes a0 yes yes dsp register a1 yes yes m0 yes m1 yes x0 yes yes x1 yes yes y0 yes yes y1 yes yes a0g yes a1g yes 2.6.4 dsp operation instruction set dsp operation instructions are instructions for digital signal processing performed by the dsp unit. these instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. the instruction code is divided into an a field and b field; a parallel data transfer instruction is specified in the a field, and a single or double data operation instruction in the b field. instructions can be specified independently, and are also executed independently. the parallel data transfer instruction specified in the a field is exactly the same as a double data transfer instruction. the function of the a field? that is, the data transf er instruction field?is
section 2 cpu rev.6.00 mar. 27, 2009 page 86 of 1036 rej09b0254-0600 basically the same as in the double data transfer instructions described in section 2.6.3, single and double data transfer for dsp data instructions, but has a special function in load instructions. b-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. the formats of the dsp operation instructions ar e shown in table 2.30. the respective operands are selected independently from the dsp regist ers. the correspondence between dsp operation instruction operands and registers is shown in table 2.31. table 2.30 dsp operation instruction formats type instruction formats double data operation instructions aluop. sx, sy, du mltop. se, df, dg conditional single data operation instructions aluop. sx, sy, dz dct aluop. sx, sy, dz dcf aluop. sx, sy, dz aluop. sx, dz dct aluop. sx, dz dcf aluop. sx, dz aluop. sy, dz dct aluop. sy, dz dcf aluop. sy, dz unconditional single data operation instructions aluop. sx, sy, dz aluop. sx, dz aluop. sy, dz mltop. se, sf, dg
section 2 cpu rev.6.00 mar. 27, 2009 page 87 of 1036 rej09b0254-0600 table 2.31 correspondence between dsp instruction operands and registers alu/bpu operations multiply operations register sx sy dz du se sf dg a0 yes yes yes yes a1 yes yes yes yes yes yes m0 yes yes yes m1 yes yes yes x0 yes yes yes yes yes x1 yes yes yes y0 yes yes yes yes yes y1 yes yes yes when writing parallel instructions, the b-field inst ruction is written first, followed by the a-field instruction. a sample parallel processing program is shown in figure 2.16. dcf padd a0, m0, a0 pmuls x0, y0, m0 movx.w @r4+, x0 movy.w @r6+, y0 [;] pinc x1, a1 movx.w a0, @r5+r8 movy.w @r7+, y0 [;] pcmp x1, m0 movx.w @r4 [nopy] [;] figure 2.16 sample pa rallel instruction program square brackets mean that the contents can be omitted. the no operation instructions nopx and nopy can be omitted. table 2.32 gives an overview of the b field in parallel operation instructions. a semicolon is the instruction line delimiter, but this can also be omitted. if the semicolon delimiter is used, the area to the right of the semi colon can be used as a comment field. this has the same function as with conventional sh tools. the dsr register condition code bit (dc) is always updated on the basis of the result of an unconditional alu or shift operation instruction. conditional instructions do not update the dc bit. multiply instructions, also, do not update the dc bit. dc bit updating is performed by means of bits cs0 to cs2 in the dsr register. the dc bit update rules are shown in table 2.33.
section 2 cpu rev.6.00 mar. 27, 2009 page 88 of 1036 rej09b0254-0600 table 2.32 dsp operation instructions instruction instruction code operation execu- tion states dc pmuls se,sf,dg 111110********** 0100eeff0000gg00 se * sf dg (signed) 1 ? padd sx,sy,du pmuls se,sf,dg 111110********** 0111eeffxxyygguu sx + sy du se * sf dg (signed) 1 * psub sx,sy,du pmuls se,sf,dg 111110********** 0110eeffxxyygguu sy ? sy du se * sf dg (signed) 1 * padd sx,sy,dz 111110********** 10110001xxyyzzzz sx + sy dz 1 * dct padd sx,sy,dz 111110********** 10110010xxyyzzzz if dc = 1, sx + sy dz if dc = 0, nop 1 * dcf padd sx,sy,dz 111110********** 10110011xxyyzzzz if dc = 0, sx + sy dz if dc = 1, nop 1 * psub sx,sy,dz 111110********** 10100001xxyyzzzz sx ? sy dz 1 * dct psub sx,sy,dz 111110********** 10100010xxyyzzzz if dc = 1, sx ? sy dz if dc = 0, nop 1 * dcf psub sx,sy,dz 111110********** 10100011xxyyzzzz if dc = 0, sx ? sy dz if dc = 1, nop 1 * psha sx,sy,dz 111110********** 1010001xxyyzzzz if sy > = 0, sx << sy dz (arithmetic shift) if sy<0, sx>>sy dz 1 * dct psha sx,sy,dz 111110********** 10010010xxyyzzzz if dc = 1 & sy > = 0, sx << sy dz (arithmetic shift) if dc = 1 & sy < 0, sx >> sy dz if dc = 0, nop 1 *
section 2 cpu rev.6.00 mar. 27, 2009 page 89 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states dc dcf psha sx,sy,dz 111110********** 10010011xxyyzzzz if dc = 0 & sy > = 0, sx << sy dz (arithmetic shift) if dc = 0 & sy < 0, sx >> sy dz if dc = 1, nop 1 * pshl sx,sy,dz 111110********** 10000001xxyyzzzz if sy > = 0, sx << sy dz (logical shift) if sy < 0, sx >> sy dz 1 * dct pshl sx,sy,dz 111110********** 10000010xxyyzzzz if dc = 1 & sy > = 0, sx << sy dz (logical shift) if dc = 1 & sy < 0, sx >> sy dz if dc = 0, nop 1 * dcf pshl sx,sy,dz 111110********** 10000011xxyyzzzz if dc = 0 & sy > = 0, sx << sy dz (logical shift) if dc = 0 & sy < 0, sx >> sy dz if dc = 1, nop 1 * pcopy sx,dz 111110********** 11011001xx00zzzz sx dz 1 * pcopy sy,dz 111110********** 1111100100yyzzzz sy dz 1 * dct pcopy sx,dz 111110********** 11011010xx00zzzz if dc = 1, sx dz if dc = 0, nop 1 * dct pcopy sy,dz 111110********** 1111101000yyzzzz if dc = 1, sy dz if dc = 0, nop 1 * dcf pcopy sx,dz 111110********** 11011011xx00zzzz if dc = 0, sx dz if dc = 1, nop 1 * dcf pcopy sy,dz 111110********** 1111101100yyzzzz if dc = 0, sy dz if dc = 1, nop 1 * pdmsb sx,dz 111110********** 10011101xx00zzzz sx dz normalization count shift value 1 * pdmsb sy,dz 111110********** 1011110100yyzzzz sx dz normalization count shift value 1 *
section 2 cpu rev.6.00 mar. 27, 2009 page 90 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states dc dct pdmsb sx,dz 111110********** 10011110xx00zzzz if dc = 1, normalization count shift value sx dz if dc = 0, nop 1 * dct pdmsb sy,dz 111110********** 1011111000yyzzzz if dc = 1, normalization count shift value sy dz if dc = 0, nop 1 * dcf pdmsb sx,dz 111110********** 10011111xx00zzzz if dc = 0, normalization count shift value sx dz if dc = 1, nop 1 * dcf pdmsb sy,dz 111110********** 1011111100yyzzzz if dc = 0, normalization count shift value sy dz if dc = 1, nop 1 * pinc sx,dz 111110********** 10011001xx00zzzz msw of sx dz 1 * pinc sy,dz 111110********** 1011100100yyzzzz msw of sy dz 1 * dct pinc sx,dz 111110********** 10011010xx00zzzz if dc = 1, msw of sx + 1 dz if dc = 0, nop 1 * dct pinc sy,dz 111110********** 1011101000yyzzzz if dc = 1, msw of sy + 1 dz if dc = 0, nop 1 * dcf pinc sx,dz 111110********** 10011011xx00zzzz if dc = 0, msw of sx + 1 dz if dc = 1, nop 1 * dcf pinc sy,dz 111110********** 1011101100yyzzzz if dc = 0, msw of sy + 1 dz if dc = 1, nop 1 * pneg sx,dz 111110********** 11001001xx00zzzz 0 ? sx dz 1 * pneg sy,dz 111110********** 1110100100yyzzzz 0 ? sy dz 1 *
section 2 cpu rev.6.00 mar. 27, 2009 page 91 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states dc dct pneg sx,dz 111110********** 11001010xx00zzzz if dc = 1, 0 ? sx dz if dc = 0, nop 1 * dct pneg sy,dz 111110********** 1110101000yyzzzz if dc = 1, 0 ? sy dz if dc = 0, nop 1 * dcf pneg sx,dz 111110********** 11001011xx00zzzz if dc = 0, 0 ? sx dz if dc = 1, nop 1 * dcf pneg sy,dz 111110********** 1110101100yyzzzz if dc = 0, 0 ? sy dz if dc = 1, nop 1 * por sx,sy,dz 111110********** 10110101xxyyzzzz sx | sy dz 1 * dct por sx,sy,dz 111110********** 10110110xxyyzzzz if dc = 1, sx | sy dz if dc = 0, nop 1 * dcf por sx,sy,dz 111110********** 10110111xxyyzzzz if dc = 0, sx | sy dz if dc = 1, nop 1 * pand sx,sy,dz 111110********** 10010101xxyyzzzz sx & sy dz 1 * dct pand sx,sy,dz 111110********** 10010110xxyyzzzz if dc = 1, sx & sy dz if dc = 0, nop 1 * dcf pand sx,sy,dz 111110********** 10010111xxyyzzzz if dc = 0, sx & sy dz if dc = 1, nop 1 * pxor sx,sy,dz 111110********** 10100101xxyyzzzz sx ^ sy dz 1 * dct pxor sx,sy,dz 111110********** 10100110xxyyzzzz if dc = 1, sx ^ sy dz if dc = 0, nop 1 * dcf pxor sx,sy,dz 111110********** 10100111xxyyzzzz if dc = 1, sx ^ sy dz if dc = 0, nop 1 * pdec sx,dz 111110********** 10001001xx00zzzz sx [39:16] ? 1 dz 1 * pdec sy,dz 111110********** 1010100100yyzzzz sy [31:16] ? 1 dz 1 *
section 2 cpu rev.6.00 mar. 27, 2009 page 92 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states dc dct pdec sx,dz 111110********** 10001010xx00zzzz if dc = 1, sx [39:16] ? 1 dz if dc = 0, nop 1 * dct pdec sy,dz 111110********** 1010101000yyzzzz if dc = 1, sy [31:16] ? 1 dz if dc = 0, nop 1 * dcf pdec sx,dz 111110********** 10001011xx00zzzz if dc = 0, sx [39:16] ? 1 dz if dc = 1, nop 1 * dcf pdec sy,dz 111110********** 1010101100yyzzzz if dc = 0, sy [31:16] ? 1 dz if dc = 1, nop 1 * pclr dz 111110********** 100011010000zzzz h'00000000 dz 1 * dct pclr dz 111110********** 100011100000zzzz if dc = 1, h'00000000 dz if dc = 0, nop 1 * dcf pclr dz 111110********** 100011110000zzzz if dc = 0, h'00000000 dz if dc = 1, nop 1 * psha #imm,dz 111110********** 00010iiiiiiizzzz if imm > = 0, dz << imm dz (arithmetic shift) if imm<0, dz>>imm dz 1 * pshl #imm,dz 111110********** 00000iiiiiiizzzz if imm > = 0, dz << imm dz (logical shift) if imm < 0, dz >> imm dz 1 * psts mach,dz 111110********** 110011010000zzzz mach dz 1 ? dct psts mach,dz 111110********** 110011100000zzzz if dc = 1, mach dz 1 ? dcf psts mach,dz 111110********** 110011110000zzzz if dc = 0, mach dz 1 ? psts macl,dz 111110********** 110111010000zzzz macl dz 1 ?
section 2 cpu rev.6.00 mar. 27, 2009 page 93 of 1036 rej09b0254-0600 instruction instruction code operation execu- tion states dc dct psts macl,dz 111110********** 110111100000zzzz if dc = 1, macl dz 1 ? dcf psts macl,dz 111110********** 110111110000zzzz if dc = 0, macl dz 1 ? plds dz,mach 111110********** 111011010000zzzz dz mach 1 ? dct plds dz,mach 111110********** 111011100000zzzz if dc = 1, dz mach 1 ? dcf plds dz,mach 111110********** 111011110000zzzz if dc = 0, dz mach 1 ? plds dz,macl 111110********** 111111010000zzzz dz macl 1 ? dct plds dz,macl 111110********** 111111100000zzzz if dc = 1, dz macl 1 ? dcf plds dz,macl 111110********** 111111110000zzzz if dc = 0, dz macl 1 ? paddc sx,sy,dz 111110********** 10110000xxyyzzzz sx + sy + dc dz carry dc 1 carry psubc sx,sy,dz 111110********** 10100000xxyyzzzz sx ? sy ? dc dz borrow dc 1 borrow pcmp sx,sy 111110********** 10000100xxyy0000 sx ? sy dc update * 1 * pabs sx,dz 111110********** 10001000xx00zzzz if sx < 0, 0 ? sx dz if sx > = 0, nop 1 * pabs sy,dz 111110********** 1010100000yyzzzz if sy < 0, 0 ? sy dz if sx > = 0, nop 1 * prnd sx,dz 111110********** 10011000xx00zzzz sx + h'00008000 dz lsw of dz h'0000 1 * prnd sy,dz 111110********** 1011100000yyzzzz sy + h'00008000 dz lsw of dz h'0000 1 * note: * see table 2.33.
section 2 cpu rev.6.00 mar. 27, 2009 page 94 of 1036 rej09b0254-0600 table 2.33 dc bit update definitions cs [2:0] condition mode description 0 0 0 carry or borrow mode the dc bit is set if an alu arithm etic operation generates a carry or borrow, and is cleared otherwise. when a psha or pshl shift instruct ion is executed, the last bit data shifted out is copied into the dc bit. when an alu logical operation is executed, the dc bit is always cleared. 0 0 1 negative value mode when an alu or shift (psha) arit hmetic operation is executed, the msb of the result, including t he guard bits, is copied into the dc bit. when an alu or shift (pshl) logical operation is executed, the msb of the result, excluding the guard bits, is copied into the dc bit. 0 1 0 zero value mode the dc bit is set if t he result of an alu or shift operation is all- zeros, and is cleared otherwise. 0 1 1 overflow mode the dc bit is set if the re sult of an alu or shift (psha) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. 1 0 0 signed greater-than mode this mode is similar to signed greater-or-equal mode, but dc is cleared if the result is all-zeros. dc = ~{(negative value ^ over-range) | zero value}; in case of arithmetic operation dc = 0; in case of logical operation 1 0 1 signed greater-or- equal mode if the result of an alu or shi ft (psha) arithmetic operation exceeds the destination register range, including the guard bits (?over-range?), the definition is the same as in negative value mode. if the result is not over-rang e, the definition is the opposite of that in negative value mode. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. dc = ~(negative value ^ over-range); in case of arithmetic operation dc = 0; in case of logical operation 1 1 0 reserved 1 1 1 reserved
section 2 cpu rev.6.00 mar. 27, 2009 page 95 of 1036 rej09b0254-0600 conditional operations and data transfer: some instructions belonging to this class can be executed conditionally, as described earlier. the specified condition is valid only for the b field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. examples are shown in figure 2.17. dct padd x0,y0,a0 movx.w @r4+,x0 movy.w a0,@r6+r9 ; when condition is true before execution: a fter execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00008233, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'0088888888, r4=h'00008002, r6=h'00008237, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 when condition is false before execution: a fter execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00008233, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'123456789a, r4=h'00008002, r6=h'00008237, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 figure 2.17 examples of conditional operations and data transfer instructions assignment of nopx and nopy instruction codes: when there is no data transfer instruction to be parallel-processed simultaneously with a dsp operation instruction, an nopx or nopy instruction can be written as the data transfer inst ruction, or the instruction can be omitted. the instruction code is the same whether an nopx or nopy instruction is writte n or the instruction is omitted. examples of nopx and nopy instruction codes are shown in table 2.34.
section 2 cpu rev.6.00 mar. 27, 2009 page 96 of 1036 rej09b0254-0600 table 2.34 examples of nopx and nopy instruction codes instruction code padd x0,y0,a0 movx.w @r4+,x0 movy.w @r6+r9,y0 1111100000001011 1011000100000111 padd x0,y0,a0 nopx movy.w @r6+r9,y0 1111100000000011 1011000100000111 padd x0,y0,a0 nopx nopy 1111100000000000 1011000100000111 padd x0,y0,a0 nopx 1111100000000000 1011000100000111 padd x0,y0,a0 1111100000000000 1011000100000111 movx.w @r4+,x0 movy.w @r6+r9,y0 1111000000001011 movx.w @r4+,x0 nopy 1111000000001000 movs.w @r4+,x0 1111010010001000 nopx movy.w @r6+r9,y0 1111000000000011 movy.w @r6+r9,y0 1111000000000011 nopx nopy 1111000000000000 nop 0000000000001001
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 97 of 1036 rej09b0254-0600 section 3 memory management unit (mmu) 3.1 overview 3.1.1 features the SH7727 has an on-chip memory management unit (mmu) that implements address translation. the SH7727 featur es a resident translation look-aside buffer (tlb) that caches information for user-created addre ss translation tables located in external memory. it enables high- speed translation of logical addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbyte an d 4 kbytes). the access right to logical address space can be set for privileged and user modes to provide memory protection. 3.1.2 role of mmu the mmu is a feature designed to make efficient use of physical memory. as shown in figure 3.1, if a process is smaller in size than the physi cal memory, the entire process can be mapped onto physical memory. however, if the pr ocess increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands (1). ha ving the process itself consider this mapping onto physical memory would impose a large burden on the process. to lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (2). in a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. thus a process only has to consider operation in virtual memory. mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. switching of physical memory is carried out via secondary storage, etc. the virtual memory system that came into being in this way is particularly effective in a time- sharing system (tss) in which a number of processes are running simultaneously (3). if processes running in a tss had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. virtual memo ry is thus used to reduce this load on the individual processes and so improve efficien cy (4). in the virtual memory system, virtual memory is allocated to each pro cess. the task of the mmu is to perform efficient mapping of these virtual memory areas onto physical memory. it also has a memory protection feature that prevents one process from inadvertently acce ssing another process?s physical memory.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 98 of 1036 rej09b0254-0600 when address translation from virtual memory to physical memory is performed using the mmu, it may occur that the relevant translation information is not recorded in the mmu, with the result that one process may inadvertently access the virtual memory allocated to another process. in this case, the mmu will generate an exception, change the physical memory mapping, and record the new address translation information. although the functions of the mmu could also be implemented by software alone, the need for translation to be performed by software eac h time a process accesses physical memory would result in poor efficiency. for this reason, a buff er for address translation (translation look-aside buffer: tlb) is provided in hardware to hold frequently used address translation information. the tlb can be described as a cache for storing address translation info rmation. unlike cache memory, however, if address translation fails, th at is, if an exception is generated, switching of address translation information is normally performed by software. this makes it possible for memory management to be performed flexibly by software. the mmu has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. in the following text, th e SH7727 address space in virtual memory is referred to as logical address space, and address space in physical memory as physical memory space.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 99 of 1036 rej09b0254-0600 process 1 physical memory mmu (1) (2) (3) (4) process 1 physical memory process 1 virtual memory mmu physical memory process 1 process 2 process 3 physical memory process 1 process 2 process 3 virtual memory physical memory figure 3.1 mmu functions 3.1.3 SH7727 mmu logical address space: the SH7727 uses 32-bit logical ad dresses to access a 4-gbyte logical address space that is divided into several areas. address space mapping is shown in figure 3.2. in the privileged mode, there are five areas, p0 to p4. the p0 and p3 areas are mapped onto physical ad dress space in page un its, in accordance with address translation table informa tion. write-back or write-through can be selected for write access by means of a ccr setting. mapping of the p1 area is fixed in physical ad dress space (h'00000000 to h'1fffffff). in the p1 area, setting a logical address msb (bit 31) to 0 generates the corresponding physical address. p1 area accesses can be cached, and the cache control register (ccr) is set to indicate whether to cache or not. write-back or write -through mode can be selected.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 100 of 1036 rej09b0254-0600 mapping of the p2 area is fixed to physical ad dress space (h'00000000 to h'1fffffff). in the p2 area, setting the top three logical address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. p2 area access cannot be cached. the p1 and p2 areas are not mapped by the address translation table, so the tlb is not used and no exceptions like tlb misses occur. initializati on of mmu-related registers, exception handling, and the like are located in the p1 and p2 areas. because the p1 area is cached, handlers that require high-speed processing are placed there. a part of the control register in the peripheral module is allocated in area 1 of the physical address space. when the physical address space is not used for address translation, a llocate that part of the control register in the p2 area. when the physical address space is used for address translation, set no caching. the p4 area is used for mapping on- chip control register addresses. in the user mode, 2 gbytes of the logical address space from h'00000 000 to h'7fffffff (area u0) can be accessed. u0 is mapped onto physi cal address space in page units, in accordance with address translation table information. when sr.dsp is off, 2 gbytes of the logical address space from h'80000000 to h'ffffffff cannot be accesse d in the user mode. attempting to do so creates an address error. write-b ack or write-through mode can be selected for write accesses by means of a ccr setting. when the sr.dsp is on, a new 16-mb address space, uxy, is defined from address h'a5000000 to h'a5ffffff for x/y ram. this uxy space is non-cached, fixed physical address space. any access to address space beyond u0 an d uxy creates an address error. for details on the x/y ram space, refer to section 6, x/y memory.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 101 of 1036 rej09b0254-0600 h'80000000 h'a0000000 h'c0000000 h'e0000000 h'ffffffff 2-gbyte virtual space, cacheable (write-back/write-through) 2-gbyte virtual space, cacheable (write-back/write-through) address error address error h'00000000 h'00000000 h'80000000 h'ffffffff area p0 area p1 area p2 area p3 area p4 area u0 area uxy (present only when sr.dsp=1) privileged mode user mode 0.5-gbyte fixed physical space, cacheable (write-back/write-through) 0.5-gbyte fixed physical space, non-cacheable 0.5-gbyte virtual space, cacheable (write-back/write-through) 0.5-gbyte control space, non-cacheable figure 3.2 logical address space mapping physical address space: the SH7727 supports a 32-bit phys ical address space, but the upper 3 bits are actually ignored and treated as a shadow. see section 12, bus state controller (bsc), for details. address translation: when the mmu is enabled, the logical address space is divided into units called pages. physical addresses ar e translated in page units. addre ss translation tables in external memory hold information such as the physical addr ess that corresponds to the logical address and memory protection codes. when an access to an ar ea other than p4 occurs, if the accessed logical address belongs to area p1 or p2 there is no tlb access and the physical address is uniquely defined. if it belongs to area p0, p3 or u0, the tlb is searched by logical address and, if that logical address is registered in the tlb, the access hits the tlb. the corresponding physical
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 102 of 1036 rej09b0254-0600 address and the page control information are re ad from the tlb and the physical address is determined. if the logical address is not registered in the tlb, a tlb miss exception occurs and processing will shift to the tlb miss handler. in the tlb mi ss handler, the tlb address translation table in external memory is searched and the correspon ding physical address and the page control information are registered in the tlb. after return ing from the handler, the instruction that caused the tlb miss is re-executed. when the mmu is enabled, address translation information that results in a physical address sp ace of h'80000000 to h'ffffffff shou ld not be registered in the tlb. when the mmu is disabled, the logical address is used directly as the physical address. as the SH7727 supports a 29-bit address space as the physical addre ss space, the top 3 bits of the physical address are ignored, and constitute a sh adow space (see section 12, bus state controller (bsc)). for example, addresses h'00001000 in the p0 area, h'80001000 in the p1 area, h'a0001000 in the p2 area, and h'c0001000 in the p3 area are all mapped onto the same physical address. when access to these addresses is performe d with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. single virtual memory mode and multiple virtual memory mode: there are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in paralle l using the logical address space exclusively and the physical address corresponding to a given logical address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the logical address space, so a given logical address may be translated into differe nt physical addresses depending on the process. by the value set to the mmu control register (mmucr), either single or multiple virtual mode is selected. in terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the tlb address comparison method (see section 3.3.3, tlb address comparison). address space identifier (asid): in multiple virtual memory mode, the address space identifier (asid) is used to differentiate between processes running in parallel and sharing logical address space. the asid is 8 bits in length and can be set by software setting of the asid of the currently running process in pteh within the mmu. when the process is switched using the asid, the tlb does not have to be purged. in single virtual memory mode, the asid is used to provide memory protection for processes running simultaneously and usin g the logical address space exclus ively (see section 3.4.2, mmu software management).
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 103 of 1036 rej09b0254-0600 3.1.4 register configuration table 3.1 shows the configuration of the mmu control registers. table 3.1 register configuration name abbreviation r/w size initial value * 1 address page table entry register high pteh r/w longword undefined h'fffffff0 page table entry register low ptel r/w longword undefined h'fffffff4 translation table base register ttb r/w longword undefined h'fffffff8 tlb exception address register tea r/w longword undefined h'fffffffc mmu control register mmucr r/w longword * 2 h'ffffffe0 notes: 1. initialized by a power-on reset or manual reset. 2. sv bit = undefined other bits = 0 3.2 register description there are five registers for mmu processing. these are all peripheral module registers, so they are located in address space area p4 and can only be accessed from privileged mode by specifying the address. these registers consist of: 1. the page table entry register high (pteh) re gister residing at address h'fffffff0, which consists of a virtual page number (vpn) and asid. the vpn set is the vpn of the logical address at which the exception is generated in case of an mmu exception or address error exception. when the page size is 4 kbytes, the vpn is the upper 20 bits of the logical address, but in this case the upper 22 bits of the logica l address are set. the vpn can also be modified by software. as the asid, software sets the number of the currently executing process. the vpn and asid are recorded in the tlb by the ldtlb instruction. 2. the page table entry register low (ptel) regist er residing at address h'fffffff4, and used to store the physical page number and page management information to be recorded in the tlb by the ldtlb instruction. the contents of this register are only modified in response to a software command. 3. the translation table base register (ttb) re siding at address h'fffffff8, which points to the base address of the current page table. th e software does not set any value in ttb automatically. ttb is available to software for general purposes.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 104 of 1036 rej09b0254-0600 4. the tlb exception address register (tea) re siding at address h'fffffffc, which stores the logical address corresponding to a tlb or address error exception. this value remains valid until the next exception or interrupt. 5. the mmu control register (mmucr) resi ding at address h'ffffffe0, which makes the mmu settings described in figure 3.3. any program that modifies mmucr should reside in the p1 or p2 area. the mmu registers are shown in figure 3.3. 31 7 vpn pteh ptel asid 0 ppn 0 10 31 6 4 3 2 1 0 10 31 ttb ttb 0 31 virtual address causing tlb-related or address error exception tea 0 pr sz c d 8 9 7 v 0 0 sh 0 mmucr 0 31 8 4 65 73210 sv rc 00 0 tf ix at 0: reserved bits. always read as 0. writing is ignored. however, 0 should also be specified in a write to mmucr only. sv: single virtual memory mode bit. set to 1 for the single virtual memory mode, cleared to 0 for the multiple virtual memory mode. rc: a 2-bit random counter, automatically updated by hardware according to the following rules in the event of an mmu exception. when a tlb miss exception occurs, all tlb entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to rc; if there is one or more invalid way, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. in the event of an mmu exception other than a tlb miss exception, the way which caused the exception is set in rc. tf: tlb flush bit. write 1 to flush the tlb (clear all valid bits of the tlb to 0). always reads 0. ix: index mode bit. when 0, vpn bits 16 to 12 are used as the tlb index number. when 1, the value obtained by ex-oring asid bits 4 to 0 in pteh and vpn bits 16 to 12 are used as the tlb index number. at: address translation bit. enables/disables the mmu. 0: mmu disabled 1: mmu enabled figure 3.3 mmu register contents
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 105 of 1036 rej09b0254-0600 3.3 tlb functions 3.3.1 configuration of the tlb the tlb caches address translation table informati on located in the external memory. the address translation table stores the physical page number translated from the virtual page number, the address space identifier, and the control informat ion for the page, which is the unit of address translation. figure 3.4 shows the overall tlb co nfiguration. the tlb is 4-way set associative with 128 entries. there are 32 entries for each way. figure 3. 5 shows the configuration of logical addresses and tlb entries. entry 1 address array data array entry 0 entry 1 entry 31 ways 0 to 3 ways 0 to 3 vpn(11 ? 10) vpn(31 ? 17) asid(7 ? 0) v entry 0 entry 31 ppn(31 ? 10) pr(1 ? 0) sz c d sh figure 3.4 overall configuration of the tlb
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 106 of 1036 rej09b0254-0600 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn (31 ? 17) vpn (11 ? 10) asid sh sz v pr ppn c d offset 0 10 31 11 0 (15) (2) (2) (22) (8) (1) (1) (1) (1) (1) 12 vpn: virtual page number. top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. since vpn bits 16 to 12 are used as the index number, they are not stored in the tlb entry. asid: address space identifier. indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, the address is compared with the asid in pteh when address comparison is performed. sh: share status bit 0 = page not shared between processes 1 = page shared between processes sz: page-size bit 0 = 1-kbyte page 1 = 4-kbyte page v: valid bit. indicates whether entry is valid. 0 = invalid 1 = valid cleared to 0 by a power-on reset. not affected by a manual reset. ppn: physical page number. top 22 bits of physical address. ppn bits 11 and 10 are not used in case of a 4-kbyte page. attention must be paid to the synonym problem in case of a 1-kbyte page (see section 3.4.4, avoiding synonym problems). pr: set the most significant bit to 0. protection key field. 2-bit field encoded to define the access rights to the page. 00: reading only is possible in privileged mode. 01: reading/writing is possible in privileged mode. 10: reading only is possible in privileged/user mode. 11: reading/writing is possible in privileged/user mode. c: cacheable bit. indicates whether the page is cacheable. 0 = non-cacheable 1 = cacheable d: dirty bit. indicates whether the page has been written to. 0 = not written to 1 = written to legend: figure 3.5 logical address and tlb structure
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 107 of 1036 rej09b0254-0600 3.3.2 tlb indexing the tlb uses a 4-way set associative scheme, so en tries must be selected by index. vpn bits 16 to 12 and asid bits 4 to 0 in pteh are used as the index number. the index number can be generated in two different ways depending on the setting of the ix bit in mmucr. 1. when ix = 0, vpn bits 16 to 12 alone are used as the index number 2. when ix = 1, vpn bits 16 to 12 are ex-ore d with asid bits 4 to 0 to generate the index number the method 1 is used to prevent lowered tlb efficiency that results when multiple processes run simultaneously in the same logical address space (m ultiple virtual memory) and a specific entry is selected by indexing of each process. figu res 3.6 and 3.7 show th e indexing schemes. 31 16 11 12 17 0 31 0 pteh register virtual address vpn 0 asid 7 10 index asid(4 ? 0) exclusive-or ways 0 to 3 vpn(31 ? 17) vpn(11 ? 10) asid(7 ? 0) v 0 31 address array data array ppn(31 ? 10) pr(1 ? 0) sz c d sh figure 3.6 tlb indexing (ix = 1)
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 108 of 1036 rej09b0254-0600 31 16 11 12 17 0 virtual address ways 0 to 3 vpn(31 ? 17) vpn(11 ? 10) asid(7 ? 0) v 0 address array data array ppn(31 ? 10) pr(1 ? 0) sz c d sh index 31 figure 3.7 tlb indexing (ix = 0) 3.3.3 tlb address comparison a tlb address comparison is performed when an instruction is fetched from a program in external memory or data in external memory is referenced. the items used in the comparison are vpn and asid. the vpn of the logical address that accesses external memory is compared to the vpn of the tlb entry selected with the index numbe r. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are searched simultaneously. if the compared values match, and the indexed tlb entry is valid (v bit = 1), the hit is registered. it is necessary to have software ensure that tlb hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. for example, if there are two identical tlb entries with the same vpn and a setting is made such that a tlb hit is made only by a process with asid = h'ff when one is in the shared state (sh = 1) and the other in the non-shared state (sh = 0), then if the asid in pteh is set to h'ff, there is a possibility of simultaneous tlb hits in both these ways. it is th erefore necessary to ensure that th is kind of setting is not made by software. the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page-size information determines whether vpn (11, 10) is compared. vpn (11, 10) is compared for 1-kbyte pages (sz = 0) but not for 4-kbyte pages (sz = 1).
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 109 of 1036 rej09b0254-0600 the sharing information (sh) determines whethe r the pteh.asid and the asid in the tlb entry are compared. asids are comp ared when there is no sh aring between processes (sh = 0) but not when there is sharing (sh = 1). when single virtual memory is supported (mmucr.sv = 1) and privileged mode is engaged (sr.md = 1), all process resources can be accessed. this means that as ids are not compared when single virtual memory is supported and privileged mode is engaged. the objects of address comparison are shown in figure 3.8. bits compared: vpn (31 ? 17) vpn (11 ? 10) sz = 0? yes no yes (1 kbyte) no (4 kbytes) bits compared: vpn (31 ? 17) bits compared: vpn (31 ? 17) vpn (11 ? 10) asid (7 ? 0) sz = 0? yes (1 kbyte) no (4 kbytes) bits compared: vpn (31 ? 17) asid (7 ? 0) sh = 1 or (sr.md = 1 and mmucr.sv = 1)? figure 3.8 objects of address comparison
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 110 of 1036 rej09b0254-0600 3.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits. the d bit of a tlb entry indicates whether the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. to record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. the c bit in the entry indicates whether the re ferenced page resides in a cacheable or non- cacheable area of memory. when the control register in area 1 is mapped, set the c bit to 0. the pr field specifies the access rights for the page in privileged and user modes and is used to protect memory. attempts at nonpermitted accesse s result in tlb protection violation exceptions. access states designated by the d, c, and pr bits are shown in table 3.2. table 3.2 access states designated by d, c, and pr bits privileged mode user mode reading writing reading writing d bit 0 permitted initial page write exception permitted initial page write exception 1 permitted permitted permitted permitted c bit 0 permitted (no caching) permitted (no caching) permitted (no caching) permitted (no caching) 1 permitted (with caching) permitted (with caching) permitted (with caching) permitted (with caching) pr bit 00 permitted tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 permitted permitted tlb protection violation exception tlb protection violation exception 10 permitted tlb protection violation exception permitted tlb protection violation exception 11 permitted permitted permitted permitted
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 111 of 1036 rej09b0254-0600 3.4 mmu functions 3.4.1 mmu hardware management there are two kinds of mmu hardware management as follows: 1. the mmu decodes the logical address accessed by a process and performs address translation by controlling the tlb in accordance with the mmucr settings. 2. in address translation, the mmu receives pa ge management informa tion and bit information from the tlb, and determines the mmu excep tion and whether the cache is to be accessed (using the c bit). for details of the determin ation method and the hardware processing, see section 3.5, mmu exceptions. 3.4.2 mmu software management there are three kinds of mmu software management, as follows. 1. mmu register setting. mmucr setting, in particular, should be performed in areas p1 and p2 for which address translation is not performed. also, since sv and ix bit changes constitute address translation system changes, in this case, tlb flushing should be performed by simultaneously writing 1 to the tf bit also. si nce mmu exceptions are not generated in the mmu disabled state with the at bit cleared to 0, use in the disabled state must be avoided with software that does not use the mmu. 2. tlb entry recording, deletion, and reading. tlb entry recording can be done in two ways by using the ldtlb instruction, or by writing directly to the memory-mapped tlb. for tlb entry deletion and reading, the memory alloca tion tlb can be accessed. see section 3.4.3, mmu instruction (ldtlb), for details of the ldtlb instruction, and section 3.6, memory- mapped tlb, for details of the memory-mapped tlb. 3. mmu exception handling. when an mmu exception is generated, it is handled on the basis of information set from the hardware side. see section 3.5, mmu exceptions, for details. when single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share stat us bit (sh) to 0 to specify recording of all tlb en tries. this strengthens inter- process memory protection, and enables special access levels to be cr eated in the privileged mode only. recording a 1-kbyte page tlb entry may result in a synonym problem. see section 3.4.4, avoiding synonym problems.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 112 of 1036 rej09b0254-0600 3.4.3 mmu instruction (ldtlb) the load tlb instruction (ldtlb) is used to record tlb entries. when the ix bit in mmucr is 0, the ldtlb instruction changes the tlb entry in the way specified by the rc bit in mmucr to the value specified by pteh and ptel, using vpn bits 16 to 12 specified in pteh as the index number. when the ix bit in mmucr is 1, the ex-or of vpn bits 16 to 12 specified in pteh and asid bits 4 to 0 in pteh are used as the index number. figure 3.9 shows the case wher e the ix bit in mmucr is 0. when an mmu exception occurs, the virtual page nu mber of the logical address that caused the exception is set in pteh by hardware. the way is set in the rc bit of mmucr for each exception according to the rules show n in figure 3.9. consequently, if the ldtlb instruction is issued after setting only ptel in the mmu excep tion handling routine, tlb entry recording is possible. any tlb entry can be updated by software rewriting of pteh and the rc bits in mmucr. as the ldtlb instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the p0, u0, or p3 area. make sure, therefore, that this instruction is issued in the p1 or p2 area. also, an instru ction associated with an access to the p0, u0, or p3 area (such as the rte instruction) should be issued at least two instructions after the ldtlb instruction.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 113 of 1036 rej09b0254-0600 vpn(31 ? 17) vpn(11 ? 10) asid(7 ? ) v vpn 0 asid vpn 0 sv 0 0 rc 0 tf ix at ppn 0 v 0 pr sz c d sh 0 write ppn(31 ? 10) pr(1 ? 0) sz c d sh write data array address array way selection ways 0 to 3 31 9 0 mmucr index 31 17 12 10 8 0 pteh register 31 10 0 ptel register 0 31 figure 3.9 operation of ldtlb instruction 3.4.4 avoiding synonym problems when a 1-kbyte page is recorded in a tlb entry, a synonym problem may arise. if a number of logical addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. the reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.10. to achieve high-speed operation of the SH7727 cach e, an index number is created using logical address bits 11 to 4. when a 4-kbyte page is used, logical address bits 11 to 4 are included in the offset, and since they are not subject to address tr anslation, they are the sa me as physical address bits 11 to 4. in cache-based address comparison and recording in the addr ess array, since the cache tag address is a physical address, physical address bits 31 to 10 are recorded. when a 1-kbyte page is used, also, a cache index numb er is created using logical address bits 11 to 4. however, in case of a 1-kbyte page, logical address bits 11 and 10 are subject to address translation and therefore may not be the same as physical address bits 11 and 10. consequently,
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 114 of 1036 rej09b0254-0600 the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. note: when multiple address information items use the same physical memory to provide for future expansion of the superh risc engine family, it is recommended that vpn[20:10] be made equal. also, the same physical addresses should not be used with different page size address conversion information. for example, assume that, with 1-kbyte page tlb entries, tlb entries for which the following translation has been performed are recorded in two tlbs: logical address 1 h'00000000 physical address h'00000c00 logical address 2 h'00000c00 physical address h'00000c00 logical address 1 is recorded in cache entry h'00, and logical address 2 in cache entry h'c0. since two logical addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will o ccur as soon as a write is performed to either logical address. therefore, when recording a 1-kbyte tlb entry, if the physical address is the same as a physical address already used in another tlb entry, it should be recorded in such a way that physical address bits 11 and 10 are the same.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 115 of 1036 rej09b0254-0600 when using a 4-kbyte page virtual address 31 vpn 0 12 11 10 offset physical address 31 ppn 0 offset virtual address (11 ? 4) physical address (31 ? 10) cache address array when using a 1-kbyte page virtual address 31 vpn 0 10 11 offset physical address 31 ppn 0 10 11 offset virtual address (11 ? 4) physical address (31 ? 10) cache address array 9 9 12 11 10 figure 3.10 synonym problem
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 116 of 1036 rej09b0254-0600 3.5 mmu exceptions there are four mmu exceptions: tlb miss, tlb protection violation, tlb invalid, and initial page write. 3.5.1 tlb miss exception a tlb miss results when the logical address and th e address array of the selected tlb entry are compared and no match is found. tlb miss exception handling includes both hardware and software operations. hardware operations: in a tlb miss, the SH7727 hardwa re executes a set of prescribed operations, as follows: 1. the vpn field of the logical address causing the exception is written to the pteh register. 2. the logical address causing the exception is written to the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related dela yed branch instruction is written to the spc. 5. the contents of the status register (sr) at the time of the exception are written to the save status register (ssr). 6. the mode (md) bit in sr is set to 1 to place the SH7727 in the privileged mode. 7. the block (bl) bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the random counter (rc) field in the mmu control register (mmucr) is incremented by 1 when all ways are checked for the tlb entry corr esponding to the logical address at which the exception occurred, and all ways are valid. if one or more ways are invalid, those ways are set in rc in prioritized order from way 0 through way 1, way 2, and way 3. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000400 to invoke the user-w ritten tlb miss exception handler. software (tlb miss handler) operations: the software searches the page tables in external memory and allocates the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the value of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (s h), and valid (v) bits of the page table entry
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 117 of 1036 rej09b0254-0600 recorded in the address translation table in the external memory into th e ptel register in the SH7727. 2. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions. 3.5.2 tlb protection violation exception a tlb protection violation exception results when th e logical address and the address array of the selected tlb entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the pr field. tlb protection violation exception handling includes both hardware and software operations. hardware operations: in a tlb protection violation exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. the vpn field of the logical address causing the exception is written to the pteh register. 2. the logical address causing the exception is written to the tea register. 3. either exception code h'0a0 for a load access, or h'0c0 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written into spc (if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into spc). 5. the contents of sr at the time of the exception ar e written to ssr. 6. the md bit in sr is set to 1 to place the SH7727 in the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the way that generated the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the tlb protection violation exception handler. software (tlb protection viol ation handler) operations: software resolves the tlb protection violation and issues the rte (return from exception handler) instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 118 of 1036 rej09b0254-0600 3.5.3 tlb invalid exception a tlb invalid exception results when the logical address is compared to a selected tlb entry address array and a match is found but the entry is not valid (the v bit is 0). tlb invalid exception handling includes both hardware and software operations. hardware operations: in a tlb invalid exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. the vpn number of the logical address causing the exception is written to the pteh register. 2. the logical address causing the exception is written to the tea register. 3. the way number causing the exception is written to rc in mmucr. 4. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 5. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch in struction is written to the spc. 6. the contents of sr at the time of the exception are written into ssr. 7. the mode (md) bit in sr is set to 1 to place the SH7727 in the privileged mode. 8. the block (bl) bit in sr is set to 1 to mask any further exception requests. 9. the register bank (rb) bit in sr is set to 1. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100, and the tlb protection violation exception handler starts. software (tlb invalid exce ption handler) operations: the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, software must ex ecute the following operations: 1. write the values of the physical page number (ppn) field and the values of the protection key (pr), page size (sz), cacheable (c), dirty (d), shar e status (sh), and valid (v) bits of the page table entry recorded in the external memory to the ptel register. 2. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 119 of 1036 rej09b0254-0600 3.5.4 initial page write exception an initial page write exception results in a write access when the logical address and the address array of the selected tlb entry are compared an d a valid entry with the appropriate access rights is found to match, but the d (dirty) bit of the en try is 0 (the page has not been written to). initial page write exception handling includes both hardware and software operations. hardware operations: in an initial page write exception, the SH7727 hardware executes a set of prescribed operations, as follows: 1. the vpn field of the logical address causing the exception is written to the pteh register. 2. the logical address causing the exception is written to the tea register. 3. exception code h'080 is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the related de layed branch instruction is written to the spc. 5. the contents of sr at the time of the exception ar e written to ssr. 6. the md bit in sr is set to 1 to place the SH7727 in the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the way that caused the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the user-written initial page write exception handler. software (initial page write handler) operations: the software must execute the following operations: 1. retrieve the required page table entry from external memory. 2. set the d bit of the page table entry in the external memory to 1. 3. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in the external memory to the ptel register. 4. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. 5. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 6. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions. figure 3.11 shows the flowchart for mmu exceptions.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 120 of 1036 rej09b0254-0600 start tlb miss exception initial page write exception pr check pr check yes sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? vpns match? no yes yes yes yes user or privileged? d = 1? c = 1? v = 1? no no user mode privileged mode no no tlb protection violation exception tlb protection violation cache access w 00/01 10 01/11 00/10 11 ww w rr rr r/w? r/w? r/w? r/w? tlb invalid exception memory access no (noncacheable) yes (cacheable) figure 3.11 mmu exception generation flowchart
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 121 of 1036 rej09b0254-0600 3.5.5 processing flow in event of mmu ex ception (same processing flow for address error) mmu exception in the instruction fetch mode id ex ma wb id ex ma wb id ex ma wb nop nop if id ex ma wb : exception source stage if id ex ma wb nop mmu exception handler handler transition processing = instruction fetch = instruction decode = instruction execution = memory access = write back = no operation if figure 3.12 mmu exception signals in instruction fetch
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 122 of 1036 rej09b0254-0600 mmu exception in th e data access mode if id ex if id ex if id id ex ma wb id ex ma wb id ex ma wb nop nop if id ex ma wb : exception source stage : stage cancellation for instruction that has begun execution if id ex ma wb nop = instruction fetch = instruction decode = instruction execution = memory access = write back = no operation mmu exception handler handler transition processing ma wb ma wb ex ma wb figure 3.13 mmu exception signals in data access
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 123 of 1036 rej09b0254-0600 3.5.6 mmu exception in repeat loop when mmu exception or cpu address error occurs immediately before or within a repeat loop, the pc of the instruction that generated the exception can not be saved in spc correctly and repeat loop can not be restarted after returning from exception handler. expevt is set to h'070 in cases of tlb miss, tlb invalid, and cpu address erro r. expevt is set to h'0d0 in case of tlb protection violation. figure 3.14 describes the places where this case occurs. in a repeat loop of 4 or more instructions, only th e last 4 instructions are relevant (see figure 3.14 (4)). : exception source stage where spc is not correct and repeat loop can not be restarted (1) 1 instruction repeated (inst1, sr.rc=2) inst-1 inst0 inst1 inst1 inst2 if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb (2) 2 instructions repeated (inst1 and inst2, sr.rc=2) inst-1 inst0 inst1 inst2 inst1 inst2 inst3 if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb (3) 3 instructions repeated (inst1, inst2 and inst3, sr.rc=2) inst-1 inst0 inst1 inst2 inst3 inst1 inst2 inst3 inst4 if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb figure 3.14 mmu exception in repeat loop
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 124 of 1036 rej09b0254-0600 (4) 4 or more instructions repeated (inst1, inst2, ..., instn, sr.rc=2) inst-1 inst0 inst1 inst2 : instn-3 instn-2 instn-1 instn inst1 inst2 : instn-3 instn-2 instn-1 instn instn+1 if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb : if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb if id ex ma wb : : exception source stage where spc is not correct and repeat loop can not be restarted figure 3.14 mmu exception in repeat loop (cont) 3.6 memory-mapped tlb in order for tlb operations to be managed by soft ware, tlb contents can be read or written to in the privileged mode using the mov instruction. the tlb is assigned to the p4 area in the logical address space. the tlb address array (vpn, v b it, and asid) is assigned to h'f2000000 to h'f2ffffff, and the data array (ppn, pr, sz , c, d, and sh bits) to h'f3000000 to h'f3ffffff. the v bit in the address array can al so be accessed from the data array. only longword access is possible for both th e address array and the data array.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 125 of 1036 rej09b0254-0600 3.6.1 address array the address array is assigned to h'f2000000 to h'f2ffffff. to access an address array, the 32-bit address field (for read/write operations) and 32- bit data field (for write operations) must be specified. the address field specifi es information for selecting the entry to be accessed; the data field specifies the vpn, v bit and asid to be wr itten to the address array ((1) in figure 3.15). in the address field, specify vpn (16 to 12) as th e index address for selecting the entry (bits 16 to 12), the w bits for selecting the way (bits 9 and 8), and h'f2 to indicate address array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or of vpn (16 to 12) and asid (4 to 0) in the pteh register is taken as the index address. when writing, the write is perf ormed to the entry selected with the index address and way. when reading, the vpn, v bit, and asid of the entry selected with the index address and way in the format of the data field in figure 3.12 without comparing addresses. 0 is written to data field bits 16 to 12. to invalidate a specific entry, specify the entry and way, and write 0 to the corresponding v bit. 3.6.2 data array the data array is assigned to h'f3000000 to h'f3ffffff. to access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. the address section speci fies information for selecting th e entry to be accessed; the data section specifies the longword data to be written to the data array ((2) in figure 3.15). longword data has the same bit configuration as ptel. in the address field, specify vpn (16 to 12) as th e index address for selecting the entry (bits 16 to 12), the w bits for selecting the way (bits 9 and 8), and h'f3 to indicate data array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or of vpn (16 to 12) and asid (4 to 0) in the pteh register is taken as the index address. both reading and writing use the longword of the data array specified by the entry address and way number.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 126 of 1036 rej09b0254-0600 vpn 31 23 1111 0010 * * 16 (1) tlb address array access read access w 0 * vpn * 31 23 24 24 17 17 17 1111 0010 * ** * 16 write access read/write access w 60 * * 0 vpn 31 23 24 11110011 000 * * 16 17 address field w 0 * * 31 29 28 data field 10 ppn 8 9 7654 3 2 1 0 x v xx vpn 31 16 data field (2) tlb data array access 12 10 11 8 97 12 10 11 8 97 12 10 11 8 97 12 10 11 8 97 6 * 0 0 asid 0v vpn 0 0 17 vpn 16 12 10 11 vpn 31 asid 8 97 0 * v d c sh pr sz vpn: v: w: virtual page number valid bit way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: : address space identifie r don't care bit ppn: pr: c: sh: vpn: x: w: physical page number protection key field cacheable bit share status bit virtual page number 0 for read, don't care bit for write way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: sz: d: : valid bit page-size bit dirty bit don't care bit address field data field address field * * * * * * * figure 3.15 specifying address a nd data for memory-mapped tlb access
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 127 of 1036 rej09b0254-0600 3.6.3 usage examples invalidating specific entries: specific tlb entries can be invalidated by writing 0 to the entry?s v bit. r0 specifies the write data and r1 specifies the address. ; r0=h'1547 381c r1=h'f201 30 ; mmucr.ix=0 ; vpn(31?17)=b'0001 0101 0100 011 vpn(11?10)=b'10 asid=b'0001 1100 ; corresponding entry association is made from the entry selected by ; the vpn(16?12)=b'1 0011 index, the v bit of the hit way is cleared to ; 0,achieving invalidation. mov.l r0,@r1 reading the data of a specific entry: this example reads the data section of a specific tlb entry. the bit order indicated in the data field in figure 3.15 (2) is read. r0 specifies the address and the data section of a selected entry is read to r1. ; r1 = h'f300 4300 vpn(16-12)=b'00100 way 3 ; mov.l @r0,r1
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 128 of 1036 rej09b0254-0600 3.7 usage notes 1. instructions that manipulate the md or bl bit in register sr (the ldc rm, sr instruction, ldc @rm+, sr instruction, and rte instruction) and the following instruction, or the ldtlb instruction, should be used with the tlb disabled or in a fixed physical address space (the p1 or p2 space). 2. the value of the rc bit in mmucr may be set abnormally if all of the following conditions are met: (1) mmu is on (at is set to 1 in mmucr). (2) identical entries in the tlb address array reference the same vpn using multiple ways. (3) a tlb related exception occurs. the vpn is not initialized at power on reset or manual reset. therefore, identical entries may access two or more vpns using the same value. in such cases, certain entries in the tlb address array may end up as shown below if, fo r example, they are registered in way 3. in this case way 0 and way 3 reference the same vpn, thereby satisfying condition (2). after reset after registration to way 3 way vpn v way vpn v 0 12345 0 0 12345 0 3 12345 0 3 12345 1 the above conditions can also be satisfied by tlb handling in software. for example, the situation shown below could occur if, after inva lidating way 0 (by setting v from 1 to 0) for an entry in the tlb address array, th e entry is registered to way 3. in this case as well, the same vpn is assigned for both way 0 and way 3, thereby satisfying condition (2) above. after invalidation of way 0 after registration to way 3 way vpn v way vpn v 0 12345 0 0 12345 0 3 11111 0 3 12345 1
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 129 of 1036 rej09b0254-0600 measures to avoid the problem the following two measures should be taken to avoid the problem described above: a. after performing a reset and before setting at to 1 in mmucr, initialize to 1 the upper four bits of the vpns for each entry in the tlb address array. b. when invalidating an entry in the tlb address array, initialize to 1 the upper four bits of the corresponding vpn in addition to setting v to 0. the above measures will ensure that the vpn is not in the area referenced after address conversion. this will prevent condition (3) from being satisfied and prevent the problem described above from arising.
section 3 memory management unit (mmu) rev.6.00 mar. 27, 2009 page 130 of 1036 rej09b0254-0600
section 4 exception handling rev.6.00 mar. 27, 2009 page 131 of 1036 rej09b0254-0600 section 4 exception handling 4.1 overview 4.1.1 features exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. in response to an exception handling request due to abnormal termination of the executing instruction, contro l is passed to a user-written exception handler. however, in response to an in terrupt request, normal program execution continues until the end of the executing instruction. here, all exceptions other than resets and interrupts will be called general exceptions. there are thus three type s of exceptions: resets, general exceptions, and interrupts. 4.1.2 register configuration table 4.1 lists the registers used for exception handling. a register with an undefined initial value should be initialized by software. table 4.1 register configuration register abbr. r/w size initial value address trapa exception register tra r/ w longword undefined h'ffffffd0 exception event register expevt r/w longword power-on reset: h'000 manual reset: h'020 h'ffffffd4 interrupt event register intevt r/w longword undefined h'ffffffd8 interrupt event register2 intevt2 r longword undefined h'04000000 (h'a4000000) * note: * when address translation by the mmu does not apply, the address in parentheses should be used. 4.2 exception handling function 4.2.1 exception handling flow in exception handling, the contents of the program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. the return from exception handler (rte) instruction is issued by the exception handler routin e at the completion of the routine, restoring the
section 4 exception handling rev.6.00 mar. 27, 2009 page 132 of 1036 rej09b0254-0600 contents of the pc and sr to return to the pr ocessor state at the point of interruption and the address where the ex ception occurred. a basic exception handling sequence consists of the following operations: 1. the contents of the pc and sr are saved in the spc and ssr, respectively. 2. the block (bl) bit in sr is set to 1, masking any subsequent exceptions. 3. the mode (md) bit in sr is set to 1 to place the SH7727 in the privileged mode. 4. the register bank (rb) bit in sr is set to 1. 5. an exception code identifying the exception ev ent is written to bits 11 to 0 of the exception event (expevt) or interrupt even t (intevt or intevt2) register. 6. instruction execution jumps to the designated exception handling vector address to invoke the handler routine. 4.2.2 exception handling vector addresses the reset vector address is fixed at h'a0000000. the other three events are assigned offsets from the vector base address by software. translati on look-aside buffer (tlb) miss exceptions have an offset from the vector base address of h'00000400. the vector address offset for general exception events other than tlb miss exceptions is h'00000100. the interrupt vector address offset is h'00000600. the vector base addres s is loaded into the vector base register (vbr) by software. the vector base address should re side in p1 or p2 fixed physical address space. fi gure 4.1 shows the relationship between the vector base addres s, the vector offset, and the vector table. vbr (vector base address) + vector offset h'a000 0000 vector addres s figure 4.1 vector table with regard to exceptions and their vector addresses, table 4.2 lists exception type, instruction completion state, priority, exception orde r, vector address, and vector offset.
section 4 exception handling rev.6.00 mar. 27, 2009 page 133 of 1036 rej09b0254-0600 table 4.2 exception event vectors exception type current instruction exception event priority * 1 exception order vector address vector offset reset aborted power-on reset 1 ? h'a0000000 ? manual reset 1 ? h'a0000000 ? h-udi reset 1 ? h?a0000000 ? aborted and retried cpu address error (instruction access) 2 1 ? h'00000100 general exception events tlb miss (instruction access not in repeat loop) 2 2 ? h'00000400 tlb miss (instruction access in repeat loop) * 4 2 2 ? h?00000100 tlb invalid (instruction access) 2 3 ? h'00000100 tlb protection violation (instruction access) 2 4 ? h'00000100 general illegal instruction exception 2 5 ? h'00000100 illegal slot instruction exception 2 5 ? h'00000100 cpu address error (data access) 2 6 ? h'00000100 tlb miss (data access not in repeat loop) 2 7 ? h'00000400 tlb miss (data access in repeat loop) * 4 2 7 ? h'00000100 tlb invalid (data access) 2 8 ? h'00000100 tlb protection violation (data access) 2 9 ? h'00000100 initial page write 2 10 ? h'00000100 completed unconditional trap (trapa instruction) 2 5 ? h'00000100 user breakpoint trap 2 n * 2 ? h'00000100 dma address error 2 12 ? h'00000100
section 4 exception handling rev.6.00 mar. 27, 2009 page 134 of 1036 rej09b0254-0600 exception type current instruction exception event priority * 1 exception order vector address vector offset completed nonmaskable interrupt 3 ? ? h'00000600 external hardware interrupt 4 * 3 ? ? h'00000600 general interrupt requests h-udi interrupt 4 * 3 ? ? h'00000600 notes: 1. priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. the user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction ex ecution. for an operand break point, use 11. 3. use software to specify relative prioriti es of external hardware interrupts and peripheral module interrupts (see section 7, interrupt controller (intc)). 4. see section 4.5.2, gener al exceptions for details. 4.2.3 acceptance of exceptions processor resets and interrupts are asynchronous events unrelated to the instruction stream. all exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. when a power-on re set and a manual reset occur simultaneously, the power-on reset has priority. all general exception events occur in a relative order in the execution sequence of an instruction (i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. three general exception events (general illegal instruction exception, unconditional trap exception, and illegal slot instruction exception) are detected in the decode stage (id stage) of different instructions and are mutually exclusive events in the instruction pipeline. they have the same execution priority. figure 4.2 shows the order of ge neral exception acceptance.
section 4 exception handling rev.6.00 mar. 27, 2009 page 135 of 1036 rej09b0254-0600 if instruction n id ex ma tlb miss (data access) wb if instruction n + 1 instruction n + 2 id ex ma tlb miss (instruction access) wb if id ex ma rie (reserved instruction exception) wb pipeline sequence: tlb miss (instruction n) re-execution of instruction n 1 2 3 tlb miss (instruction n + 1) re-execution of instruction n + 1 rie (instruction n + 2) if id ex ma wb = instruction fetch = instruction decode = instruction execution = memory access = write back handling order: program order: tlb miss (instruction n+1) tlb miss (instruction n) and rie (instruction n + 2) = simultaneous detection detection order: figure 4.2 example of accept ance order of general exceptions
section 4 exception handling rev.6.00 mar. 27, 2009 page 136 of 1036 rej09b0254-0600 all exceptions other than a reset are detected in the pipeline id stage, and accepted on instruction boundaries. however, an exception is not accepte d between a delayed branch instruction and the delay slot. a re-execution type ex ception detected in a delay slot is accepted before execution of the delayed branch instruction. a completion type exception detected in a delayed branch instruction or delay slot is accepted after execu tion of the delayed branch instruction. the delay slot here refers to the next instruction after a delayed unconditional branch instruction, or the next instruction when a delayed conditional branch instruction is true. 4.2.4 exception codes table 4.3 lists the exception codes written to bits 11 to 0 of the expevt register (for reset or general exceptions) or the intevt and intevt2 registers (for general interrupt requests) to identify each specific exception event. an a dditional exception register, the trapa (tra) register, is used to hold the 8-bit immediate da ta in an unconditional trap (trapa instruction). table 4.3 exception codes exception type exception event exception code reset power-on reset h'000 manual reset h'020 h-udi reset h'000 general exception events tlb miss/invalid (read) h'040 tlb miss/invalid (write) h'060 tlb miss/invalid/cpu address error in repeat loop h'070 initial page write h'080 tlb protection violation (read) h'0a0 tlb protection violation (write) h'0c0 tlb protection violation in repeat loop h'0d0 cpu address error (read) h'0e0 cpu address error (write) h'100 unconditional trap (trapa instruction) h'160 illegal general instruction exception h'180 illegal slot instruction exception h'1a0 user breakpoint trap h'1e0 dma address error h'5c0
section 4 exception handling rev.6.00 mar. 27, 2009 page 137 of 1036 rej09b0254-0600 exception type exception event exception code general interrupt requests nonmaskable interrupt h'1c0 h-udi interrupt h'5e0 external hardware interrupts: irl3 to irl0 = 0000 h'200 irl3 to irl0 = 0001 h'220 irl3 to irl0 = 0010 h'240 irl3 to irl0 = 0011 h'260 irl3 to irl0 = 0100 h'280 irl3 to irl0 = 0101 h'2a0 irl3 to irl0 = 0110 h'2c0 irl3 to irl0 = 0111 h'2e0 irl3 to irl0 = 1000 h'300 irl3 to irl0 = 1001 h'320 irl3 to irl0 = 1010 h'340 irl3 to irl0 = 1011 h'360 irl3 to irl0 = 1100 h'380 irl3 to irl0 = 1101 h'3a0 irl3 to irl0 = 1110 h'3c0 note: exception codes h'120, h'140, and h'3e0 are reserved. 4.2.5 exception request masks when the bl bit in sr is 0, excep tions and interrupts are accepted. if a general exception event occurs when the bl bit in sr is 1, the cpu?s internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (h'a0000000) as for a reset. if a general interrupt occurs when bl = 1, the request is masked (held pending) and not accepted until the bl bit is cleared to 0 by software. for reentrant exception handling, the spc and ssr must be saved and the bl bit in sr cleared to 0.
section 4 exception handling rev.6.00 mar. 27, 2009 page 138 of 1036 rej09b0254-0600 4.2.6 returning from exception handling the rte instruction is used to return from exception handling. when rte is executed, the spc value is set in the pc, and the ssr value in sr, and the return from exception handling is performed by branching to the spc address. if the spc and ssr have been saved in the external memory, set the bl bit in sr to 1, then restore the spc and ssr, and issue an rte instruction. 4.3 register description there are four registers related to exception handling. these are peripheral module registers, and therefore reside in area p4. they can be accessed by specifying the address in the privileged mode only. 1. the exception event register (expevt) resi des at address h'ffffffd4, and contains a 12-bit exception code. the exception code set in expevt is that for a reset or general exception event. the exception code is set automatical ly by hardware when an exception occurs. expevt can also be modified by software. 2. interrupt event register 2 (intevt2) resides at address h'04000000, and contains a 12-bit exception code. the exception code set in inte vt2 is that for an interrupt request. the exception code is set automatically by hardware when an exception occurs. 3. the interrupt event register (intevt) resi des at address h'ffffffd8, and contains a 12-bit interrupt exception code or a code indicating the interrupt priority. which is set when an interrupt occurs depends on the interrupt source (see tables 7.4 and 7.5). the exception code or interrupt priority code is set automatically by hardware when an exception occurs. intevt can also be modified by software. 4. the trapa exception register (tra) reside s at address h'ffffffd0, and contains 8-bit immediate data (imm) for the trapa instruction. tra is set automatically by hardware when a trapa instruction is executed. tra can also be modified by software. the bit configurations of the expevt, intevt, intevt2, and tra registers are shown in figure 4.3.
section 4 exception handling rev.6.00 mar. 27, 2009 page 139 of 1036 rej09b0254-0600 31 0 0 exception code imm 00 11 0 expevt register, intevt and intevt2 registers 8-bit immediate data in trapa instruction imm: 0: reserved bits, always read as zero 31 00 920 tra register figure 4.3 bit configurations of ex pevt, intevt, intevt2, and tra registers 4.4 exception handling operation 4.4.1 reset the reset sequence is used to power up or restar t the SH7727 from the initialization state. the resetp and resetm signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the rtc) is suspended, all unfinished events are canceled, and reset processing is executed immedi ately. in the case of a manual reset, however, processing to retain external memory contents is continued. the reset sequence consists of the following operations: 1. the md bit in sr is set to 1 to place the SH7727 in privileged mode. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except nmi interrupt when blmsk bit is 1). 3. the rb bit in sr is set to 1. 4. an encoded value of h'000 in a power-on reset or h'020 in a manual reset is written to bits 11 to 0 of the expevt register to identify the exception event. 5. instruction execution jumps to the user-written exception handler at address h'a0000000. 4.4.2 interrupts an interrupt processing request is accepted on completion of the cu rrent instruction. the interrupt acceptance sequence consists of the following operations: 1. the contents of the pc and sr ar e saved in spc and ssr, respectively. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except nmi interrupt when blmsk bit is 1). 3. the md bit in sr is set to 1 to place the SH7727 in privileged mode. 4. the rb bit in sr is set to 1. 5. an encoded value identifying the exception event is written to bits 11 to 0 of the intevt and intevt2 registers.
section 4 exception handling rev.6.00 mar. 27, 2009 page 140 of 1036 rej09b0254-0600 6. instruction execution jumps to the vector location designated by the sum of the value of the contents of the vector base register (vbr) and h'00000600 to invoke the exception handler. 4.4.3 general exceptions when the SH7727 encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. the contents of the pc and sr are saved in the spc and ssr, respectively. 2. the bl bit in sr is set to 1, masking any subsequent exceptions (except nmi interrupt when blmsk bit is 1). 3. the md bit in sr is set to 1 to place the SH7727 in privileged mode. 4. the rb bit in sr is set to 1. 5. an encoded value identifying the exception ev ent is written to bits 11 to 0 of the expevt register. 6. instruction execution jumps to the vector location designated by either the sum of the vector base address and offset h'00000400 in the vector table in a tlb miss trap, or by the sum of the vector base address and offset h'00000100 for exceptions other than tlb miss traps, to invoke the exception handler. 4.5 individual exception operations this section describes the conditions for specific exception handling, and the processor operations. 4.5.1 resets ? power-on reset ? conditions: resetp low ? operations: expevt set to h'000, v br and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000 0000. in sr, the md, rb and bl bits are set to 1 and the interrupt mask bits (i3 to i0) is set to 1111. the cpu and on-chip supporting modules are initialized. see the register descrip tions in the relevant sections for details. a power-on reset must always be performed when powering on. a high level is output from the status0 and status1 pins.
section 4 exception handling rev.6.00 mar. 27, 2009 page 141 of 1036 rej09b0254-0600 ? manual reset ? conditions: resetm low ? operations: expevt set to h'020, v br and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000000 0. in sr, the md, rb, and bl bits are set to 1 and the interrupt mask bits (i3 to i0) is set to 1111. the cpu and on-chip supporting modules are initialized. see the register descrip tions in the relevant sections for details. a high level is output from the status0 and status1 pins. ? h-udi reset ? conditions: h-udi reset command input (s ee section 31.4.3, h-udi reset) ? operations: expevt set to h'000, v br and sr initialized, branch to pc = h'a0000000. initialization sets the vbr register to h'0000000 . in sr, the md, rb and bl bits are set to 1 and the interrupt mask bits (i3 to i0) is set to 1111. the cpu and on-chip supporting modules are initialized. see the register descrip tions in the relevant sections for details. table 4.4 types of reset internal state type conditions for transition to reset state cpu on-chip supporting modules power-on reset resetp = low initialized (see re gister configuration in relevant sections) manual reset resetm = low initialized h-udi reset h-udi reset command input initialized 4.5.2 general exceptions ? tlb miss exception ? conditions: comparison of tlb addresses shows no address match ? operations: the logical address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31 to 10). the asid of pteh indicates the asid at the time the exception occurred. the rc bit in mmucr is incremented by 1 when all ways are enabled, and if there is a disabled way, setting is prioritized starting from way 0. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. if the exception occu rred during a read, h'040 is se t in expevt; if the exception occurred during a write, h'060 is set in expevt. the bl, md and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0400.
section 4 exception handling rev.6.00 mar. 27, 2009 page 142 of 1036 rej09b0254-0600 to speed up tlb miss processing, the offset differs from other exceptions. ? tlb invalid exception ? conditions: comparison of tlb addresses shows address match but v = 0. ? operations: the logical address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31 to 10). the asid of pteh indicates the asid at the time the excepti on occurred. the way that generated the exception is set in the rc bits in mmucr. the pc and sr of the instruction that generated the exception are saved in the spc and ssr, respectively. if the exception occu rred during a read, h'040 is se t in expevt; if the exception occurred during a write, h'060 is set in expevt . the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? tlb exception/cpu address error in re peat loop ? conditions: tlb miss, tlb invalid or cpu address error in the last several instructions of repeat loop (see section 3.5.6, mmu exception in repeat loop) ? operations: tea, pteh and rc bit in mmu cr are set in the way of the type of exception. the sr of the instruction that generated the exception are saved in the ssr. but the spc is not the pc of the instruction that generated the exception. repeat loop can not be restarted after returning from exception handler. in order to complete a repeat loop, ensure not to cause tlb exceptions or cpu address error in the last seve ral instructions of repeat loop (see section 3.5.6, mmu exception in repeat loop). if the tlb exception or cpu address error occurred in the last several instructions of repeat loop, h'070 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? initial page write exception ? conditions: a hit occurred to th e tlb for a store access, but d = 0. this occurs for initial writes to the page registered by the load. ? operations: the logical address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31 to 10). the asid of pteh indicates the asid at the time the excepti on occurred. the way that generated the exception is set in the rc bit in mmucr. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. h'080 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs in pc = vbr + h'0100.
section 4 exception handling rev.6.00 mar. 27, 2009 page 143 of 1036 rej09b0254-0600 ? tlb protection exception ? conditions: when a hit access violates the tl b protection information (pr bits) shown below: pr privileged mode user mode 00 only read enabled no access 01 read/write enabled no access 10 only read enabled only read enabled 11 read/write enabled read/write enabled ? operations: the logical address (32 bits) that caused the exception is set in tea and the corresponding virtual page number (22 bits) is set in pteh (31 to 10). the asid of pteh indicates the asid at the time the excepti on occurred. the way that generated the exception is set in the rc bits in mmucr. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. if the exception occurred during a read, h'0a0 is set in expevt; if the exception occurred during a write, h'0c0 is set in expevt . the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? tlb protection violation in repeat loop ? conditions: tlb protection violation in the last several instruction of repeat loop (see section 3.5.6, mmu exception in repeat loop) ? operations: tea, pteh and rc bit in mmu cr are set in the way of the type of exception. the sr of the instruction that generated the exception are saved in the ssr. but the spc is not the pc of the instruction that generated the exception. repeat loop can not be restarted after returning from exception handler. in order to complete a repeat loop, ensure not to cause tlb exceptions or cpu address error in the last seve ral instructions of repeat loop (see section 3.5.6, mmu exception in repeat loop). if a tlb protection violation occurs in an instruction immediately before or during a repeat loop, h'0d0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? cpu address error ? conditions: a. instruction fetch from odd address (4n + 1, 4n + 3) b. word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d. virtual space accessed in user mode in the area h'80000000 to h'ffffffff.
section 4 exception handling rev.6.00 mar. 27, 2009 page 144 of 1036 rej09b0254-0600 ? operations: the logical address (32 bits) that caused the exception is set in tea. the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. if the exception occurred during a read, h'0e0 is set in expevt; if the exception occurred during a write, h'100 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. see section 3.5.5, processing flow in event of mmu exception, for more information. ? unconditional trap ? conditions: trapa instruction executed ? operations: the exception is a processing-com pletion type, so the pc of the instruction after the trapa instruction is saved to the spc. sr from the time when the trapa instruction was executing is saved to ssr. the 8-bit immediate value in the trapa instruction is quadrupled and set in tra (9 to 0). h'160 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. ? illegal general instruction exception ? conditions: a. when undefined code not in a delay slot is decoded delay branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s undefined instruction: h'fxxx b. when a privileged instruction not in a delay slot is decoded in user mode privileged instructions: ldc, stc, rt e, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. c. when a dsp instruction not in a delay slot is decoded without dsp extension (sr.dsp=0) dsp instructions: lds rm, dsr/a0/x0/x1/y0/y1, lds.l @rm+, dsr/a0/x0/x1/y0/y1, sts dsr/a0/x0/x1/y0/y1, rn, sts.l dsr/a0/x0/x1/y0/y1, @-rn, ldc rm, rs /re/mod, ldc.l @rm+, rs/re/mod, stc rs/re/mod, rn, stc.l rs/re/mod, @-rn, ldrs, ldre, setrc, movs, movx, movy, pxxx d. when an instruction that rewrites the pc/sr/rs/re in the last three instructions of repeat loop is decoded. instructions that rewrite the pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr instructions that rewrite the sr: ldc rm, sr, ldc.l @rm+, sr, setrc instructions that rewrite the rs: ldc rm, rs, ldc.l @rm+, rs, ldrs instructions that rewrite the re: ldc rm, re, ldc.l @rm+, re, ldre
section 4 exception handling rev.6.00 mar. 27, 2009 page 145 of 1036 rej09b0254-0600 ? operations: the pc and sr of the instruction that generated the exception are saved to the spc and ssr, respectively. h'180 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. when an undefined instruction other than h'fxxx is decoded, operation cannot be guaranteed. ? illegal slot instruction ? conditions: a. when undefined code in a delay slot is decoded delay branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s, undefined instruction: h'fxxx b. when an instruction that rewrites the pc in a delay slot is decoded instructions that rewrite the pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr c. when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rt e, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. d. when a dsp instruction in a delay slot is decoded without dsp extension (sr.dsp=0) dsp instructions: lds rm, dsr/a0/x0/x1/y0/y1, lds.l @rm+, dsr/a0/x0/x1/y0/y1, sts dsr/a0/x0/x1/y0/y1, rn, sts.l dsr/a0/x0/x1/y0/y1, @-rn, ldc rm, rs /re/mod, ldc.l @rm+, rs/re/mod, stc rs/re/mod, rn, stc.l rs/re/mod, @-rn, ldrs, ldre, setrc, movs, movx, movy, pxxx ? operations: the pc of the previous delay branch instruction is saved to the spc. sr of the instruction that generated the exception is sa ved to ssr. h'1a0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. when an undefined instruction other than h'fxxx is decoded, operation cannot be guaranteed. ? user break point trap ? conditions: when a break condition set in the user break cont roller is satisfied ? operations: when a post-execution break occurs, the pc of the instruction immediately after the instruction that set the break point is set in the spc. if a pre-execution break occurs, the pc of the instruction that set the break point is set in the spc. sr when the break occurs is set in ssr. h'1e0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. see section 8, user break controller (ubc), for more information.
section 4 exception handling rev.6.00 mar. 27, 2009 page 146 of 1036 rej09b0254-0600 ? dma address error ? conditions: a. word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) b. longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? operations: the pc of the instruction immediat ely after the instruction executed before the exception occurs is saved to the spc. sr wh en the exception occurs is saved to ssr. h'5c0 is set in expevt. the bl, md, and rb bits in sr are set to 1 and a branch occurs to pc = vbr + h'0100. 4.5.3 interrupts 1. nmi conditions: nmi pin edge detection operations: the pc and sr after the instruction that receives the interrupt are saved to the spc and ssr, respectively. h'1c0 is set to intevt and intevt2. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to pc = vbr + h'0600. this interrupt is not masked by sr.imask and received with top prio rity when the sr?s bl bit in sr is 0. when the bl bit is 1, the interrupt is masked. see section 7, inte rrupt controller (intc), for more information. 2. irl interrupts conditions: the value of the interrupt mask bits in sr is lower than the irl3 to irl0 level and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. operations: the pc value after the instruction at which the interrupt is acc epted is saved to the spc. sr at the time the interrupt is accepted is saved to ssr. the code corresponding to the irl3 to irl0 level is set in intevt and intevt2. the corresponding code is given as h'200 + [irl3 to irl0] h'20. see table 7.5, for the corresponding codes. the bl, md, and rb bits in sr are set to 1 and a branch occurs to vbr + h'0600. the received level is not set in sr.imask. see section 7, interrupt c ontroller (intc), for more information. 3. irq pin interrupts conditions: irq pin is asserted and sr.imask is lower than the irq priority level and the bl bit in sr is 0. the interrupt is accepted at an in struction boundary. operations: the pc value after the instruction at which the interrupt is acc epted is saved to the spc. the sr at the point the interrupt is accepted is saved to the ssr. the code corresponding to the interrupt source is set to intevt and intevt2. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to vbr + h'0 600. the received level is not set to sr.imask. see section 7, interrupt controller (intc), for more information.
section 4 exception handling rev.6.00 mar. 27, 2009 page 147 of 1036 rej09b0254-0600 4. pint pin interrupts conditions: the pint pin is asserted and sr.imask is lower than the pint priority level and the bl bit in sr is 0. the interrupt is accepted at an instruction boundary. operations: the pc value after the instruction at which the interrupt is acc epted is saved to the spc. the sr at the point the interrupt is accepted is saved to the ssr. the code corresponding to the interrupt source is set to intevt and intevt2. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to vbr + h'0 600. the received level is not set to sr.imask. see section 7, interrupt controller (intc), for more information. 5. on-chip peripheral interrupts conditions: sr.imask is lower than the on-chip module (tmu, rtc, sci, siof, scif, a/d, dmac, cpg, ref, pcc, usbh, usbf, lcdc, afei f) interrupt level and the bl bit in sr is 0. the interrupt is accepted at an instruc tion boundary. operations: the pc value after the instruction at which the interrupt is acc epted is saved to the spc. the sr at the point the interrupt is accepted is saved to the ssr. the code corresponding to the interrupt source is set to intevt a nd intevt2. the bl, md, and rb bits of the sr are set to 1 and a branch occurs to vbr + h'0 600. see section 7, interrupt controller (intc), for more information. 6. h-udi interrupt conditions: h-udi interrupt command is input (see section 31.4.4, h-udi interrupt), the value of the interrupt mask bits of sr is lower than 15, and the bl bit in sr is 0, the interrupt is accepted at an instruction boundary. operations: the pc after the inst ruction that accepts th e interrupt is saved to the spc. the sr at the point the interrupt is accepted is sa ved to the ssr. h'5e0 is set to intevt and intevt2. the bl, md, and rb bits of the sr are set to 1 and a bran ch occurs to vbr + h'0600. see section 7, interrupt controller (intc), for more information. 4.6 usage notes ? return from exception handling ? check the bl bit in sr with software. when the spc and ssr have been saved to external memory, set the bl bit in sr to 1 before restoring them. ? issue an rte instruction. set the spc in the pc and ssr in sr with the rte instruction, branch to the spc address, and return from exception handling. ? operation when exception or interrupt occurs while sr.bl = 1 ? interrupt: acceptance is suppressed until the bl bit in sr is set to 0 by software. if there is a request and the reception conditions are satisfied, the interrupt is accepted after the
section 4 exception handling rev.6.00 mar. 27, 2009 page 148 of 1036 rej09b0254-0600 execution of the instruction that sets the bl b it in sr to 0. during the sleep or standby mode, however, the interrupt will be accepted even when the bl bit in sr is 1. nmi is accepted when blmsk in icr1 is 1, regardless of the setting of the bl bit. ? exception: no user break point trap will oc cur even when the break conditions are met. when one of the other exceptions occurs, a branch is made to the fixed address of the reset (h'a0000000). in this case, the values of the expevt, spc, and ssr registers are undefined. ? spc when an exception occurs: the pc saved to the spc when an exception occurs is as shown below: ? re-executing-type exceptions: the pc of the instruction that caused the exception is set in the spc and re-executed after return from ex ception handling. if the exception occurred in a delay slot, however, the pc of the immediately prior delayed branch instruction is set in the spc. if the condition of the conditional delayed branch instruction is not satisfied, the delay slot pc is set in spc. ? completed-type exceptions and interrupts: the pc of the instruction after the one that caused the exception is set in the spc. if the exception was caused by a delayed conditional branch instruction, however, the br anch destination pc is set in spc. if the condition of the conditional delayed branch instru ction is not satisfied, the delay slot pc is set in spc. ? initial register values after reset ? undefined registers r0_bank0/1 to r7_bank0/1, r8 to r1 5, gbr, spc, ssr, mach, macl, pr ? initialized registers vbr = h'00000000 sr.md = 1, sr.bl = 1, sr.rb = 1, sr.i3 to sr.i0 = h'f. other sr bits are undefined. pc = h'a0000000 ? ensure that an exception is not generated at an rte instruction delay slot, as operation is not guaranteed in this case. ? when the bl bit in the sr register is set to 1, ensure that a tlb-related exception or address error does not occur at an ld c instruction that updates the sr register and the following instruction. this occurrence will be identified as multiple exceptions, and may initiate reset processing.
section 5 cache rev.6.00 mar. 27, 2009 page 149 of 1036 rej09b0254-0600 section 5 cache 5.1 overview 5.1.1 features the cache specifications are listed in table 5.1. table 5.1 cache specifications parameter specification capacity 16 kbytes structure instruction/data mix ed, 4-way set associative locking way 2 and way 3 are lockable line size 16 bytes number of entries 256 entries/way write system p0, p1, p3, u0: write-back/write-through selectable replacement method least-recently-used (lru) algorithm 5.1.2 cache structure the cache mixes data and instructions and uses a 4-way set associative system. it is composed of four ways (banks), each of which is divided into an address section and a data section. each of the address and data sections is divided into 256 entries. the data section of the entry is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 4 kbytes (16 bytes 256 entries), with a total of 16 kb ytes in the cache as a whole (4 ways). figure 5.1 shows the cache structure.
section 5 cache rev.6.00 mar. 27, 2009 page 150 of 1036 rej09b0254-0600 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 ? lw3: longword data 0 to 3 entry 0 entry 1 entry 255 0 1 255 0 1 255 v u tag address lw0 lw1 lw2 lw3 address array (ways 0 to 3) data array (ways 0 to 3) lru . . . . . . . . . . . . . . . . . . figure 5.1 cache structure address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicat es whether the entry has been written to in write- back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the address tag holds the physical address used in the external me mory access. it is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. in the SH7727, the top three of 32 physical addre ss bits are used as shadow bits (see section 12, bus state controller (bsc)), and th erefore in a normal replace operation the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by a power-on or manual reset. lru: with the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache. when an entry is registered, the lru shows which of the four ways it is recorded in. there are six lru bits, controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. in normal operation, four ways are used as cach e and six lru bits indicate the way to be replaced (table 5.2). if a bit pattern other than those listed in table 5.2 is set in the lru bits by software, the
section 5 cache rev.6.00 mar. 27, 2009 page 151 of 1036 rej09b0254-0600 cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 5.2. the lru bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. table 5.2 lru and way replacement lru (5?0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 5.1.3 register configuration table 5.3 shows details of the cache control register. table 5.3 register configuration register abbr. r/w size initial value address cache control register ccr r/ w longword h'00000000 h'ffffffec cache control register 2 ccr2 w longword h?00000000 h'040000b0 (h'a40000b0) * note: * when address translation by the mmu does not apply, the address in parentheses should be used. 5.2 register description 5.2.1 cache control register (ccr) the cache is enabled or disabled using the ce b it of the cache control register (ccr). ccr also has a cf bit (which invalidates all cache entries), and a wt and cb bits (whi ch select either write- through mode or write-back mode). programs that change the contents of the ccr register should be placed in address space that is not cached. fi gure 5.2 shows the conf iguration of the ccr register.
section 5 cache rev.6.00 mar. 27, 2009 page 152 of 1036 rej09b0254-0600 ce wt cf cb 0 1 2 3 4 5 6 31 ? : reserved bits. these bits are always read as 0. the write value should always be 0. cf: cache flush bit. writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entries to 0). always reads 0. write-back to external memory is not performed when the cache is flushed. wt: write-through bit. indicates the cache's operating mode for areas p0, u0 and p3. 1 = write-through mode, 0 = write-back mode. ce: cache enable bit. indicates whether the cache function is used. 1 = cache used, 0 = cache not used. cb: cache write-back bit. indicates the cache's operating mode for area p1. 1 = write-back mode, 0 = write-through mode. figure 5.2 ccr register configuration 5.2.2 cache control register 2 (ccr2) ccr2 register is used to enable or disable cache locking mechanism during dsp mode (cpu status register bit 12) only. executing a prefetch instruction (pref) during dsp mode will bring in one line size of data pointed by rn to cache , according to the setting of ccr2 [9:8] (w3load, w3lock) and [1:0] (w2load, w2lock): when ccr2[9:8]=11, during dsp mode pref @rn will bring the data into way 3. when ccr2[9:8]=00, 01 or 10 during dsp mode, or any setting during non-dsp mode, pref @rn will place the data into the way pointed by lru. when ccr2[1:0]=11, during dsp mode pref @rn will bring the data into way 2. when ccr2[1:0]=00, 01 or 10 during dsp mode, or any setting during non-dsp mode, pref @rn will place the data into the way pointed by lru. ccr2 must be set before cache is enabled. when a pref instruction is issued and there is a cache hit, the operation is treated as nop. figure 5.3 shows the configuration of the ccr2 register. the ccr2 register is a write-only register. if read, an undefined value will be returned.
section 5 cache rev.6.00 mar. 27, 2009 page 153 of 1036 rej09b0254-0600 31 9 8 7 2 1 0 w2 load w3 lock w3 load w2 lock w2lock: way 2 lock bit. w2load: way 2 load bit. when w2lock = 1 & w2load = 1 & dsp = 1, the prefetched data will always be loaded into way2. in all other conditions the prefetched data will be loaded into the way pointed by lru. w3lock: way 3 lock bit. w3load: way 3 load bit. when w3lock = 1 & w3load = 1 & dsp = 1, the prefetched data will always be loaded into way3. in all other conditions the prefetched data will be loaded into the way pointed by lru. note: w2load and w3load should not be set to high at the same time. figure 5.3 ccr2 register configuration whenever ccr2 bit 8 (w3lock) or bit 0 (w2lock) is high the cache is locked. the locked data will not be overwritten unless w3lock b it and w2lock bit are reset or the pref condition during dsp mode matched. during cache locking mode, the lru in table 5.2 will be replaced by tables 5.4 to 5.6. table 5.4 lru and way replacement (when w2lock=1) lru (5?0) way to be replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 table 5.5 lru and way replacement (when w3lock=1) lru (5?0) way to be replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0
section 5 cache rev.6.00 mar. 27, 2009 page 154 of 1036 rej09b0254-0600 table 5.6 lru and way replacement (when w2lock=1 and w3lock=1) lru (5?0) way to be replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 5.3 cache operation 5.3.1 searching the cache if the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired in struction or data is in the cach e. figure 5.4 illustrates the method by which the cache is searched. the cache is a physical cache and holds physical addresses in its address section. entries are selected using bits 11 to 4 of the address (virtual ) of the access to memory and the address tag of that entry is read. in parallel to reading of the address tag, the logical address is translated to a physical address in the mmu. the physical address after translation and the physical address read from the address section are compared. the address comp arison uses all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 5.4 shows a hit on way 1.
section 5 cache rev.6.00 mar. 27, 2009 page 155 of 1036 rej09b0254-0600 0 1 255 v u tag address lw0 lw1 lw2 lw3 ways 0 to 3 ways 0 to 3 31 12 11 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 5.4 cache search scheme
section 5 cache rev.6.00 mar. 27, 2009 page 156 of 1036 rej09b0254-0600 5.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the lru is updated. read miss: an external bus cycle starts and the entr y is updated. the way replaced is the one least recently used. entries are updated in 16-byte units. when the desired in struction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is lo aded in the cache, the u bit is cleared to 0 and the v bit is set to 1. in the write-back mode, when the u bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. after the cache completes its update cycle, the write-back buffer writes back the entry to the memory. the write-back unit is 16 bytes. 5.3.3 prefetch operations prefetch hit: the lru is updated so that the hit wa y becomes the most recent. other cache contents are not updated. instruction or da ta transfer to the cpu is not performed. prefetch miss: instruction or data transfer to the cpu is not performed, and the way replaced is as shown in table 5.2, table 5.4, table 5.5, and table 5.6. other operations are the same as in the case of a read miss. 5.3.4 write access write hit: in a write access in the write-back mode, the data is written to the cache and the u bit of the entry written is set to 1. writing occurs only to the cache; no external memory write cycle is issued. in the write-through mode, the data is written to the cache and an external memory write cycle is issued. write miss: in the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. the way to be replaced is th e one least recently used. when the u bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write- back buffer. the write-back unit is 16 bytes. data is written to the cache and the u bit is set to 1 and the v bit is also set to 1. after the cache completes its update cycle, the write-back buffer writes back the entry to the memory. in the write -through mode, no write to cache occurs in a write miss; the write is only to the external memory.
section 5 cache rev.6.00 mar. 27, 2009 page 157 of 1036 rej09b0254-0600 5.3.5 write-back buffer when the u bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. to increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to th e cache takes priority over writing back to the external memory. during the wr ite back cycles, the cache can be accessed. the write-back buffer can hold one line of the cache data (16 bytes) an d its physical address. figure 5.5 shows the configuration of the write-back buffer. longword 0 longword 1 longword 2 longword 3 pa (31 to 4) pa (31 to 4): longword 0 to 3: physical address written to external memory the line of cache data to be written to external memory figure 5.5 write-back buffer configuration 5.3.6 coherency of cach e and external memory use software to ensure coherency between the cache and the external memory. when memory shared by this lsi and another device is accessed, the latest data may be in a write-back mode cache, so invalidate the entry that includes the latest data in the cache, generate a write back, and update the data in memory before using it. when the caching area is updated by a device other than the SH7727, invalidate the entry that includes the updated data in the cache. 5.4 memory-mapped cache to allow software management of the cache, cache contents can be read and written by means of mov instructions in the privileged mode. the cache is mapped onto the p4 area in logical address space. the address array is mapped onto addre sses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. on ly longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 address array the address array is mapped onto h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifi es information for selecting the entry to be accessed; the data field specifies the address, v bit, u bit, and lru bits to be written to the address array ((1) in figure 5.6).
section 5 cache rev.6.00 mar. 27, 2009 page 158 of 1036 rej09b0254-0600 in the address field, specify the entry address sel ecting the entry (bits 11 to 4), w for selecting the way (bits 12 and 11: in normal mode (8-kbyte cache) , 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and h'f0 to indicate address array access (bits 31 to 24). when writing, specify bit 3 as the a bit. the a bit indicates whether addresses are compared during writing. when the a bit is 1, the addresse s of four entries select ed by the entry addresses are compared to the addresses to be written into the address array specified in the data field. writing takes place to the way that has a hit. when a miss occurs, nothing is written to the address array and no operation occurs. the way number (w) specified in bits 12 and 11 is not used. when the a bit is 0, it is written to the entry selected with the entry address and way number without comparing addresses. the address sp ecified by bits 31 to 10 in the data specification in figure 5.6 (1), address array access, is a logical address. when the mmu is enabled, the address is translated into a physical address, then the physical address is used in comparing addresses when the a bit is 1. the physical address is written into the address array. when reading, the address tag, v bit, u bit, an d lru bits of the entry specified by the entry address and way number (w) are read using the data format shown in figure 5.6 without comparing addresses. to invalidat e a specific entry, specify the en try by its entry address and way number, and write 0 to its v bit. to invalidate only an entry for an address to be invalidated, specify 1 for the a bit. when an entry for which 0 is written to the v bit has a u bit set to 1, it will be written back. this allows coherency to be achieved between the ex ternal memory and cache by invalidating the entry. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. in the SH7727, the upper 3 bits of the 32-bit phy sical address are treated as a shadow field (see section 12, bus state controller (bsc)). therefore, when a cache miss occurs, 0 is stored in the upper 3 bits of the address array address tag. when using an mov instruction to modify the address array directly, a nonzero value must not be written to the upper 3 bits of the address tag. 5.4.2 data array the data array is mapped onto h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit da ta field (for write accesse s) must be specified. the address field specifies information for sel ecting the entry to be accessed; the data field specifies the longword data to be written to the data array ((2) in figure 5.6).
section 5 cache rev.6.00 mar. 27, 2009 page 159 of 1036 rej09b0254-0600 specify the entry address for selecting the entry (bits 11 to 4), l indicating the longword position within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3), w for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and h'f1 to indicate data array access (bits 31 to 24). both reading and writing use the longword of the data array specified by the entry address, way number and longword address. the access size of the data array is fixed at longword. 1. address array access address specification read access write access data specification 2. data array access (both read and write accesses) address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 * * * * * * * * w entry 31 24 23 14 13 12 11 4 3 0 1111 0000 w entry 2 a 31 30 29 10 4 3 0 lru 2 x 000 x 9 address tag (31 ? 10) uv 1 31 24 23 14 13 12 11 4 3 0 1111 0001 w entry 1 2 l data specification 31 0 longword x: 0 for read, don't care for write * : don't care bit 000 00 00 2 figure 5.6 specifying address and data for memory-m apped cache access
section 5 cache rev.6.00 mar. 27, 2009 page 160 of 1036 rej09b0254-0600 5.5 usage examples 5.5.1 invalidating specific entries specific cache entries can be invalidated by writing 0 to the entry?s v bit. when the a bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a matc h is found. if no match is found, there is no operation. r0 specifies the write data in r0 and r1 specifies the address. when the v bit of an entry in the address array is set to 0, the en try is written back if the entry?s u bit is 1. ; r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ; r1 = h'f0000088; address array access, entry = b'00001000, a = 1 ; mov.l r0,@r1 5.5.2 reading the data of a specific entry this example reads the data section of a specific cache entry. the longword indicated in the data field of the data array in figure 5.6 is read to th e register. r0 specifies the address and r1 is read. ; r1 = h'f100 004c; data array access, entry = b'00000100, way = 0, ; longword address = 3 ; mov.l @r0,r1 ; longword 3 is read.
section 6 x/y memory rev.6.00 mar. 27, 2009 page 161 of 1036 rej09b0254-0600 section 6 x/y memory 6.1 overview the SH7727 has on-chip x-ram and y-ram. it can be used by cpu, dsp and dmac to store instructions or data. 6.1.1 features the x/y memory features are listed in table 6.1. table 6.1 x/y memory specifications parameter features addressing method user selectable mapping mechanism ? fixed mapping for mission-critical realtime applications (p2/uxy area) ? automatic mapping through tlb for easy to use (p0/p3/u0 area) ports 3 independent read/write ports ? 8-/16-/32-bit access from the cpu ? maximum of two simultaneous 16-bi t accesses, or 16/32-bit accesses, from the dsp ? 8-/16-/32-bit access from the dmac size 8-kbyte ram for x and y memory each
section 6 x/y memory rev.6.00 mar. 27, 2009 page 162 of 1036 rej09b0254-0600 6.2 x/y memory access from the cpu the x/y memory can be located in either map-enabled area or fixed-mapped area, depending on the mode bit (md) and dsp bit (dsp) setting in th e status register (sr). figure 6.1 shows x/y memory logical mapping. 1. privileged mode md = 1, dsp = 0; any physical address in space p0 or p3 can map to x/y memory through tlb translation. addresses ranging from h'a500 0000 to h'a5ff ffff in the p2 space can also fixed map to x/y memory. since the dsp extension is disabled, the dsp instruction set and registers are not availabl e to the programmer. 2. user mode md = 0, dsp = 0; any physi cal address in the u0 space can access x/y memory through tlb translation. any access to addresses beyond the u0 space will cau se an address er ror. since the dsp extension is disabled, the dsp instructio n set and registers are not available to the programmer. 3. privileged-dsp mode md = 1, dsp = 1; any physical address in space p0 or p3 can map to x/y memory through tlb translation. addresses ranging from h'a500 0000 to h'a5ff ffff in the p2 space can also fixed-map to x/y memory. since the dsp extension is enabled, the dsp instruction set and registers are available to the programmer. 4. user-dsp mode md = 0, dsp = 1; any physi cal address in space u0 can ma p to x/y memory through tlb translation. addresses ranging from h'a500 0000 to h'a5ff ffff in the uxy spaces can also fixed map to x/y memory. any access to outside of u0 and uxy space will cause an address error. since the dsp extension is enabled, the ds p instruction set and registers are available to the programmer. it is recommended that for the mappable area, the c (cacheable) bit in the tlb entry must be set to 0 to guarantee a two-cycle access. mapping through tlb translation provides a flexible x/y memory addressing scheme but takes two cycles even when the c bit in the tlb entr y is cleared to 0. fixed mapping provides a one- cycle access for read and two-cycle access for write , which is the appropriate method for mission- critical realtime operations.
section 6 x/y memory rev.6.00 mar. 27, 2009 page 163 of 1036 rej09b0254-0600 the x/y memory resides on the second 16 mb of physical address space area 1, from h'a500 0000 to h'a5ff ffff. these 16-mb address spaces are shadowed and maps to the same 128- kbyte x/y rom/ram. figures 6.1 and 6.2 show x/y memory physical mapping. p4 p3 p2 p1 p0 md = 1, dsp = 0 privileged mode same as sh-3 in md = 1, cpu can change dsp bit address error u0 md = 0, dsp = 0 user mode same as sh-3 in md = 0, user cannot change dsp bit address error address error u0 md = 0, dsp = 1 user dsp mode uxy: address range from h'a500 0000 to h'a5ff ffff p4 p3 p2 p1 p0 md = 1, dsp = 1 privileged dsp mode in md = 1, cpu can change dsp bit x y x y address range from h'a500 0000 to h'a5ff ffff figure 6.1 x/y memory logical address mapping
section 6 x/y memory rev.6.00 mar. 27, 2009 page 164 of 1036 rej09b0254-0600 128-kbyte x/y memory x-rom/x-ram reserved space x-rom/x-ram reserved space y-rom/y-ram reserved space y-rom/y-ram reserved space x-ram, 8 kbytes y-ram, 8 kbytes a501ffff a5018fff a5017000 a5010000 a5008fff a5007000 a5000000 area 1, 64 mbytes i/o register space 16 mbytes reserved space 16 mbytes reserved area 32 mbytes 7ffffff x/y memory 6000000 5020000 5000000 4000000 figure 6.2 x/y memory physical address mapping 6.3 x/y memory access from the dsp the x/y memory can be accessed by the dsp through the x bus and y bus. a ccesses via the x bus/y bus are always 16-bit, while accesses via the l bus are either 16-bit or 32-bit. accesses via the x bus and y bus cannot be specified simultaneously. 6.4 x/y memory access from the dmac the x/y memory also exists on the i bus an d can be accessed by the dmac. the dmac access is 8-/16-/32-bit unit. if the i bus accesses x/y memory simulta neously with an access from x bus/y bus or l bus, the i bus master has a higher priority. to access the x/y memory by the dmac, the physi cal address from h?05 000000 to h?0501ffff should be used.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 165 of 1036 rej09b0254-0600 section 7 interrup t controller (intc) 7.1 overview the interrupt controller (intc) ascertains the prior ity of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 7.1.1 features intc has the following features: ? 16 levels of interrupt priority can be set: by setting the five interrupt-priority registers, the priorities of on-chip supporting module, irq, an d pint interrupts can be selected from 16 levels for individual request sources. ? nmi noise canceller function: nmi input-level bit indicates nmi pin states. by reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceller.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 166 of 1036 rej09b0254-0600 7.1.2 block diagram figure 7.1 is a block diagram of the intc. dmac siof scif sci adc tmu rtc wdt ref h-udi icr input control com- parator priority identifier 3 4 6 16 interrupt request sr ipra to iprg irl3 to irl0 nmi irq0 to irq5 pint0 to pint15 timer unit realtime clock unit serial communication interface serial communication interface (with fifo) watchdog timer refresh requests in the bus state controller interrupt control register registers a-e for setting the interrupt proprity levels status register tmu: rtc: sci: scif: wdt: ref: icr: ipra to iprg: sr: (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (refresh request) (interrupt request) ipr cpu internal bus bus interface 2 1 0 intc legend: direct memory access controller analog-to-digital converter hitachi user-debugging interface pcmcia controller lcd controller usb host usb function controller afe interface serial io dmac: adc: h-udi: pcc: lcdc: usbh: usbf: afe: siof: pcc lcdc usbh usbf afe (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) figure 7.1 intc block diagram
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 167 of 1036 rej09b0254-0600 7.1.3 pin configuration table 7.1 lists the intc pin configuration. table 7.1 pin configuration name abbreviation i/o description nonmaskable interrupt input pin nmi i input of interrupt request signal, which is nonmaskable by sr.imask interrupt input pins irq5 to irq0 irl3 to irl0 i input of interrupt request signals, which is maskable by sr.imask port interrupt input pins pint0 to pint15 i port input of interrupt request signals, which is maskable by sr.imask 7.1.4 register configuration the intc has 17 registers listed in table 7.2.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 168 of 1036 rej09b0254-0600 table 7.2 register configuration name abbr. r/w initial value * 1 address access size interrupt control register 0 icr0 r/w * 2 h'fffffee0 16 interrupt control register 1 icr1 r/w h'0000 h'04000010 (h'a4000010) * 3 16 interrupt control register 2 icr2 r/w h'0000 h'04000012 (h'a4000012) * 3 16 interrupt control register 3 icr3 r/w h'0000 h'04000228 (h'a4000228) * 3 16 pint interrupt enable register pinter r/w h'0000 h'04000014 (h'a4000014) * 3 16 interrupt priority level setting register a ipra r/w h'0000 h'fffffee2 16 interrupt priority level setting register b iprb r/w h'0000 h'fffffee4 16 interrupt priority level setting register c iprc r/w h'0000 h'04000016 (h'a4000016) * 3 16 interrupt priority level setting register d iprd r/w h'0000 h'04000018 (h'a4000018) * 3 16 interrupt priority level setting register e ipre r/w h'0000 h'0400001a (h'a400001a) * 3 16 interrupt priority level setting register f iprf r/w h'0000 h'04000220 (h'a4000220) * 3 16 interrupt priority level setting register g iprg r/w h'0000 h'04000222 (h'a4000222) * 3 16 interrupt request register 0 irr0 r/w h'00 h'04000004 (h'a4000004) * 3 8 interrupt request register 1 irr1 r h'00 h'04000006 (h'a4000006) * 3 8 interrupt request register 2 irr2 r h'00 h'04000008 (h'a4000008) * 3 8 interrupt request register 3 irr3 r h'00 h'04000224 (h'a4000224) * 3 16 interrupt request register 4 irr4 r h'00 h'04000226 (h'a4000226) * 3 16 notes: 1. initialized by a power-on or manual reset. 2. h'8000 when the nmi pin is at high level. h'0000 when the nmi pin is at low level. 3. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 169 of 1036 rej09b0254-0600 7.2 interrupt sources there are five types of interrupt sources: nmi, irq, irl, pint, and on-chip supporting modules. each interrupt has priority levels (0 to 16) with 0 the lowest and 16 the highest. priority level 0 masks an interrupt. 7.2.1 nmi interrupts the nmi interrupt has the highest priority leve l of 16. when the blmsk bit of the interrupt control register (icr1) is 1 or the bl bit of the status register (sr) is 0, nmi interrupts are accepted when the mai bit of the icr1 register is 0. nmi interr upts are edge-detected. in sleep or standby mode, the interrup t is accepted regardless of the bl. th e nmi edge select bit (nmie) in the interrupt control register 0 (icr0) is used to se lect either the rising or falling edge. when the nmie bit of the icr0 register is changed, the nm i interrupt is not detected for 20 cycles after changing the icr0.nmie to avoid a false detecti on of the nmi interrupt. nmi interrupt exception handling does not affect the interrupt mask level bits (i3 to i0) in the status register (sr). when the blmsk bit of the icr1 register is se t to 1 and only nmi interrupts are accepted, the spc register and ssr register are updated by the nmi interrupt handler, making it impossible to return to the original processing from exception handling initiated prior to the nmi. use should therefore be restricted to cases where return is not necessary. it is possible to wake the chip up from the standby state with an nmi interrupt (except when the mai bit of the icr1 register is set to 1). 7.2.2 irq interrupt irq interrupts are input by priority from pins irq0 to irq5 with a level or an edge. the priority level can be set by priority setting registers c, d (iprc, iprd) in a range from levels 0 to 15. when using edge sensing for irq interrupts, do the following to clear ir0. to clear bits irq5r to irq0r to 0, read from i rr0 before writing. after confirming that the bits to be cleared to 0 are set to 1, write 0 to them. in this case write 0 only to the bits to be cleared; write 1 to the other bits. the values of the bits to which 1 is written do not change. when level sensing is used for irq interrupts, bits irq5r to irq0r indicate whether or not an interrupt request has been input. they can be set and cleared by the values input to pins irq5r to irq0r alone.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 170 of 1036 rej09b0254-0600 when the icr1 register is rewritten, irq interrupt s may be mistakenly detected, depending on the pin states. to prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (irr0). it is necessary for an edge input interrupt det ection to input a pulse width more than two-cycle width by p clock basis. with level detection, the level must be mainta ined until the interrupt is accepted and the cpu starts interrupt handling. the interrupt mask bits (i3 to i0) of the status register (sr) are not affected by irq interrupt processing. interrupts irq5 to irq0 can be used to wake the chip up from the software standby mode (but only when the rtc 32 khz oscillator is used). in this case, the priority level of the interrupt to be used must be higher than the level of bits i3 to i0 in the sr register. notes: the following cautions apply when irq edge detection is used: 1. if an irq edge is input immediately befo re the cpu enters the standby mode (between when the cpu executes the sleep instruc tion and when status0 goes high), the interrupt may not be detected properly. after this, if the irq edge is input again after status0 goes high, the interrupt will be detected. 2. if an irq edge is input while the frequency is changing due to a change in the value of the stc bit in the frqcr register (during the count by wdt), the interrupt may not be detected properly. if the irq edge is input again after the wdt count completes, the interrupt will be detected. 7.2.3 irl interrupts irl interrupts are input by level at pins irl3 to irl0 . the priority level is the higher level indicated by pins irl3 to irl0 . an irl3 to irl0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). a value of 15 (1111) indicates no interrupt request (interrupt priority level 0). figure 7.2 shows an example of an irl interrupt connection. table 7.3 shows irl pins and interrupt levels.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 171 of 1036 rej09b0254-0600 interrupt request priority encoder irl3 to irl0 4 SH7727 irl3 to irl0 figure 7.2 example of irl interrupt connection table 7.3 irl3 to irl0 pins and interrupt levels irl3 irl2 irl1 irl0 interrupt priority level interrupt request 0 0 0 0 15 level 15 interrupt request 0 0 0 1 14 level 14 interrupt request 0 0 1 0 13 level 13 interrupt request 0 0 1 1 12 level 12 interrupt request 0 1 0 0 11 level 11 interrupt request 0 1 0 1 10 level 10 interrupt request 0 1 1 0 9 level 9 interrupt request 0 1 1 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 0 0 1 6 level 6 interrupt request 1 0 1 0 5 level 5 interrupt request 1 0 1 1 4 level 4 interrupt request 1 1 0 0 3 level 3 interrupt request 1 1 0 1 2 level 2 interrupt request 1 1 1 0 1 level 1 interrupt request 1 1 1 1 0 no interrupt request a noise-cancellation feature is built in, and the irl interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the irl pin change is detected. in the standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-khz clock for th e rtc instead. therefore
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 172 of 1036 rej09b0254-0600 when the rtc is not used, interruption by means of irl interrupts cannot be performed in standby mode. the priority level of the irl interrupt must not be lowered unless the interrupt is accepted and the interrupt processing starts. correct operation cannot be guaranteed if the level is not maintained. however, the priority level can be changed to a higher one. the interrupt mask bits (i3 to i0) in the status register (sr) are not a ffected by irl interrupt processing. 7.2.4 pint interrupt pint interrupts are input by priority from pins pi nt0 to pint15 with a level. the priority level can be set by priority setting registers d (iprd) in a range from levels 0 to 15, in the unit of pint0 to pint7 or pint8 to pint15. the pint interrupt level should be held until the interrupt is accepted an d interrupt handling is started. the interrupt mask bits (i3 to i0) of the status register (sr) are not affected by pint interrupt processing. pint interrupts can wake the chip up from the st andby state when the relevant interrupt level is higher than i3 to i0 in the sr register (but only when the rtc 32-khz oscillator is used). 7.2.5 on-chip support ing module interrupts on-chip supporting module interrupts are generated by the following fourteen modules: ? timer unit (tmu) ? realtime clock (rtc) ? serial communication interface (sci, scif) ? bus state controller (bsc) ? watchdog timer (wdt) ? direct memory access controller (dmac) ? analog-to-digital converter (adc) ? pc card controller (pcc) ? ohci compliant usb host controller (usbh) ? usb function controller (usbf) ? afe interface (afeif) ? lcd controller (lcdc)
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 173 of 1036 rej09b0254-0600 ? user-debugging interface (h-udi) ? serial io (siof) not every interrupt source is assigned a different interrupt vector. sources are reflected on the interrupt event register (intevt and intevt2). it is easy to identify sources by using the values of the intevt or intevt2 register as branch offsets. the priority level (from 0 to 15) can be set fo r each module except for h-udi by writing to the interrupt priority setting registers a to g (ipra to iprg). the priority level of h-udi interrupt is 15 (fixed). the interrupt mask bits (i3 to i0) of the status register are not affected by the on-chip supporting module interrupt processing. tmu and rtc interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than i3 to i0 in the sr register (but only when the rtc 32-khz oscillator is used). 7.2.6 interrupt exceptio n handling and priority tables 7.4 and 7.5 list the codes for the interrupt event register (intevt and intevt2), and the order of interrupt priority. each interrupt source is assigned unique code. the start address of the interrupt service routine is common to each interrupt source. this is why, for instance, the value of intevt or intevt2 is used as offset at the star t of the interrupt service routine and branched to identify the interrupt source. the order of priority of the on-chip supporting module, irq, and pint interrupts is set within the priority levels 0 to 15 at will by using the interru pt priority level set to registers a to g (ipra to iprg). the order of priority of the on-chip supporting module, irq, and pint interrupts is set to zero by reset. when the order of priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they ar e processed according to the default order listed in tables 7.4 and 7.5.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 174 of 1036 rej09b0254-0600 table 7.4 interrupt exception handlin g sources and priority (irq mode) interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 (h'1c0) 16 ? ? high h-udi h'5e0 (h'5e0) 15 ? ? irq irq0 h'200?3c0 * (h'600) 0?15 (0) iprc (3?0) ? irq1 h'200?3c0 * (h'620) 0?15 (0) iprc (7?4) ? irq2 h'200?3c0 * (h'640) 0?15 (0) iprc (11?8) ? irq3 h'200?3c0 * (h'660) 0?15 (0) iprc (15?12) ? irq4 h'200?3c0 * (h'680) 0?15 (0) iprd (3?0) ? irq5 h'200?3c0 * (h'6a0) 0?15 (0) iprd (7?4) ? pint pint0?7 h'200?3c0 * (h'700) 0?15 (0) iprd (15?12) ? pint8?15 h'200?3c0 * (h'720) 0?15 (0) iprd (11?8) ? dmac dei0 h'200?3c0 * (h'800) 0?15 (0) ipre (15?12) high dei1 h'200?3c0 * (h'820) dei2 h'200?3c0 * (h'840) dei3 h'200?3c0 * (h'860) low scif eri2 h'200?3c0 * (h'900) 0?15 (0) ipre (7?4) high rxi2 h'200?3c0 * (h'920) bri2 h'200?3c0 * (h'940) txi2 h'200?3c0 * (h'960) low adc adi h'200?3c0 * (h'980) 0?15 (0) ipre (3?0) ? lcdc lcdci h'200?3c0 * (h'9a0) 0?15 (0) iprf(11?8) ? siof siferi h'200?3c0 * (h'b00) 0?15 (0) iprf(3?0) high siftxi h'200?3c0 * (h'b20) 0?15 (0) sifrxi h'200?3c0 * (h'b40) 0?15 (0) sifcci h'200?3c0 * (h'b60) 0?15 (0) low usbh usbhi h'200?3c0 * (h'a00) 0?15 (0) iprg(15?12) ? usbfi0 h'200?3c0 * (h'a20) 0?15 (0) iprg(11?8) high usbf usbfi1 h'200?3c0 * (h'a40) 0?15 (0) iprg(7?4) low afeif afeifi h'200?3c0 * (h'a 60) 0?15 (0) iprg(3?0) ? low
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 175 of 1036 rej09b0254-0600 interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority pcc0 pc0swir h'200?3c0 * (h'9c0) 0?15 (0) iprf(7?4) high high pc0irir h'200?3c0 * (h'9c0) 0?15 (0) pc0scir h'200?3c0 * (h'9c0) 0?15 (0) pc0cdir h'200?3c0 * (h'9c0) 0?15 (0) pc0rcir h'200?3c0 * (h'9c0) 0?15 (0) pc0bwir h'200?3c0 * (h'9c0) 0?15 (0) pc0bdir h'200?3c0 * (h'9c0) 0?15 (0) low tmu0 tuni0 h'400 (h'400) 0?15 (0) ipra (15?12) ? tmu1 tuni1 h'420 (h'420) 0?15 (0) ipra (11?8) ? tmu2 tuni2 h'440 (h'440) 0?15 (0) ipra (7?4) ? rtc ati h'480 (h'480) 0?15 (0) ipra (3?0) high pri h'4a0 (h'4a0) cui h'4c0 (h'4c0) low sci0 eri h'4e0 (h'4e0) 0?15 (0) iprb (7?4) high rxi h'500 (h'500) txi h'520 (h'520) tei h'540 (h'540) low wdt iti h'560 (h'560) 0?15 (0) iprb (15?12) ? ref rcmi h'580 (h'580) 0?15 (0) iprb (11?8) high rovi h'5a0 (h'5a0) low low note: * the code corresponding to an interrupt level shown in table 7.6 is set.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 176 of 1036 rej09b0254-0600 table 7.5 interrupt exception handlin g sources and priority (irl mode) interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 (h'1c0) 16 ? ? high h-udi h'5e0 (h'5e0) 15 ? ? irl irl(3:0) = 0000 h'200 (h'200) 15 ? ? irl(3:0) = 0001 h'220 (h'220) 14 ? ? irl(3:0) = 0010 h'240 (h'240) 13 ? ? irl(3:0) = 0011 h'260 (h'260) 12 ? ? irl(3:0) = 0100 h'280 (h'280) 11 ? ? irl(3:0) = 0101 h'2a0 (h'2a0) 10 ? ? irl(3:0) = 0110 h'2c0 (h'2c0) 9 ? ? irl(3:0) = 0111 h'2e0 (h'2e0) 8 ? ? irl(3:0) = 1000 h'300 (h'300) 7 ? ? irl(3:0) = 1001 h'320 (h'320) 6 ? ? irl(3:0) = 1010 h'340 (h'340) 5 ? ? irl(3:0) = 1011 h'360 (h'360) 4 ? ? irl(3:0) = 1100 h'380 (h'380) 3 ? ? irl(3:0) = 1101 h'3a0 (h'3a0) 2 ? ? irl(3:0) = 1110 h'3c0 (h'3c0) 1 ? ? irq irq4 h'200?3c0 * (h'680) 0?15 (0) iprd (3?0) ? irq5 h'200?3c0 * (h'6a0) 0?15 (0) iprd (7?4) ? pint pint0?7 h'200?3c0 * (h'700) 0?15 (0) iprd (15?12) ? pint8?15 h'200?3c0 * (h'720) 0?15 (0) iprd (11?8) ? dmac dei0 h'200?3c0 * (h'800) 0?15 (0) ipre (15?12) high dei1 h'200?3c0 * (h'820) dei2 h'200?3c0 * (h'840) dei3 h'200?3c0 * (h'860) low scif eri2 h'200?3c0 * (h'900) 0?15 (0) ipre (7?4) high rxi2 h'200?3c0 * (h'920) bri2 h'200?3c0 * (h'940) txi2 h'200?3c0 * (h'960) low low
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 177 of 1036 rej09b0254-0600 interrupt source intevt code (intevt2 code) interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority adc adi h'200?3c0 * (h'980) 0?15 (0) ipre (3?0) ? high lcdc lcdci h'200?3c0 * (h'9a0) 0?15 (0) iprf (11?8) ? siof siferi h'200?3c0 * (h'b00) 0?15 (0) iprf (3?0) high siftxi h'200?3c0 * (h'b20) 0?15 (0) sifrxi h'200?3c0 * (h'b40) 0?15 (0) sifcci h'200?3c0 * (h'b60) 0?15 (0) low usbh usbhi h'200?3c0 * (h'a00) 0?15 (0) iprg (15?12) ? usbf usbfi0 h'200?3c0 * (h'a20) 0?15 (0) iprg (11?8) high usbfi1 h'200?3c0 * (h'a40) 0?15 (0) iprg (7?4) low afeif afeifi h'200?3c0 * (h'a60) 0?15 (0) iprg (3?0) ? pcc0 pc0swir h'200?3c0 * (h'9c0) 0?15 (0) iprf (7?4) high pc0irir h'200?3c0 * (h'9c0) 0?15 (0) pc0scir h'200?3c0 * (h'9c0) 0?15 (0) pc0cdir h'200?3c0 * (h'9c0) 0?15 (0) pc0rcir h'200?3c0 * (h'9c0) 0?15 (0) pc0bwir h'200?3c0 * (h'9c0) 0?15 (0) pc0bdir h'200?3c0 * (h'9c0) 0?15 (0) low tmu0 tuni0 h'400 (h'400) 0?15 (0) ipra (15?12) ? tmu1 tuni1 h'420 (h'420) 0?15 (0) ipra (11?8) ? tmu2 tuni2 h'440 (h'440) 0?15 (0) ipra (7?4) ? rtc ati h'480 (h'480) 0?15 (0) ipra (3?0) high pri h'4a0 (h'4a0) cui h'4c0 (h'4c0) low sci0 eri h'4e0 (h'4e0) 0?15 (0) iprb (7?4) high rxi h'500 (h'500) txi h'520 (h'520) tei h'540 (h'540) low wdt iti h'560 (h'560) 0?15 (0) iprb (15?12) ? ref rcmi h'580 (h'580) 0?15 (0) iprb (11?8) high rovi h'5a0 (h'5a0) low low note: * the code corresponding to an interrupt level shown in table 7.6 is set.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 178 of 1036 rej09b0254-0600 table 7.6 interrupt level and intevt code interrupt level intevt code 15 h'200 14 h'220 13 h'240 12 h'260 11 h'280 10 h'2a0 9 h'2c0 8 h'2e0 7 h'300 6 h'320 5 h'340 4 h'360 3 h'380 2 h'3a0 1 h'3c0
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 179 of 1036 rej09b0254-0600 7.3 intc registers 7.3.1 interrupt priority regi sters a to g (ipra to iprg) interrupt priority registers a to g (ipra to iprg) are 16-bit read/write regi sters that set priority levels from 0 to 15 for on-chip supporting module , irq, and pint interrup ts. these registers are initialized to h'0000 at power-on reset, and manua l reset, but are not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 7.7 lists the relationship between the in terrupt sources and the ipra to iprg bits. table 7.7 interrupt request sources and ipra to iprg register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref sci reserved * iprc irq3 irq2 irq1 irq0 iprd pint0 to pint7 pint8 to pint15 irq5 irq4 ipre dmac reserved * scif adc iprf reserved * lcdc pcc0 siof iprg usbh usbf0 usbf1 afeif note: * always read as 0. only 0 should be written in. as listed in table 7.7, four sets of on-chip supporting modules or irq or pint interrupts are assigned to each register. 4-bit groups (bits 15 to 12, b its 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f is priority level 15 (the highest level). a reset initializes ipra to iprg to h'0000.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 180 of 1036 rej09b0254-0600 7.3.2 interrupt contro l register 0 (icr0) the icr0 is a register that sets the input signal detection mode of the external interrupt input pin nmi and indicates the input signal level to the nmi pin. this register is initialized to h'0000 or h'8000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 nmil ? ? ? ? ? ? nmie initial value: 0/1 * 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r note: * when nmi input is high: 1; when nmi input is low: 0. bit 15?nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15: nmil description 0 nmi input level is low 1 nmi input level is high bit 8?nmi edge select (nmie): selects whether the falling or rising edge of the interrupt request signal to the nmi is detected. bit 8: nmie description 0 interrupt request is detected on the fa lling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input bits 14 to 9 and 7 to 0?reserved: these bits are always read as 0. the write value should always be 0.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 181 of 1036 rej09b0254-0600 7.3.3 interrupt contro l register 1 (icr1) the icr1 is a 16-bit register that specifies the detection mode to external interrupt input pins, irq0 to irq5 individually: rising edge, falling edge, or low level. this register, initialized to h'4000 at power-on reset or manual reset, is not initialized in the standby mode. bit: 15 14 13 12 11 10 9 8 mai irqlvl blmsk ? irq51s irq50s irq41s irq40s initial value: 0 1 0 0 0 0 0 0 r/w: r/w r/w r/w ? r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 irq31s irq30s irq21s irq20s ir q11s irq10s irq01s irq00s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15?mask all interrupts (mai): masks nmi interrupts in standby mode when set to 1. also selects whether or not all interrupt requests are masked when a low level is being input to the nmi pin. bit 15: mai description 0 all interrupt requests are not masked while nmi pin is receiving low-level input (initial value) 1 all interrupt requests are masked while nmi pin is receiving low-level input bit 14?interrupt request level detect (irqlvl): selects whether the irq3 to irq0 pins are used as four independent interrupt pins or as 15-level interrupt pins encoded as irl3 to irl0 . bit 14: irqlvl description 0 used as four independent interrupt request pins irq3 to irq0 1 used as encoded 15-level interrupt pins as irl3 to irl0 (initial value) bit 13?bl bit mask (blmsk): specifies whether nmi interrupts are masked when the bl bit of the sr register is 1.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 182 of 1036 rej09b0254-0600 bit 13: blmsk description 0 nmi interrupts are masked when the bl bit is 1 (initial value) 1 nmi interrupts are accepted regardless of the bl bit setting bit 12?reserved: this bit is always read as 0. the write value should always be 0. bits 11 and 10?irq5 sense select (irq51s and irq50s): select whether the interrupt signal to the irq5 pin is detected at the rising edge, at the falling edge, or at low level. bit 11: irq51s bit 10: irq50s description 0 0 an interrupt request is detected at irq5 input falling edge (initial value) 1 an interrupt request is detected at irq5 input rising edge 1 0 an interrupt request is detected at irq5 input low level 1 reserved bits 9 and 8?irq4 sense select (irq41s and irq40s): select whether the interrupt signal to the irq4 pin is detected at the rising e dge, at the falling edge, or at low level. bit 9: irq41s bit 8: irq40s description 0 0 an interrupt request is detected at irq4 input falling edge (initial value) 1 an interrupt request is detected at irq4 input rising edge 1 0 an interrupt request is detected at irq4 input low level 1 reserved bits 7 and 6?irq3 sense select (irq31s and irq30s): select whether the interrupt signal to the irq3 pin is detected at the rising e dge, at the falling edge, or at low level. bit 7: irq31s bit 6: irq30s description 0 0 an interrupt request is detected at irq3 input falling edge (initial value) 1 an interrupt request is detected at irq3 input rising edge 1 0 an interrupt request is detected at irq3 input low level 1 reserved
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 183 of 1036 rej09b0254-0600 bits 5 and 4?irq2 sense select (irq21s and irq20s): select whether the interrupt signal to the irq2 pin is detected at the rising e dge, at the falling edge, or at low level. bit 5: irq21s bit 4: irq20s description 0 0 an interrupt request is detected at irq2 input falling edge (initial value) 1 an interrupt request is detected at irq2 input rising edge 1 0 an interrupt request is detected at irq2 input low level 1 reserved bits 3 and 2?irq1 sense select (irq11s and irq10s): select whether the interrupt signal to the irq1 pin is detected at the rising e dge, at the falling edge, or at low level. bit 3: irq11s bit 2: irq10s description 0 0 an interrupt request is detected at irq1 input falling edge (initial value) 1 an interrupt request is detected at irq1 input rising edge 1 0 an interrupt request is detected at irq1 input low level 1 reserved bits 1 and 0?irq0 sense select (irq01s and irq00s): select whether the interrupt signal to the irq0 pin is detected at the rising e dge, at the falling edge, or at low level. bit 1: irq01s bit 0: irq00s description 0 0 an interrupt request is detected at irq0 input falling edge (initial value) 1 an interrupt request is detected at irq0 input rising edge 1 0 an interrupt request is detected at irq0 input low level 1 reserved
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 184 of 1036 rej09b0254-0600 7.3.4 interrupt contro l register 2 (icr2) the icr2 is a 16-bit read/write register that sets the detection mode to external interrupt input pins pint0 to pint15. this register is initialized to h' 0000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 pint15s pint14s pint13s pint14s pi nt11s pint10s pint9s pint8s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?pint15 to pint0 sense select (pint15s to pint0s): select whether interrupt request signals to pint15 to pint0 are detected at low levels or high levels. bits 15 to 0: pint15s to pint0s description 0 interrupt requests are detected at low level input to the pint pins (initial value) 1 interrupt requests are detected at high level input to the pint pins
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 185 of 1036 rej09b0254-0600 7.3.5 interrupt contro l register 3 (icr3) the icr3 is a 16-bit read/write regi ster that sets the mask to pc ca rd controller. this register is initialized to h'0000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 ? pc0swim pc0irim pc0scim pc0cdim pc0rcim pc0bwim pc0bdim initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15?reserved: this bit is always read as 0. the write value should always be 0. bit 14?pc0swim: pc card controller0 swi mask. bit 14: pc0swim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bit 13?pc0irim: pc card controller0 iri mask. bits 13: pc0irim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bit 12?pc0scim: pc card controller0 sci mask. bit 12: pc0scim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 186 of 1036 rej09b0254-0600 bit 11?pc0cdim: pc card controller0 cdi mask. bit 11: pc0cdim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bit 10?pc0rcim: pc card controller0 rci mask. bit 10: pc0rcim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bit 9?pc0bwim: pc card controller0 bwi mask. bit 9: pc0bwim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bit 8?pc0bdim: pc card controller0 bdi mask. bit 8: pc0bdim description 0 interrupt requests is masked (initial value) 1 interrupt requests is not masked bits 7 to 0? reserved: these bits are always read as 0. th e write value should always be 0.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 187 of 1036 rej09b0254-0600 7.3.6 pint interrupt enable register (pinter) the pinter is a 16-bit read/write register that enables interrupt requests input to external interrupt input pins pint0 to pint15. this register is initialized to h'0000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 pint15e pint14e pint13e pint12e pi nt11e pint10e pint9e pint8e initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pint7e pint6e pint5e pint4e pi nt3e pint2e pint1e pint0e initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?pint15 to pint0 inte rrupt enable (pint15e to pint0e): enable whether the interrupt requests input to the pint15 to pint0 pins. bits 15 to 0: pint15e to pint0e description 0 disables pint input interrupt requests (initial value) 1 enables pint input interrupt requests when all or some of these pins, pint0 to pint 15 are not used as an interrupt input, a bit corresponding to a pin unused as an interrupt request should be set to 0. 7.3.7 interrupt request register 0 (irr0) the irr0 is an 8-bit register th at indicates interrupt requests from external input pins irq0 to irq5 and pint0 to pint15. this register is initia lized to h'00 at power-on reset or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 pint0r pint1r irq5r irq4r irq3r irq2r irq1r irq0r initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 188 of 1036 rej09b0254-0600 when using edge sensing for irq interrupts, do the following to clear ir0. to clear bits irq5r to irq0r to 0, read from i rr0 before writing. after confirming that the bits to be cleared to 0 are set to 1, write 0 to them. in this case write 0 only to the bits to be cleared; write 1 to the other bits. the values of the bits to which 1 is written do not change. when level sensing is used for irq interrupts, bits irq5r to irq0r indicate whether or not an interrupt request has been input. they can be set and cleared by the values input to pins irq5r to irq0r alone. bit 7?pint0 to pint7 interrupt request (pint0r): indicates whether interrupt requests are input to pint0 to pint7 pins. bit 7: pint0r description 0 interrupt requests are not input to pint0 to pint7 pins (initial value) 1 interrupt requests are input to pint0 to pint7 pins. bit 6?pint8 to pint15 interrupt request (pint1r): indicates whether interrupt requests are input to pint8 to pint15 pins. bit 6: pint1r description 0 interrupt requests are not input to pint8 to pint15 pins (initial value) 1 interrupt requests are input to pint8 to pint15 pins. bit 5?irq5 interrupt request (irq5r): indicates whether an interrupt request is input to the irq5 pin. when edge detection mode is set for irq5, an interrupt request is cleared by clearing the irq5r bit. bit 5: irq5r description 0 an interrupt request is not inpu t to irq5 pin (initial value) 1 an interrupt request is input to irq5 pin
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 189 of 1036 rej09b0254-0600 bit 4?irq4 interrupt request (irq4r): indicates whether an interrupt request is input to the irq4 pin. when edge detection mode is set for irq4, an interrupt request is cleared by clearing the irq4r bit. bit 4: irq4r description 0 an interrupt request is not inpu t to irq4 pin (initial value) 1 an interrupt request is input to irq4 pin bit 3?irq3 interrupt request (irq3r): indicates whether an interrupt request is input to the irq3 pin. when edge detection mode is set for irq3, an interrupt request is cleared by clearing the irq3r bit. bit 3: irq3r description 0 an interrupt request is not inpu t to irq3 pin (initial value) 1 an interrupt request is input to irq3 pin bit 2?irq2 interrupt request (irq2r): indicates whether an interr upt request is input to the irq2 pin. when edge detection mode is set for irq2, an interrupt request is cleared by clearing the irq2r bit. bit 2: irq2r description 0 an interrupt request is not inpu t to irq2 pin (initial value) 1 an interrupt request is input to irq2 pin bit 1?irq1 interrupt request (irq1r): indicates whether an interr upt request is input to the irq1 pin. when edge detection mode is set for irq1, an interrupt request is cleared by clearing the irq1r bit. bit 1: irq1r description 0 an interrupt request is not inpu t to irq1 pin (initial value) 1 an interrupt request is input to irq1 pin bit 0?irq0 interrupt request (irq0r): indicates whether an interr upt request is input to the irq0 pin. when edge detection mode is set for irq0, an interrupt request is cleared by clearing the irq0r bit.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 190 of 1036 rej09b0254-0600 bit 0: irq0r description 0 an interrupt request is not inpu t to irq0 pin (initial value) 1 an interrupt request is input to irq0 pin 7.3.8 interrupt request register 1 (irr1) the irr1 is an 8-bit read-only register that i ndicates whether dmac or interrupt requests are generated. this register is initialized to h'00 at power-on reset or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? dei3r dei2r dei1r dei0r initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 7 to 4?reserved : these bits are always read as 0. the write value should always be 0. bit 3?dei3 interrupt request (dei3r): indicates whether a dei3 (dmac) interrupt request is generated. bit 3: dei3r description 0 a dei3 interrupt request is not generated (initial value) 1 a dei3 interrupt request is generated bit 2?dei2 interrupt request (dei2r): indicates whether a dei2 (dmac) interrupt request is generated. bit 2: dei2r description 0 a dei2 interrupt request is not generated (initial value) 1 a dei2 interrupt request is generated bit 1?dei1 interrupt request (dei1r): indicates whether a dei1 (dmac) interrupt request is generated. bit 1: dei1r description 0 a dei1 interrupt request is not generated (initial value) 1 a dei1 interrupt request is generated
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 191 of 1036 rej09b0254-0600 bit 0?dei0 interrupt request (dei0r): indicates whether a dei0 (dmac) interrupt request is generated. bit 0: dei0r description 0 a dei0 interrupt request is not generated (initial value) 1 a dei0 interrupt request is generated 7.3.9 interrupt request register 2 (irr2) the irr2 is an 8-bit read-only register that i ndicates whether a/d converter, or scif interrupt requests are generated. this register is initialized to h'00 at power-on reset or manual reset, but is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? adir txi2r bri2r rxi2r eri2r initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 7 to 5?reserved: these bits are always read as 0. the write value should always be 0. bit 4?adi interrupt request (adir): indicates whether an adi (adc) interrupt request is generated. bit 4: adir description 0 an adi interrupt request is not generated (initial value) 1 an adi interrupt request is generated bit 3?txi2 interrupt request (txi2r): indicates whether a txi2 (s cif) interrupt request is generated. bit 3: txi2r description 0 a txi2 interrupt request is not generated (initial value) 1 a txi2 interrupt request is generated
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 192 of 1036 rej09b0254-0600 bit 2?bri2 interrupt request (bri2r): indicates whether a bri2 (s cif) interrupt request is generated. bit 2: bri2r description 0 a bri2 interrupt request is not generated (initial value) 1 a bri2 interrupt request is generated bit 1?rxi2 interrupt request (rxi2r): indicates whether an rxi2 (s cif) interrupt request is generated. bit 1: rxi2r description 0 an rxi2 interrupt request is not generated (initial value) 1 an rxi2 interrupt request is generated bit 0?eri2 interrupt request (eri2r): indicates whether an eri2 (s cif) interrupt request is generated. bit 0: eri2r description 0 an eri2 interrupt request is not generated (initial value) 1 an eri2 interrupt request is generated 7.3.10 interrupt requ est register 3 (irr3) the irr3 is a 16-bit read-only re gister that indicates whether pc card controller, usb controller or lcdc interrupt requests are generated. this re gister is initialized to h' 0000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 lcdcir pc0swir pc0irir pc0scir pc0cdir pc0rcir pc0bwir pc0bdir initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 usbhir usbf0ir usbf1ir afeifir ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 193 of 1036 rej09b0254-0600 bit 15?lcdci interrupt request (lcdcir): indicates whether a lcdci (lcdc) interrupt request is generated. bit 15: lcdcir description 0 a lcdci interrupt request is not generated (initial value) 1 a lcdci interrupt request is generated bit 14?pc0swi interrupt request (pc0swir): indicates whether a pc0swi (pcc0) interrupt request is generated. bit 14: pc0swir description 0 a pc0swi interrupt request is not generated (initial value) 1 a pc0swi interrupt request is generated bit 13?pc0iri interrupt request (pc0irir): indicates whether a pc0ireq (pcc0) interrupt request is generated. bit 13: pc0irir description 0 a pc0iri interrupt request is not generated (initial value) 1 a pc0iri interrupt request is generated bit 12?pc0sci interrupt request (pc0scir): indicates whether a pc0sci (pcc0) interrupt request is generated. bit 12: pc0scir description 0 a pc0sci interrupt request is not generated (initial value) 1 a pc0sci interrupt request is generated bit 11?pc0cdi interrupt request (pc0cdir): indicates whether a pc0cdi (pcc0) interrupt request is generated. bit 11: pc0cdir description 0 a pc0cdi interrupt request is not generated (initial value) 1 a pc0cdi interrupt request is generated
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 194 of 1036 rej09b0254-0600 bit 10?pc0rci interrupt request (pc0rcir): indicates whether a pc0rci (pcc0) interrupt request is generated. bit 10: pc0rcir description 0 a pc0rci interrupt request is not generated (initial value) 1 a pc0rci interrupt request is generated bit 9?pc0bwi interrupt request (pc0bwir): indicates whether a pc0bwi (pcc0) interrupt request is generated. bit 9: pc0bwir description 0 a pc0bwi interrupt request is not generated (initial value) 1 a pc0bwi interrupt request is generated bit 8?pc0bdi interrupt request (pc0bdir): indicates whether a pc0bdi (pcc0) interrupt request is generated. bit 8: pc0bdir description 0 a pc0bdi interrupt request is not generated (initial value) 1 a pc0bdi interrupt request is generated bit 7?usbhi interrupt request (usbhir): indicates whether a usbhi (usb host) interrupt request is generated. bit 7: usbhir description 0 a usbhi interrupt request is not generated (initial value) 1 a usbhi interrupt request is generated bit 6?usbf0i interrupt request (usbf0ir): indicates whether a usbf0i (usb function) interrupt request is generated. bit 6: usbf0ir description 0 a usbf0i interrupt request is not generated (initial value) 1 a usbf0i interrupt request is generated
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 195 of 1036 rej09b0254-0600 bit 5?usbf1i interrupt request (usbf1ir): indicates whether a usbf1i (usb function) interrupt request is generated. bit 5: usbf1ir description 0 a usbf1i interrupt request is not generated (initial value) 1 a usbf1i interrupt request is generated bit 4?afeifi interrupt request (afeifir): indicates whether a afeifi (afe i/f) interrupt request is generated. bit 4: afeifir description 0 an afe i/f interrupt request is not generated (initial value) 1 an afe i/f interrupt request is generated bits 3 to 0?reserved: these bits are always read as 0. 7.3.11 interrupt requ est register 4 (irr4) the irr4 is a 16-bit read-only register that indicates whether siof interrupt requests are generated. this register is initialized to h'0000 at power-on reset or manual reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? eri txi rxi cci initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 15 to 4?reserved: these bits are always read as 0. the write value should always be 0.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 196 of 1036 rej09b0254-0600 bit 3?eri interrupt request (eri): indicates whether a eri (siof) interrupt request is generated. bit 3: eri description 0 eri interrupt request is not generated (initial value) 1 eri interrupt request is generated bit 2?txi interrupt request (txi): indicates whether a txi (siof) interrupt request is generated. bit 2:txi description 0 txi interrupt request is not generated (initial value) 1 txi interrupt request is generated bit 1?rxi interrupt request (rxi): indicates whether a rxi (siof) interrupt request is generated. bit 1: rxi description 0 rxi interrupt request is not generated (initial value) 1 rxi interrupt request is generated bit 0?cci interrupt request (cci): indicates whether a cci (cci) interrupt request is generated. b it 0: cci description 0 cci interrupt request is not generated (initial value) 1 cci interrupt request is generated
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 197 of 1036 rej09b0254-0600 7.4 intc operation 7.4.1 interrupt sequence the sequence of interrupt operations is explained below. figure 7.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest prio rity interrupt from the interrupt requests sent, following the priority levels set in interrupt pr iority registers a to g (ipra to iprg). lower priority interrupts are held pending. if two of thes e interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting unit (as indicated in tables 7.4 and 7.5) is selected. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3 to i0) in the status regist er (sr) of the cpu. if the request priority level is higher than the level in bits i3 to i0, th e interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. detection timing: the intc operates, and notifies the cpu of interrupt requests, in synchronization with the peripheral clock (p ). the cpu receives an interrupt at a break in instructions. 5. the interrupt source code is set in the in terrupt event registers (intevt and intevt2). 6. the status register (sr) and program counte r (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). this jump is not a delayed branch. the interrupt handler may branch with the intevt and intevt2 register value as its offset in order to identify the interrupt source. this enables it to branch to the processing routine for the individual interrupt source. notes: 1. the interrupt mask bits (i3 to i0) in the status register (sr) are not changed by acceptance of an interr upt in the SH7727. 2. the interrupt source flag should be cleared in the interrupt handler. to ensure that an interrupt request that should have been clear ed is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 7.8 (time for priority decision and sr mask bit comparison) before clearing the bl bit or executing an rte instruction.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 198 of 1036 rej09b0254-0600 i3 ? i0: interrupt mask bits in status register (sr) program execution state icr1.mai = 1? interrupt generated? nmi = low? sr.bl= 0 or sleep mode? yes yes yes yes yes yes yes yes yes yes yes yes yes no no no no no no no no no no no no no icr1.blmsk = 1? nmi? nmi? level 15 interrupt? set interrupt cause in intevt, intevt2 save sr to ssr; save pc to spc set bl/md/rb bits in sr to 1 branch to exception handler i3 ? i0 level 14 or lower? level 14 interrupt? i3 ? i0 level 13 or lower? level 1 interrupt? i3 ? i0 level 0? figure 7.3 interrupt operation flowchart
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 199 of 1036 rej09b0254-0600 7.4.2 multiple interrupts when processing multiple interrupts, an interrupt handler should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in intevt and intevt2. the code in intevt and intevt2 can be used as a branch-offset for branching to the specific handler. 2. clear the cause of the inte rrupt in each specific handler. 3. save ssr and spc to the memory. 4. clear the bl bit in sr, and set the accepted in terrupt level in the inte rrupt mask bits in sr. 5. handle the interrupt. 6. execute the rte instruction. when these procedures are followed in order, an interrupt of high er priority than the one being handled can be accepted after clearing bl in step 4. 7.5 interrupt response time the time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exceptio n handler is started (the interrupt response time) is shown in table 7.8. figure 7.4 shows an example of pipeline operation when an irl interrupt is accepted. when sr.bl is 1, interrupt excepti on handling is masked, and is kept waiting until completion of an instructio n that clears bl to 0.
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 200 of 1036 rej09b0254-0600 table 7.8 interrupt response time number of states item nmi irq pint peripheral modules notes 0.5 icyc + 0.5 bcyc + 0.5 pcyc 0.5 icyc + 1 bcyc + 4.5 pcyc * 4 0.5 icyc + 3.5 pcyc 0.5 icyc + 1.5 pcyc * 5 time for priority decision and sr mask bit comparison 0.5 icyc + 3 pcyc * 6 wait time until end of sequence being executed by cpu x ( 0) icyc x ( 0) icyc x ( 0) icyc x ( 0) icyc interrupt exception handling is kept waiting until the executing instruction ends. if the number of instruction execution states is s * 1 , the maximum wait time is: x = s ? 1. however, if bl is set to 1 by instruction execution or by an exception, interrupt exception handling is deferred until completion of an instruction that clears bl to 0. if the following instruction masks interrupt exception handling, the processing may be further deferred. time from interrupt exception handling (save of sr and pc) until fetch of first instruction of exception handler is started 5 icyc 5 icyc 5 icyc 5 icyc
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 201 of 1036 rej09b0254-0600 number of states item nmi irq pint peripheral modules notes response time total (5.5 + x) icyc + 0.5 bcyc + 0.5 pcyc (5.5 + x) icyc + 1 bcyc + 4.5 pcyc * 4 (5.5 + x) icyc + 3.5 pcyc * 5 (5.5 + x) icyc + 1.5 pcyc * 5 (5.5 + x) icyc + 3 pcyc * 6 minimum case * 2 7.5 16.5 12.5 8.5 * 5 /11.5 * 6 at 60-mhz (ckio = 30) operation: 0.13?0.28 s maximum case * 3 8.5 + s 26.5 + s 18.5 + s 10.5 + s * 5 16.5 + s * 6 at 60-mhz (ckio = 15) operation: 0.26?0.56 s (in case of operand cache-hit) at 60-mhz (ckio = 15) operation: 0.29?0.59 s (when external memory access is performed with wait = 0) icyc: duration of one cycle of internal clock supplied to cpu. bcyc: duration of one ckio cycle. pcyc: duration of one cycle of peripheral clock supplied to peripheral modules. notes: 1. s also includes the memory access wait time. the processing requiring the maximum exec ution time is ldc.l @rm+, sr. when the memory access is a cache-hit, this requires seven instruction execution cycles. when the external access is performed, the corre sponding number of cycles must be added. there are also instructions that perform two external memory accesse s; if the external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. the internal clock: ckio: per ipheral clock ratio is 2:1:1. 3. the internal clock: ckio: per ipheral clock ratio is 4:1:1. 4. irq mode 5. modules: tmu, rtc, sci, wdt, refc 6. modules: dmac, adc, scif, lcdc, p cc, usb host, usb function, afe interface
section 7 interrupt controller (intc) rev.6.00 mar. 27, 2009 page 202 of 1036 rej09b0254-0600 interrupt acceptance irl 0.5 icyc + 0.5 bcyc + 2 pcyc instruction (instruction replaced by interrupt exception processing) if id ex ex ex ex if if id ex 5 icyc start of interrupt processing if: instruction fetch: instruction is fetched from memory in which program is stored. id: instruction decode: fetched instruction is decoded. ex: instruction execution: data operation and address calculation are performed in accordance with result of decoding. overrun fetch first instruction of interrupt handler figure 7.4 example of pipeline operat ions when irl interrupt is accepted
section 8 user break controller rev.6.00 mar. 27, 2009 page 203 of 1036 rej09b0254-0600 section 8 user break controller 8.1 overview the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data si ze, data contents, address value, and timing in the case of instruction fetch. 8.1.1 features the ubc has the following features: ? the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and, then channel b match with logical and, but not in the same bus cycle). ? address (compares 40 bits comprised of a 32-bit logical address prefixed with an asid address comparison bits are maskable in 32-bit units, user can easily program it to mask addresses at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc. the 8-bit asid checking is from mmu control to indicate hit or not hit.) one of four address buses (cpu addres s bus (lab), cache address bus (iab), x-memory address bus (xab) and y-memory address bus (yab)) can be selected. ? data (only on channel b, 32-bit maskable) one of the four data buses (cpu data bus (ldb), cache data bus (idb), x-memory data bus (xdb) and y-memory data bus (ydb)) can be selected. ? bus master: cpu cycle or dmac cycle ? bus cycle: instruction fetch or data access ? read/write ? operand size: byte, word, or longword ? user break is generated upon satisfying br eak conditions. a user-designed user-break condition exception processing routine can be run. ? in an instruction fetch cycle, it can be selected that a break is se t before or after an instruction is executed.
section 8 user break controller rev.6.00 mar. 27, 2009 page 204 of 1036 rej09b0254-0600 ? maximum repeat times for the break condition: 2 12 ? 1 times. (it is only for channel b) ? eight pairs of branch source/destination buffers. 8.1.2 block diagram figure 8.1 is a block diagram of the ubc. bbra bara bamra basra asid comparator cpu state signals xab/yab iab lab mdb access comparator address comparator channel a asid comparator access comparator address comparator data comparator pc trace control channel b bbrb betr barb bamrb basrb bdrb bdmrb brsr brdr brcr user break request ubc location ccn location ldb/idb/ xdb/ydb legend bbra: break bus cycle register a bara: break address register a bamra: break address mask register a basra: break asid register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b basrb: break asid register b bdrb: break data register b bdmrb: break data mask register b betr: break execution times registe r brsr: branch source register brdr: branch destination register brcr: break control register a ccess control figure 8.1 block diagram of user break controller
section 8 user break controller rev.6.00 mar. 27, 2009 page 205 of 1036 rej09b0254-0600 8.1.3 register configuration table 8.1 register configuration name abbr. r/w initial value * 1 address access size location break address register a bara r/w h'00000000 h'ffffffb0 32 ubc break address mask register a bamra r/w h'00000000 h'ffffffb4 32 ubc break bus cycle register a bbra r/w h'0000 h'ffffffb8 16 ubc break address register b barb r/w h'00000000 h'ffffffa0 32 ubc break address mask register b bamrb r/w h'00000000 h'ffffffa4 32 ubc break bus cycle register b bbrb r/w h'0000 h'ffffffa8 16 ubc break data register b bdrb r/w h'00000000 h'ffffff90 32 ubc break data mask register b bdmrb r/w h'00000000 h'ffffff94 32 ubc break control register b rcr r/w h'00000000 h'ffffff98 32 ubc execution count break register betr r/w h'0000 h'ffffff9c 16 ubc branch source register brsr r undefined * 2 h'ffffffac 32 ubc branch destination register brdr r undefined * 2 h'ffffffbc 32 ubc break asid register a basra r/w undefined h'ffffffe4 8 ccn break asid register b basrb r/w undefined h'ffffffe8 8 ccn notes: 1. initialized by power-on reset. values held in standby state and undefined by manual resets. 2. bit 31 of brsr and brdr (valid flag) is initialized by power-on resets. but other bits are not initialized.
section 8 user break controller rev.6.00 mar. 27, 2009 page 206 of 1036 rej09b0254-0600 8.2 register descriptions 8.2.1 break address register a (bara) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 baa 31 baa 30 baa 29 baa 28 baa 27 baa 26 baa 25 baa 24 baa 23 baa 22 baa 21 baa 20 baa 19 baa 18 baa 17 baa 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 baa 15 baa 14 baa 13 baa 12 baa 11 baa 10 baa 9 baa 8 baa 7 baa 6 baa 5 baa 4 baa 3 baa 2 baa 1 baa 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bara is a 32-bit read/wr ite register. bara specifies the address used as a break condition in channel a. a power-on reset initializes bara to h'00000000. bits 31 to 0?break address a3 1 to a0 (baa31 to baa0): stores the address on the lab or iab specifying break conditions of channel a. 8.2.2 break address mask register a (bamra) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bama 31 bama 30 bama 29 bama 28 bama 27 bama 26 bama 25 bama 24 bama 23 bama 22 bama 21 bama 20 bama 19 bama 18 bama 17 bama 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bama 15 bama 14 bama 13 bama 12 bama 11 bama 10 bama 9 bama 8 bama 7 bama 6 bama 5 bama 4 bama 3 bama 2 bama 1 bama 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bamra is a 32-bit read/write register. bamra specifies bits masked in the break address specified by bara. a power-on reset initializes bamra to h'00000000.
section 8 user break controller rev.6.00 mar. 27, 2009 page 207 of 1036 rej09b0254-0600 bits 31 to 0?break address mask register a31 to a0 (bama31 to bama0): specifies bits masked in the channel a break address bits specified by bara (baa31 to baa0). bits 31 to 0: baman description 0 break address bit baan of channel a is included in the break condition (initial value) 1 break address bit baan of channel a is masked and is not included in the break condition n = 31 to 0 8.2.3 break bus cycl e register a (bbra) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w break bus cycle register a (bbra) is a 16-bit read /write register, which specifies (1) cpu cycle or dmac cycle, (2) instruction fetch or data acce ss, (3) read or write, an d (4) operand size in the break conditions of channel a. a powe r-on reset initializes bbra to h'0000. bits 15 to 8?reserved: these bits are always read as 0. th e write value should always be 0. bits 7 and 6?cpu cycle/dmac cycle select a (cda1, cda0): selects the cpu cycle or dmac cycle as the bus cycle of the channel a break condition. bit 7: cda1 bit 6: cda0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle note: * don?t care
section 8 user break controller rev.6.00 mar. 27, 2009 page 208 of 1036 rej09b0254-0600 bits 5 and 4?instruction fetch/data access select a (ida1, ida0): selects the instruction fetch cycle or data access cycle as the bu s cycle of the channel a break condition. bit 5: ida1 bit 4: ida0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the inst ruction fetch cycle or data access cycle bits 3 and 2?read/write select a (rwa1, rwa0): selects the read cycle or write cycle as the bus cycle of the channel a break condition. bit 3: rwa1 bit 2: rwa0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0?operand size select a (sza1, sza0): selects the operand size of the bus cycle for the channel a break condition. bit 1: sza1 bit 0: sza0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
section 8 user break controller rev.6.00 mar. 27, 2009 page 209 of 1036 rej09b0254-0600 8.2.4 break address register b (barb) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bab 31 bab 30 bab 29 bab 28 bab 27 bab 26 bab 25 bab 24 bab 23 bab 22 bab 21 bab 20 bab 19 bab 18 bab 17 bab 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bab 15 bab 14 bab 13 bab 12 bab 11 bab 10 bab 9 bab 8 bab 7 bab 6 bab 5 bab 4 bab 3 bab 2 bab 1 bab 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w barb is a 32-bit read/write register. barb specifi es the address used as a break condition in channel b. control bits xye and xys in the bbrb selects an address bus for break condition b. if the xye is 0, then barb specifies the break addr ess on logic or internal bus, lab or iab. if the xye is 1, then the bab31 to 16 specifies th e break address on xab (bits 15 to 1) and the bab15 to 0 specifies the break address on yab (bits 15 to 1). however, you have to choose one of two address buses for the break. a power-on reset initializes barb to h'00000000. bab31 to 16 bab15 to 0 xye = 0 l(i) ab31 to 16 l(i) ab15 to 0 xye = 1 xab15 to 1 (xys = 0) yab15 to 1 (xys = 1)
section 8 user break controller rev.6.00 mar. 27, 2009 page 210 of 1036 rej09b0254-0600 8.2.5 break address ma sk register b (bamrb) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bamb 31 bamb 30 bamb 29 bamb 28 bamb 27 bamb 26 bamb 25 bamb 24 bamb 23 bamb 22 bamb 21 bamb 20 bamb 19 bamb 18 bamb 17 bamb 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bamb 15 bamb 14 bamb 13 bamb 12 bamb 11 bamb 10 bamb 9 bamb 8 bamb 7 bamb 6 bamb 5 bamb 4 bamb 3 bamb 2 bamb 1 bamb 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bamrb is a 32-bit read/write register. bamrb specifies bits masked in the break address specified by barb. a power-on reset initializes bamrb to h'00000000. bamb31 to 16 bamb15 to 0 xye = 0 mask l(i) ab31 to 16 mask l(i) ab15 to 0 xye = 1 mask xab15 to 1 (xys = 0) mask yab15 to 1 (xys = 1) bits 31 to 0: bambn description 0 break address babn of channel b is includ ed in the break condit ion (initial value) 1 break address babn of channel b is masked and is not included in the break condition n = 31 to 0
section 8 user break controller rev.6.00 mar. 27, 2009 page 211 of 1036 rej09b0254-0600 8.2.6 break data register b (bdrb) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bdb 31 bdb 30 bdb 29 bdb 28 bdb 27 bdb 26 bdb 25 bdb 24 bdb 23 bdb 22 bdb 21 bdb 20 bdb 19 bdb 18 bdb 17 bdb 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bdb 15 bdb 14 bdb 13 bdb 12 bdb 11 bdb 10 bdb 9 bdb 8 bdb 7 bdb 6 bdb 5 bdb 4 bdb 3 bdb 2 bdb 1 bdb 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bdrb is a 32-bit read/write regi ster. the control bits xye and xys in bbrb select a data bus for break condition b. if the xye is 0, then bdrb specifies the break data on ldb or idb. if the xye is 1, then bdb 31 to 16 specifies the break data on xdb (bits 15 to 0) and bdb 15 to 0 specifies the break data on ydb (bits 15 to 0). however, you have to choose one of two data buses for the break. a power-on reset initializes bdrb to h'00000000. bdb31 to 16 bdb15 to 0 xye = 0 l(i) db31 to 16 l(i) db15 to 0 xye = 1 xdb15 to 0 (xys = 0) ydb15 to 0 (xys = 1)
section 8 user break controller rev.6.00 mar. 27, 2009 page 212 of 1036 rej09b0254-0600 8.2.7 break data mask register b (bdmrb) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bdmb 31 bdmb 30 bdmb 29 bdmb 28 bdmb 27 bdmb 26 bdmb 25 bdmb 24 bdmb 23 bdmb 22 bdmb 21 bdmb 20 bdmb 19 bdmb 18 bdmb 17 bdmb 16 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bdmb 15 bdmb 14 bdmb 13 bdmb 12 bdmb 11 bdmb 10 bdmb 9 bdmb 8 bdmb 7 bdmb 6 bdmb 5 bdmb 4 bdmb 3 bdmb 2 bdmb 1 bdmb 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bdmrb is a 32-bit read/write register. bdmrb speci fies bits masked in the break data specified by bdrb. a power-on reset initializes bdmrb to h'00000000. bdmb31 to 16 bdmb15 to 0 xye = 0 mask l(i) db31 to 16 mask l(i) db15 to 0 xye = 1 mask xdb15 to 0 (xys = 0) mask ydb15 to 0 (xys = 1) bits 31 to 0: bdmbn description 0 break data bdbn of channel b is included in the break condition (initial value) 1 break data bdbn of channel b is ma sked and is not included in the break condition n = 31 to 0 notes: 1. specify an operand size when including t he value of the data bus in the break condition. 2. when a byte size is selected as a break condition, the same break data (byte size) must be set both in bits 15 to 8 and in bits 7 to 0 in bdrb.
section 8 user break controller rev.6.00 mar. 27, 2009 page 213 of 1036 rej09b0254-0600 8.2.8 break bus cycle register b (bbrb) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? xye xys cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w break bus cycle register b (bbrb) is a 16-bit read /write register, which specifies (1) logic or internal bus (l or i bus), x bus, of y bus, (2) cpu cycle or dmac cycle, (3) instruction fetch or data access, (4) read/write, and (5) operand size in the break conditions of channel b. a power-on reset initializes bbrb to h'0000. bits 15 to 10?reserved: these bits are always read as 0. the write value should always be 0. bit 9?x/y memory bus enable (xye): selects the logic bus or intern al bus (l bus or i bus) or the x/y memory bus as the bus of the channel b break condition. bit 9: xye description 0 select internal bus (i bus) for the channel b break condition 1 select x/y memory bus (x/y bus) for the channel b break condition bits 8?x or y memory bus select (xys): selects the x bus or the y bus as the bus of the channel b break condition. bit 8: xys description 0 select the x bus for the channel b break condition 1 select the y bus for the channel b break condition bits 7 and 6?cpu cycle/dmac cy cle select b (cdb1 and cdb0): select the cpu cycle or dmac cycle as the bus cycle of the channel b break condition. bit 7: cdb1 bit 6: cdb0 description 0 0 condition comparison is not performed (initial value) * 1 the break condition is the cpu cycle 1 0 the break condition is the dmac cycle note: * don?t care.
section 8 user break controller rev.6.00 mar. 27, 2009 page 214 of 1036 rej09b0254-0600 bits 5 and 4?instruction fetch/data access select b (idb1 and idb0): select the instruction fetch cycle or data access cycle as the bu s cycle of the channel b break condition. bit 5: idb1 bit 4: idb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the instruction fetch cycle 1 0 the break condition is the data access cycle 1 the break condition is the inst ruction fetch cycle or data access cycle bits 3 and 2?read/write select b (rwb1 and rwb0): select the read cycle or write cycle as the bus cycle of the ch annel b break condition. bit 3: rwb1 bit 2: rwb0 description 0 0 condition comparison is not performed (initial value) 1 the break condition is the read cycle 1 0 the break condition is the write cycle 1 the break condition is the read cycle or write cycle bits 1 and 0?operand size select b (szb1 and szb0): select the operand size of the bus cycle for the channel b break condition. bit 1: szb1 bit 0: szb0 description 0 0 the break condition does not include operand size (initial value) 1 the break condition is byte access 1 0 the break condition is word access 1 the break condition is longword access
section 8 user break controller rev.6.00 mar. 27, 2009 page 215 of 1036 rej09b0254-0600 8.2.9 break control register (brcr) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? ? ? bas ma bas mb ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r/w r/w r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scm fca scm fcb scm fda scm fdb pcte pcba ? ? dbeb pcbb ? ? seq ? ? etbe initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r r/w r/w r r r/w r r r/w brcr sets the following conditions: 1. channels a and b are used in two independ ent channels condition or under the sequential condition. 2. a break is set before or after instruction execution. 3. a break is set by the number of execution times. 4. determine whether to include data bus on channel b in comparison conditions. 5. enable pc trace. 6. enable the asid check. the break control register (brcr) is a 32-bit read /write register that has break conditions match flags and bits for setting a variety of break conditions. a power-on reset initializes brcr to h'00000000. bits 31 to 22?reserved: these bits are always read as 0. the write value should always be 0. bit 21?break asid mask a (basma): specifies whether the bits of the channel a break asid7 to asid0 (basa7 to basa0) set in basra are masked or not. bit 21: basma description 0 all basra bits are included in break condition, and asid is checked (initial value) 1 no basra bits are included in break condition, and asid is not checked
section 8 user break controller rev.6.00 mar. 27, 2009 page 216 of 1036 rej09b0254-0600 bit 20?break asid mask b (basmb): specifies whether the bits of channel b break asid7 to asid0 (basb7 to basb0) set in basrb are masked or not. bit 20: basmb description 0 all basrb bits are included in break condition, and asid is checked (initial value) 1 no basrb bits are included in break condition, and asid is not checked bits 19 to 16?reserved: these bits are always read as 0. the write value should always be 0. bit 15?cpu condition match flag a (scmfca): when the cpu bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 15: scmfca description 0 the cpu cycle condition for channel a does not match (initial value) 1 the cpu cycle condition for channel a matches bit 14?cpu condition match flag b (scmfcb): when the cpu bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 14: scmfcb description 0 the cpu cycle condition for channel b does not match (initial value) 1 the cpu cycle condition for channel b matches bit 13?dmac condition match flag a (scmfda): when the on-chip dmac bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 13: scmfda description 0 the dmac cycle condition for channel a does not match (initial value) 1 the dmac cycle condition for channel a matches
section 8 user break controller rev.6.00 mar. 27, 2009 page 217 of 1036 rej09b0254-0600 bit 12?dmac condition match flag b (scmfdb): when the on-chip dmac bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. bit 12: scmfdb description 0 the dmac cycle condition for channel b does not match (initial value) 1 the dmac cycle condition for channel b matches bit 11?pc trace enable (pcte): enables pc trace. bit 11: pcte description 0 disables pc trace (initial value) 1 enables pc trace bit 10?pc break select a (pcba): selects the break timing of the instruction fetch cycle for channel a as before or af ter instruction execution. bit 10: pcba description 0 pc break of channel a is set before instruction execution (initial value) 1 pc break of channel a is set after instruction execution bits 9 and 8?reserved: these bits are always read as 0. th e write value should always be 0. bit 7?data break enable b (dbeb): selects whether or not the data bus condition is included in the break condition of channel b. bit 7: dbeb description 0 no data bus condition is included in the condition of channel b (initial value) 1 the data bus condition is included in the condition of channel b bit 6?pc break select b (pcbb): selects the break timing of the instruction fetch cycle for channel b as before or af ter instruction execution. bit 6: pcbb description 0 pc break of channel b is set before instruction execution (initial value) 1 pc break of channel b is set after instruction execution
section 8 user break controller rev.6.00 mar. 27, 2009 page 218 of 1036 rej09b0254-0600 bits 5 and 4?reserved: these bits are always read as 0. th e write value should always be 0. bit 3?sequence condition select (seq): selects two conditions of channels a and b as independent or sequential. bit 3: seq description 0 channels a and b are compared under the independent condition (initial value) 1 channels a and b are compared under the sequential condition bits 2 and 1?reserved: these bits are always read as 0. th e write value should always be 0. bit 0?the number of execution times break enable (etbe): enable the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the betr register. bit 0: etbe description 0 the execution-times break condition is disabled on channel b (initial value) 1 the execution-times break condition is enabled on channel b 8.2.10 execution times break register (betr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w when the execution-times break condition of channe l b is enabled, this register specifies the number of execution times to make the break. the maximum number is 2 12 ? 1 times. a power-on reset initializes betr to h'0000. when a break condition is satisfied, it decreases the betr. a break is issued when the break condition is satisfi ed after the betr becomes h'0001. bits 15 to 12 are always read as 0 and 0 should always be written in these bits.
section 8 user break controller rev.6.00 mar. 27, 2009 page 219 of 1036 rej09b0254-0600 8.2.11 branch source register (brsr) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 svf pid2 pid1 pid0 bsa 27 bsa 26 bsa 25 bsa 24 bsa 23 bsa 22 bsa 21 bsa 20 bsa 19 bsa 18 bsa 17 bsa 16 initial value: 0 * * * * * * * * * * * * * * * r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bsa 15 bsa 14 bsa 13 bsa 12 bsa 11 bsa 10 bsa 9 bsa 8 bsa 7 bsa 6 bsa 5 bsa 4 bsa 3 bsa 2 bsa 1 bsa 0 initial value: * * * * * * * * * * * * * * * * r/w: r r r r r r r r r r r r r r r r note: * undefined brsr is a 32-bit read register. brsr stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. brsr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brsr is read and also initialized by power-on resets or manual resets. other bits are not initialized by reset. eight brsr registers have que ue structure and a stored register is shifted every branch. bit 31?brsr valid flag (svf): indicates whether the address and the pointer by which the branch source address can be calculated. when a bran ch source address is fetched, this flag is set to 1. this flag is clear ed to 0 in reading brsr. bit 31: svf description 0 the value of brsr register is invalid 1 the value of brsr register is valid bits 30 to 28?instruction decode pointer (pid2 to pid0): pid is a 3-bit binary pointer (0 to 7). these bits indicate the instruction buffer number which stores the last executed instruction before branch. bits 30 to 28: pid description even pid indicates the instruction buffer number. odd pid+2 indicates the instruction buffer number
section 8 user break controller rev.6.00 mar. 27, 2009 page 220 of 1036 rej09b0254-0600 bits 27 to 0?branch source address (bsa27 to bsa0): these bits store the last fetched address before branch. 8.2.12 branch destination register (brdr) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dvf ? ? ? bda 27 bda 26 bda 25 bda 24 bda 23 bda 22 bda 21 bda 20 bda 19 bda 18 bda 17 bda 16 initial value: 0 * * * * * * * * * * * * * * * r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bda 15 bda 14 bda 13 bda 12 bda 11 bda 10 bda 9 bda 8 bda 7 bda 6 bda 5 bda 4 bda 3 bda 2 bda 1 bda 0 initial value: * * * * * * * * * * * * * * * * r/w: r r r r r r r r r r r r r r r r note: * undefined brdr is a 32-bit read register. brdr stores the branch destination fetch address. brdr has the flag bit that is set to 1 when branch occurs. this flag bit is cleared to 0, when brdr is read and also initialized by power-on resets or manual resets. other bits are not initialized by resets. eight brdr registers have queue structure and a stored register is shifted every branch. bit 31?brdr valid flag (dvf): indicates whether a branch de stination address is stored. when a branch destination address is fetched, this flag is set to 1. this flag is cleared to 0 in reading brdr. bit 31: dvf description 0 the value of brdr register is invalid 1 the value of brdr register is valid bits 30 to 28?reserved: these bits are always read as 0. the write value should always be 0. bits 27 to 0?branch destination address (bda27 to bda0): these bits store the first fetched address after branch.
section 8 user break controller rev.6.00 mar. 27, 2009 page 221 of 1036 rej09b0254-0600 8.2.13 break asid register a (basra) bit: 7 6 5 4 3 2 1 0 basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined break asid register a (basra) is an 8-bit read/wr ite register that specifies the asid that serves as the break condition for channel a. it is not initialized by resets. it is located in ccn. bits 7 to 0?break asid a7 to 0 (basa7 to basa0): these bits store the asid (bits 7 to 0) that is the channel a break condition. 8.2.14 break asid register b (basrb) bit: 7 6 5 4 3 2 1 0 basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 initial value: * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * undefined break asid register b (basrb) is an 8-bit read/write register that specifies the asid that serves as the break condition for channel b. it is not initialized by resets. it is located in ccn. bits 7 to 0: break asid a7 to 0 (basb7 to basb0): these bits store the asid (bits 7 to 0) that is the channel b break condition.
section 8 user break controller rev.6.00 mar. 27, 2009 page 222 of 1036 rej09b0254-0600 8.3 operation description 8.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses and the corresponding as ids are loaded in the break address registers (bara and barb) and break asid registers (basra and basrb in ccn). the masked addresses are set in the break address mask registers (bamra and bamrb). the break data is set in the break data register (bdrb). the mask ed data is set in the break data mask register (bdmrb). the breaking bus conditions are set in the break bus cycle registers (bbra and bbrb). three groups of the bbra and bbrb (cpu cycle/dmac cycle select, instruction fetch/data access select, and read/write select) are each set. no user break will be generated if even one of these groups is set with 00. the re spective conditions are set in the bits of the brcr. 2. when the break conditions are satisfied, the u bc sends a user break request to the interrupt controller. the break type will be sent to cpu indicating the instruction fetch, pre/post instruction break, data access break, or on -chip i/o access/ldtlb break. when conditions match up, the cpu condition match flags (scmfca and scmfcb) and dmac condition match flags (scmfda and scmfdb) for the respective channels are set. 3. the appropriate condition match flags (scmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. there is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one br eak request to the cpu, but these two break channel match flags could both be set. 8.3.2 break on inst ruction fetch cycle 1. when cpu/instruction fetch/read/word or longword is set in the break bus cycle registers (bbra/bbrb), the break condition becomes the cpu instruction fetch cycle. whether it then breaks before or after the execution of the instruction can then be selected with the pcba/pcbb bits of the break control regist er (brcr) for the appropriate channel. 2. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delay branch instruction, the break is generated prior to execution of the instruction that then first accepts the break. meanwhile, the break set for pre-instruction- break on delay slot instruction and post- instruction-break on sleep instruction are also prohibited.
section 8 user break controller rev.6.00 mar. 27, 2009 page 223 of 1036 rej09b0254-0600 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delay bran ch instruction, the break is generated at the instruction that then first accepts the break. 4. when an instruction fetch cycle is set for channel b, break data register b (bdrb) is ignored. there is thus no need to set break data fo r the break of the inst ruction fetch cycle. 8.3.3 break by data access cycle 1. the memory cycles in which cpu data access breaks occur are from instructions. 2. the relationship between the data access cy cle address and the co mparison condition for operand size are listed in table 8.2: table 8.2 data access cycle addresses an d operand size comparison conditions access size address compared longword compares break address register bits 31 to 2 to address bus bits 31 to 2 word compares break address register bits 31 to 1 to address bus bits 31 to 1 byte compares break address register bits 31 to 0 to address bus bits 31 to 0 this means that when address h'00001003 is set without specifying the size condition, for example, the bus cycle in which the break cond ition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 3. when the data value is included in the break conditions on b channel: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (bbra and bbrb). when data values are included in break conditions, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31 to 16 of bdrb and bdmrb are ignored. 4. when the dmac data access is included in the break condition: when the address is included in the break cond ition on dmac data access, the operand size of the break bus cycle registers (bbra and bbrb) should be byte, word or no operand size specification. when the data value is in cluded, select either byte or word.
section 8 user break controller rev.6.00 mar. 27, 2009 page 224 of 1036 rej09b0254-0600 8.3.4 break on x/y-memory bus cycle 1. the break condition on x/y-memory bus cycle is specified only in channel b. if xye in bbrb is set to 1, break address and break data on x/y-memory bus are selected. at this time, select x-memory bus or y-memory bus by specifying xys in bbrb. the break condition cannot include both x-memory and y-memory at the same time. the break condition is applied to x/y-memory bus cycle by specifying cpu/data access/read or write/word or no operand size specification in the break bus cycle register b (bbrb). 2. when x-memory address is selected as th e break condition, specify x-memory address in upper 16 bits in barb and bamrb. when y-me mory address is selected, specify y-memory address in lower 16 bits. specification of x/y-memory data is the same for bdrb and bdmrb. 8.3.5 sequential break 1. by specifying seq in brcr is set to 1, the sequential break is issued when channel b break condition matches after channel a break condition matches. a user break is ignored even if channel b break condition matches before channel a break condition matches. when channels a and b condition match at the same time, the sequential break is not issued. 2. in sequential break specification, internal/x /y bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied at channel b condition match with betr = h'0001 after channel a condition match. 8.3.6 value of saved program counter the pc when a break occurs is saved to the spc in user breaks. the pc value saved is as follows depending on the type of break. 1. when instruction fetch (before instruction execution) is specified as a break condition: the value of the program counter (pc) saved is the address of the instruction that matches the break condition. the fetched instruction is not executed, and a break occurs before it. 2. when instruction fetch (after instruction execution) is specified as a break condition: the pc value saved is the address of the instruction to be executed following the instruction in which the break condition matches. the fetched instruction is executed, and a break occurs before the execution of the next instruction.
section 8 user break controller rev.6.00 mar. 27, 2009 page 225 of 1036 rej09b0254-0600 3. when data access (address only) is specified as a break condition: the pc value is the address of the instruction to be executed following the instruction that matched the break condition. the instruction that matched the condition is executed and the break occurs before the next instruction is executed. 4. when data access (address + data) is specified as a break condition: the pc value is the start address of the instruction that follows the instruction already executed when break processing started up. when a data value is added to the break conditions, the place where the break will occur cannot be specifi ed exactly. the break will occur before the execution of an instruction fetched around the data access where the break occurred. 8.3.7 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in brsr and brdr, respectively. the branch address and the pointer, wh ich corresponds to the branch, are included in brsr. 2. the branch address before branch occurs ca n be calculated from the address and the pointer stored in brsr. the expression from bsa (the address in brsr), pid (the pointer in brsr), and ia (the instruction address before branch occurs) is as follows: ia = bsa ? 2 * pid. notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. in case of the next fi gure, the instruction ?exec? executed immediately before branch is calculated by ia = bsa ? 2 * pid. however, when branch ?branch? has delay slot and the destination address is 4n + 2 addr ess, the address ?dest? which is specified by branch instruction is stored in brsr (dest = bsa). therefore, as ia = bsa ? 2 * pid is not applied to this case, this pid is invalid. th e case where bsa is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: exec: branch dest dest: instr (not executed) interrupt int: interrupt routine if the pid value is odd, instruction buffer indicates pid+2 buffer. however, these expressions in this table are accounted for it. therefore, th e true branch source address is calculated with bsa and pid values stored in brsr.
section 8 user break controller rev.6.00 mar. 27, 2009 page 226 of 1036 rej09b0254-0600 3. the branch address before branch occurrence, ia, has different values due to some kinds of branch. a. branch instruction the branch instruction address b. repeat the instruction before the last instruction of a repeat loop repeat_start: inst (1); brdr inst (2); : inst (n-1); the address calculated from brsr repeat_end: inst (n); c. interrupt the last instruction executed before interrupt the top address of interrupt routine is stored in brdr. in a repeat loop with instructions less than thr ee, no instruction fetch cycle appears and branch source address is unkno wn. therefore, pc trace is disabled. 4. brsr and brdr have eight pairs of queue struct ures. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shifts after brdr is read. when reading brdr, longword access should be used . also, the pc trace has a trace pointer, which initially points to the bottom of the queues. the first pair of br anch addresses will be st ored at the bottom of the queues, then push up when next pairs come into the queues. the trace pointer will points to the next branch address to be executed, unless it got push out of the queues. when the branch address has been executed, the tr ace pointer will shift down to next pair of addresses, until it reaches the bottom of the queu es. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. the read point er stay at the position before pcte is switched, but the trace pointer restart at the bottom of the queues.
section 8 user break controller rev.6.00 mar. 27, 2009 page 227 of 1036 rej09b0254-0600 8.3.8 usage examples break condition specified to a cpu instruction fetch cycle 1. register specifications bara = h'00000404, bamra = h'00000000, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300400 specified conditions: channel a/channel b independent mode ? channel a address: h'00000404, address mask: h'00000000 bus cycle: cpu/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) no asid check is included ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before inst ruction execution)/read (operand size is not included in the condition) no asid check is included a user break occurs after an instruction of address h'00000404 is executed or before instructions of adresses h'00008010 to h'00008016 are executed. 2. register specifications bara = h'00037226, bamra = h'00000000 , bbra = h'0056, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequence mode ? channel a address: h'00037226, address mask: h'00000000, asid = h'80 bus cycle: cpu/instruction fetch (before instruction execution)/read/word ? channel b address: h'0003722e, address mask: h'00000000, asid = h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word
section 8 user break controller rev.6.00 mar. 27, 2009 page 228 of 1036 rej09b0254-0600 an instruction with asid = h'80 and address h'00037226 is executed, and a user break occurs before an instruction with asid = h'70 and address h'0003722e is executed. 3. register specifications bara = h'00027128, bamra = h'00000000, bbra = h'005a, barb = h'00031415, bamrb = h'00000000, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300000 specified conditions: channel a/channel b independent mode ? channel a address: h'00027128, address mask: h'00000000 bus cycle: cpu/instruction fetch (bef ore instruction execution)/write/word no asid check is included ? channel b address: h'00031415, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before inst ruction execution)/read (operand size is not included in the condition) no asid check is included on channel a, no user break occurs since instru ction fetch is not a write cycle. on channel b, no user break occurs since instruction fe tch is performed for an even address. 4. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'005a, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequence mode ? channel a address: h'00037226, address mask: h'00000000, asid: h'80 bus cycle: cpu/instruction fetch (bef ore instruction execution)/write/word ? channel b address: h'0003722e, address mask: h'00000000, asid: h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/word since instruction fetch is not a write cycle on channel a, a sequence condition does not match. therefore, no user break occurs.
section 8 user break controller rev.6.00 mar. 27, 2009 page 229 of 1036 rej09b0254-0600 5. register specifications bara = h'00000500, bamra = h'00000000, bbra = h'0057, barb = h'00001000, bamrb = h'00000000, bbrb = h'0057, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300001, betr = h'0005 specified conditions: channel a/channel b independent mode ? channel a address: h'00000500, address mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword ? channel b address: h'00001000, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before instruction execution)/read/longword the number of exec ution-times break enable (5 times) on channel a, a user break occurs before an instruction of address h'00000500 is executed. on channel b, a user break occurs before the fifth instruction execution after instructions of address h'00001000 are executed four times. 6. register specifications bara = h'00008404, bamra = h'00000fff, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000400, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00008404, address mask: h'00000fff, asid: h'80 bus cycle: cpu/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006, asid: h'70 data: h'00000000, data mask: h'00000000 bus cycle: cpu/instruction fetch (before inst ruction execution)/read (operand size is not included in the condition) a user break occurs after an instruction with asid = h'80 and address h'00008000 to h'00008ffe is executed or before instructions with asid = h'70 and addresses h'00008010 to h'00008016 are executed.
section 8 user break controller rev.6.00 mar. 27, 2009 page 230 of 1036 rej09b0254-0600 break condition specified to a cpu data access cycle 1. register specifications bara = h'00123456, bamra = h'00000000 , bbra = h'0064, barb = h'000abcde, bamrb = h'000000ff, bbrb = h'006a, bdrb = h'0000a512, bdmrb = h'00000000, brcr = h'00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00123456, address mask: h'00000000, asid: h'80 bus cycle: cpu/data access/read (operand size is not included in the condition) ? channel b address: h'000abcde, address mask: h'000000ff, asid: h'70 data: h'0000a512, data mask: h'00000000 bus cycle: cpu/data access/write/word on channel a, a user break occurs with asid = h'80 during longword read to address h'00123454, word read to address h'00123456, or byte read to address h'00123456. on channel b, a user break occurs with asid = h'70 when word h'a512 is written in addresses h'000abc00 to h'000abcfe. 2. register specifications bara = h'01000000, bamra = h'00000000 , bbra = h'0066, barb = h'0000f000, bamrb = h'ffff0000, bbrb = h'036a, bdrb = h'00004567, bdmrb = h'00000000, brcr = h'00300080 specified conditions: channel a/channel b independent mode ? channel a address: h'01000000, address mask: h'00000000 bus cycle: cpu/data access/read/word no asid check is included ? channel b y address: h'0001f000, address mask: h'ffff0000 data: h'00004567, data mask: h'00000000 bus cycle: cpu/data access/write/word no asid check is included on channel a, a user break occurs during word read to address h'01000000 on the memory space. on channel b, a user break occurs when word h'4567 is written in address h' 0001f000
section 8 user break controller rev.6.00 mar. 27, 2009 page 231 of 1036 rej09b0254-0600 on y memory space. the x/y-memory spa ce is changed by a mode specification. break condition specified to a dmac data access cycle 1. register specifications bara = h'00314156, bamra = h'00000000, bbra = h'0094, barb = h'00055555, bamrb = h'00000000, bbrb = h'00a9, bdrb = h'00000078, bdmrb = h'0000000f, brcr = h'00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00314156, address mask: h'00000000, asid: h'80 bus cycle: dmac/instruction fetch/read (operand size is not included in the condition) ? channel b address: h'00055555, address mask: h'00000000, asid: h'70 data: h'00000078, data mask: h'0000000f bus cycle: dmac/data access/write/byte on channel a, no user break occurs since inst ruction fetch is not performed in dmac cycles. on channel b, a user break occurs with asid = h'70 when the dmac writes byte h'7* in address h'00055555. 8.3.9 usage notes 1. only cpu can read/write ubc registers. 2. ubc cannot monitor cpu and dm ac access in the same channel. 3. notes in specification of sequential break are described below: (1) a condition match occurs when b-channel matc h occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no condition match occurs even if a bus cycle, in which an a-channel match and a channel b match occur simultaneously, is set. (2) since the cpu has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. (3) when the bus cycle condition for channel a is specified as a break before execution (pcba = 0 in brcr) and an instruction fetch cy cle (in bbra), the attention is as follows. a break is issued and condition match flags in brcr are set to 1, when the bus cycle conditions both for channels a and b match simultaneously.
section 8 user break controller rev.6.00 mar. 27, 2009 page 232 of 1036 rej09b0254-0600 4. the change of a ubc register value is ex ecuted in ma (memory access) stage. therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. in order to know the timing ubc register is changed, read th e last written register. instructions after then are valid for the newly written register value. 5. notes in specifying the instruction during repeat execution with repeat instruction as the break condition are as follows: when the instruction during repeat execution is specified as the break condition, (1) the break is not issued duri ng repeat execution, which has fewer than three instructions. (2) when the execution times break is set, no instruction fetch from memory occurs during repeat execution under three instructions. ther efore, the execution times register betr is not decreased. 6. the branch instruction should not be execut ed as soon as pc trace register brsr and brdr are read. 7. when pc breaks and tlb exceptions or errors oc cur in the same instruction. the priority is as follows: (1) break and instruction fetch exceptions: instruction fetch exception occurs first. (2) break before execution and operand excepti on: break before execution occurs first. (3) break after execution and operand exce ption: operand exception occurs first.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 233 of 1036 rej09b0254-0600 section 9 power-down modes and software reset 9.1 overview in the power-down modes, all cpu and some on-chip supporting module functions are halted. this lowers power consumption. in particular, the x/y memory can be stopped to significantly reduce power consumption. software reset f unction enables each module to reset itself. 9.1.1 power-down modes the SH7727 has three power-down modes: 1. sleep mode 2. standby mode 3. module standby function (tmu, rtc, sci, x/y memory, ubc, dmac, dac, adc, scif, lcdc, pcc, usbh, usbf, afeif, and siof on-chip supporting modules) 4. hardware standby mode table 9.1 shows the transition conditions for enteri ng any mode from the program execution state, the cpu and supporting module states in each m ode, and the procedures for canceling each mode.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 234 of 1036 rej09b0254-0600 table 9.1 power-down modes state mode transition conditions cpg cpu cpu register on-chip memory on-chip supporting modules pins external memory canceling procedure sleep mode execute sleep instruction with stby bit cleared to 0 in stbcr * 7 runs halts held held run held refresh 1. interrupt 2. reset standby mode execute sleep instruction with stby bit set to 1 in stbcr * 4 * 5 halts halts held held halt * 1 held self- refresh 1. interrupt 2. reset module standby function set mstp bit of stbcr to 1 * 6 runs runs or halts held held specified module halts * 2 refresh 1. clear mstp bit to 0 2. reset hardware standby mode drive ca pin low halts halts held held halt * 3 held self- refresh power-on reset notes: 1. the rtc runs if the start bit in rcr2 is set to 1 (see section 16, realtime clock (rtc)). tmu runs when output of the rtc is used as input to its counter (see section 15, timer (tmu)). 2. depends on the on-chip supporting module. tmu external pin: held sci external pin: reset 3. the rtc runs if the start bit in rcr2 is set to 1. tmu does not run. 4. usb and lcdc must be stopped before entering standby mode. 1) to stop lcdc, set 0 to don bit. 2) to stop the usb host controller, set usbreset bit in the hccontrol register. 5. for lcdc, refer to the lps bit in ldp mmr to confirm that power-off sequence has been completed before entering standby-mode. 6. when putting the rtc into module standby mode, first access one or more of registers rtc, sci, and tmu. then put the rtc into module standby mode. 7. do not cause the cpu to transition to sleep mode, or cancel sleep mode, during a transmit or receive operation in which the usb function controller or siof uses dma.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 235 of 1036 rej09b0254-0600 9.1.2 pin configuration table 9.2 lists the pins used for the power-down modes. table 9.2 pin configuration pin name symbol i/o description processing state 1 status1 o processing state 0 status0 o indicate operating stat e of the processor. hh: reset, hl: sleep mode, lh: standby mode, ll: normal operation note: h means high level, and l means low level. 9.1.3 register configuration table 9.3 shows the configuration of the control register for the power-down modes. table 9.3 register configuration name abbreviation r/w initia l value address access size standby control register stbcr r/w h'00 * 1 h'ffffff82 8 standby control register 2 stbcr2 r/w h'00 * 1 h'ffffff88 8 standby control register 3 stbcr3 r/w h'00 * 1 h?04000230 (h?a4000230) * 2 8 software reset register srstr r/w h'00 * 1 h?04000232 (h?a4000232) * 2 8 notes: 1. initialized by power-on resets. not init ialized by manual resets but the contents are held. 2. the addresses in parentheses ( ) should be used when no address translation by the mmu is involved.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 236 of 1036 rej09b0254-0600 9.2 register description 9.2.1 standby control register (stbcr) the standby control register (stbcr) is an 8-bit readable/writable register that sets the power- down mode. stbcr is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 stby ? ? stbxtl ? mstp2 mstp1 mstp0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r/w r r/w r/w r/w bit 7?standby (stby): specifies transition to standby mode. bit 7: stby description 0 executing sleep instruction puts the chip into sleep mode. (initial value) 1 executing sleep instruction puts the chip into standby mode. bits 6, 5, and 3?reserved: these bits are always read as 0. the write value should always as 0. bit 4?standby crystal (stbxtl): enables/disables crystal resonator in standby mode. bit 4: stbxtl description 0 crystal oscillator in standby mode disabled (initial value) 1 crystal oscillator in standby mode enabled bit 2?module stop 2 (mstp2): specifies halting the clock supply to the timer unit (tmu) in the on-chip supporting module. when the mstp2 bit is set to 1, the clock supply to the tmu is halted. bit 2: mstp2 description 0 tmu runs. (initial value) 1 clock supply to tmu is halted.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 237 of 1036 rej09b0254-0600 bit 1?module stop 1 (mstp1): specifies halting the clock supply to the realtime clock (rtc) in the on-chip supporting module. when the mstp1 bit is set to 1, the clock supply to rtc is halted. when the clock halts, all rtc registers cannot be accessed, but the counter keeps running. bit 1: mstp1 description 0 rtc runs. (initial value) 1 clock supply to rtc is halted. bit 0?module stop 0 (mstp0): specifies halting the clock suppl y to the serial communication interface (sci) in the on-chip supporting module. when the mstp0 bit is set to 1, the clock supply to the sci is halted. bit 0: mstp0 description 0 sci runs. (initial value) 1 clock supply to sci is halted. 9.2.2 standby control register 2 (stbcr2) the standby control register 2 (stbcr2) is an 8-b it readable/writable register that controls the operation of the peripheral modules in the normal mode and sleep mode. stbcr is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 mstp9 mdchg mstp8 mstp7 mstp6 mstp5 mstp4 ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r bit 7? module stop 9 (mstp9): specifies halting the clock supply to the x/y memory. when the mstp9 bit is set to 1, the clock supply to the x/y memory is halted. halting of the clock supply to the x/y memory must be controlle d by software (any access is not blocked by hardware). bit 7: mstp9 description 0 x/y memory runs (initial value) 1 clock supply to x/y memory is halted
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 238 of 1036 rej09b0254-0600 bit 6?md5 to md0 pin control (mdchg): specifies whether or not pins md5 to md0 are switched in standby mode. when this bit is set to 1, the md5 to md0 pin values are latched when returning from standby mode by means of a reset or interrupt. bit 6: mdchg description 0 pins md5 to md0 are not switched in standby mode (initial value) 1 pins md5 to md0 are switched in standby mode bit 5? module stop 8 (mstp8): specifies halting the clock supply to the user break controller (ubc) in the on-chip supp orting module. when the mstp8 bit is set to 1, the clock supply to the ubc is halted. bit 5: mstp8 description 0 ubc runs (initial value) 1 clock supply to ubc is halted bit 4?module stop 7 (mstp7): specifies halting of clock supp ly to the direct memory access controller (dmac) in the on-chip supporting module. when the mstp7 bit is set to 1, the clock supply to the dmac is halted. bit 4: mstp7 description 0 dmac runs (initial value) 1 clock supply to dmac halted bit 3?module stop 6 (mstp6): specifies halting of clock supply to the d/a converter (dac) in the on-chip supporting module. when the mstp6 bit is set to 1, the clock supply to the dac is halted. bit 3: mstp6 description 0 dac runs (initial value) 1 clock supply to dac halted bit 2?module stop 5 (mstp5): specifies halting of clock supply to the a/d converter (adc) in the on-chip supporting module. when the mstp5 bit is set to 1, the clock supply to the adc is halted and all registers are initialized.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 239 of 1036 rej09b0254-0600 bit 2: mstp5 description 0 adc runs (initial value) 1 clock supply to adc halted, and all registers initialized bit 1?module stop 4 (mstp4): specifies halting the clock suppl y to the serial communication interface sci (scif) with fifo. when the mstp4 bit is set to 1, the clock supply to the scif is halted bit 1: mstp4 description 0 scif runs (initial value) 1 clock supply to sci2 (scif) halted bit 0? reserved: this bit is always read as 0. the write value should always as 0. 9.2.3 standby control register 3 (stbcr3) the standby control register 3 (stbcr3) is an 8- bit readable/writable register that controls standby operation for the on-chip supporting modules. stbcr3 is in itialized to h'00 by a power- on reset. bit: 7 6 5 4 3 2 1 0 mstp17 ? mstp15 mstp14 mstp13 ? mstp11 mstp10 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7? module stop 17 (mstp17): specifies halting the clock supply to the serial io with fifo interface (siof). when the mstp17 bit is set to 1, the clock supply to the serial io with fifo interface (siof) is halted. bit 7: mstp17 description 0 siof runs (initial value) 1 clock supply to siof halted bit 6? reserved: this bit is always read as 0. the write value should always as 0.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 240 of 1036 rej09b0254-0600 bit 5? module stop 15 (mstp15): specifies halting the clock supply to the afe interface (afe if). when the mstp15 bit is set to 1, th e clock supply to the afe interface is halted. bit 5: mstp15 description 0 afe interface runs (initial value) 1 clock supply to afe interface halted bit 4? module stop 14 (mstp14): specifies halting the clock supply to the usb function module (usbf). when the mstp14 bit is set to 1, the clock supply to the usbf is halted. bit 4: mstp14 description 0 usbf runs (initial value) 1 clock supply to usbf halted bit 3?module stop 13 (mstp13): specifies halting the clock supply to the usb host controller (usbh). when the mstp13 bit is set to 1, the clock supply to the usbh is halted. bit 3: mstp13 description 0 usbh runs (initial value) 1 clock supply to usbh halted note: this bit should not be set to 1 when mstp14 (bit 4) is 0. bit 2??reserved: this bit is always read as 0. the write value should always as 0. bit 1? module stop 11 (mstp11): specifies halting the clock supply lcd controller (lcdc). when the mstp11 bit is set to 1, the clock supply to the lcdc is halted. bit 1: mstp11 description 0 lcdc runs (initial value) 1 clock supply to lcdc halted bit 0? module stop 10 (mstp10): specifies halting the clock supply to pc card controller (pcc). when the mstp10 bit is set to 1, the clock supply to the pcc is halted. bit 0: mstp10 description 0 pcc runs (initial value) 1 clock supply to pcc halted
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 241 of 1036 rej09b0254-0600 9.2.4 module software reset register (srstr) the software reset register (srstr) is an 8-bit readable/writable register that controls module reset operation equivalent to power-on reset. sr str is initialized to h'00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 siofr ? afecr usbfr usbhr lbscr lcdcr pccr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r/w r/w r/w r/w r/w bit 7? siof reset (siofr): when the siof bit is set to 1, the serial i/o (siof) is reset. 0 should be written after writing 1. bit 7: siofr description 0 not reset siof (initial value) 1 resets siof bit 6?reserved: this bit is always read as 0. the write value should always be 0. bit 5? afeif reset (afecr): when the afec bit is set to 1, the afe interface (afeif) is reset. 0 should be written after writing 1. bit 5: afecr description 0 not reset afeif (initial value) 1 resets afeif bit 4? usbf reset (usbfr): when the usbf bit is set to 1, the sub function module (usbf) is reset. 0 should be written after writing 1. bit 4: usbfr description 0 not reset usbf (initial value) 1 resets usbf
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 242 of 1036 rej09b0254-0600 bit 3? usbh reset (usbhr): when the usbh bit is set to 1, the usb host controller is reset. 0 should be written after writing 1. bit 3: usbhr description 0 not reset usbh (initial value) 1 resets usbh bit 2? lbsc reset (lbscr): when the lbsc bit is set to 1, the li bus state controller (lbsc) is reset. 0 should be written after writing 1. bit 2: lbscr description 0 not reset lbsc (initial value) 1 resets lbsc bit 1? lcdc reset (lcdcr): when the lcdc bit is set to 1, the lcd controller (lcdc) is reset. 0 should be written after writing 1. bit 1: lcdcr description 0 not reset lcdc (initial value) 1 resets lcdc bit 0? pcc reset (pccr): when the pcc bit is set to 1, pc card controller (pcc) is reset. 0 should be written after writing 1. bit 0: pccr description 0 not reset pcc (initial value) 1 resets pcc
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 243 of 1036 rej09b0254-0600 9.3 sleep mode 9.3.1 transition to sleep mode executing the sleep inst ruction when the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers are retained . the on-chip supporting modules continue to run during sleep mode and the clock continues to be output to the ckio and ckio2 pins. in sleep mode, the status1 pin is set to high and the status0 pin low. 9.3.2 canceling sleep mode sleep mode is canceled by an interrupt (nmi, irq, irl, on-chip supporting module interrupt, pint) or reset. interrupts are accep ted during sleep mode even when the bl bit in the sr register is 1. if necessary, save spc and ssr in the stack before executing th e sleep instruction. canceling with an interrupt: when an nmi, irq, irl or on-chip supporting module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. a code corresponding to the interrupt source is set in the intevt and intevt2 registers. canceling with a reset: sleep mode is canceled by a power-on reset or a manual reset. 9.4 standby mode 9.4.1 transition to standby mode to enter standby mode, set the stby bit to 1 in stbcr, then execute the sleep instruction. the chip moves from the program execution state to standby mode. in standby mode, not only the cpu, but the clock and on-chip supporting modules are halted. the clock output from the ckio and ckio2 pins also halts. the contents of the cpu and cach e register are held, but some on-chip supporting modules are initialized. table 9.4 lists the states of registers in standby mode.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 244 of 1036 rej09b0254-0600 table 9.4 register states in standby mode module registers initialized registers retaining data interrupt controller (intc) ? all registers on-chip clock pulse generator (osc) ? all registers user break controller (ubc) ? all registers bus state controller (bsc) ? all registers timer unit (tmu) tstr register registers other than tstr realtime clock (rtc) ? all registers a/d converter (adc) all registers ? d/a converter (dac) ? all registers li bus state controller (lbsc) ? all registers lcd controller (lcdc) ? all registers usb host controller (usbh) ? all registers usb function module (usbf) ? all registers afe interface (afeif) ? all registers serial io with fifo (siof) ? all registers pc card controller (ppc) ? registers other than pcc0isr * note: * pcc0isr reflects the normal status. the procedure for moving to standby mode is as follows: 1. clear the tme bit in the wdt?s timer contro l register (wtcsr) to 0 to stop the wdt. set the wdt?s timer counter (wtcnt) to 0 and set a value to the cks2 to cks0 bits in the wtcsr register to secure the specified oscillation settling time. 2. after the stby bit in the st bcr register is set to 1, the sleep instruction is executed. 3. when the chip enters standby mode and the clocks within the chip are halted, he status1 pin output goes low and the status0 pin output goes high.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 245 of 1036 rej09b0254-0600 9.4.2 canceling standby mode standby mode is canceled by an interrupt (nmi, irq, irl, on-chip supporting module interrupt or pint) or a reset. canceling with an interrupt: the on-chip wdt can be used for hot starts. when the chip detects an nmi, irl, irq, pint * 1 , or on-chip supporting module (except the interval timer) * 2 interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the wdt?s timer control/status register has elapsed. the status1 and status0 pins both go low. interrupt exception handling then begins and a code corresponding to the interrupt source is set in the intevt and intevt2 registers. after branchin g to the interrupt processing routine occurs, clear the stby bit in the stbcr register. the wtcnt stops automatically. if the stby bit is not cleared, wtcnt continues operatio n and transits to the standby mode * 3 when it reaches h?80. this function prevents the data from being destroyed due to a rising voltage under an unstable power supply. interrupts are accep ted during standby mode even when the bl bit in the sr register is 1. if necessary, save spc and ssr in th e stack before executing the sleep instruction. immediately after an interrupt is detected, the ph ase of the clock output of the ckio and ckio2 pin may be unstable, until the standby mode is canceled. the canceling condition is that the interrupt request level (irq, irl, or on-chip supporting module interrupt) is higher than the mask level in the i3 to i0 bits in the sr register. notes: 1. when the rtc is being used, standby mode can be canceled using irl3 to irl0 , irq4 to irq0 or pint0 to pint5. 2. standby mode can be canceled with an rtc or tmu (only when running on the rtc clock) interrupt. 3. use a power-on reset to cancel standby mode. operation is not guaranteed in the cas e of a manual reset or interrupt input.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 246 of 1036 rej09b0254-0600 wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear bit stbcr.stby before wtcnt reaches h'80. when stbcr.stby is cleared, wtcnt halts automatically. figure 9.1 canceling standby mode with stbcr.stby canceling with a reset: standby mode can be canceled with a reset (power-on or manual). keep the reset or resetm pin low until the clock oscillation settles. the internal clock will be output continuously to the ckio pin. 9.4.3 clock pause function in standby mode, the clock input from the extal pin or ckio pin can be halted and the frequency can be changed. this function is used as follows: 1. enter standby mode using the procedure for changing to standby mode. 2. when the chip enters standby mode and the clock stopped within the chip, the status1 pin output is low and the status0 pin output is high. 3. when the status1 pin goes low and the status0 pin goes high, the input clock is stopped or the frequency is changed. 4. when the frequency is changed, an nmi, irl, irq, pint or on-chip supporting module (except the internal timer) interrupt is input after changing the frequency. when the clock is stopped, the same interrupts are input after the clock is applied. 5. after the time set in the wdt has elapsed, the clock starts being applied within the chip, the status1 and status0 pins both go low, operation resumes from the interrupt exception handling.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 247 of 1036 rej09b0254-0600 9.5 module standby function 9.5.1 transition to module standby function setting the standby control register stbcr, stbcr2, stbcr3, mstp17, mstp15 to mstp13, mstp11 to mstp4, and mstp 2 to mstp0 bits to 1 halts the clock supply to the corresponding on-chip supporting modules. by using this function, the power consumption in normal mode and sleep mode can be reduced. in the module standby function, external pins of the on-chip supporting modules are different depending on the on-chip supporting modules. tmu external pins hold their state prior to the halt. sci external pins go to the reset state. with a few exceptions, all registers hold their values.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 248 of 1036 rej09b0254-0600 bit value description mstp17 0 siof runs. 1 clock supply to siof halted. mstp15 0 afeif runs. 1 clock supply to afeif halted. mstp14 0 usbf runs. 1 clock supply to usbf halted. mstp13 0 usbh runs. 1 clock supply to usbh halted. this bit should not be set to 1 when mstp14 (bit 4) is 0. mstp11 0 lcdc runs. 1 clock supply to lcdc halted. mstp10 0 pcc runs. 1 clock supply to pcc halted. mstp9 0 x/y memory runs. 1 clock supply to x/y memory halted. mstp8 0 ubc runs. 1 clock supply to ubc halted. mstp7 0 dmac runs. 1 clock supply to dmac halted. mstp6 0 dac runs. 1 clock supply to dac halted. mstp5 0 adc runs. 1 clock supply to adc halted, and all registers initialized. mstp4 0 scif runs. 1 clock supply to scif halted. mstp2 0 tmu runs. 1 clock supply to tmu halted. * 1 mstp1 0 rtc runs. 1 clock supply to rtc halted. register access prohibited. * 2 mstp0 0 sci runs. 1 clock supply to sci halted. notes: 1. the initialized registers are the sa me as in the standby mode (see table 9.4). 2. the counter runs.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 249 of 1036 rej09b0254-0600 9.5.2 clearing the module standby function the module standby function can be cleared by clearing the mstp17, mstp15 to mstp13, mstp11 to mstp4, and mstp2 to mstp0 bits to 0, or by a power-on reset or manual reset. 9.6 timing of status pin changes the timing of status1 and status0 pin changes is shown in figures 9.2 to 9.9. the meanings of status are as follows: ? reset: hh (status1 is high, status0 is high) ? sleep: hl (status1 is high, status0 is low) ? standby: lh (status1 is low, status0 is high) ? normal: ll (status1 is low, status0 is low) the meanings of clock units are as follows: ? bcyc: bus clock cycle ? pcyc: peripheral clock cycle ? rcyc: 32.768-khz rtc clock cycle 9.6.1 timing for resets power-on reset ckio, ckio2 * resetp status normal normal reset pll settling time 0 to 5 bcyc 0 to 30 bcyc note: * ckio2 can be used at only clock modes 0, 1 and 2. figure 9.2 power-on reset (clock modes 0, 1, 2, and 7) status output
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 250 of 1036 rej09b0254-0600 manual reset ckio, ckio * 2 resetm status normal normal reset 0 bcyc or more * 1 0 to 30 bcyc notes: 1. during manual reset, status becomes hh (reset) and the internal reset begins after waiting for the executing bus cycle to end. 2. ckio2 can be used at only clock modes 0, 1 and 2. figure 9.3 manual reset status output 9.6.2 timing for canceling standbys standby to interrupt ckio, ckio2 * status normal normal wdt count oscillation stops standby interrupt request wdt overflow note: * ckio2 can be used at only clock modes 0, 1 and 2. figure 9.4 standby to interrupt status output
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 251 of 1036 rej09b0254-0600 standby to power-on reset ckio, ckio2 * 2 status normal normal oscillation stops standby 0 to 10 bcyc 0 to 30 bcyc reset reset resetp * 1 * 3 notes: 1. when standby mode is cleared with a power-on reset, the wdt does not count. keep resetp low during pll's oscillation settling time. 2. ckio2 can be used at only clock modes 0, 1 and 2. 3. undefined figure 9.5 standby to power-on reset status output standby to manual reset status normal normal oscillation stops standby reset 0 to 20 bcyc reset ckio, ckio2 * 2 resetm * 1 notes: 1. when standby mode is cleared with a power-on reset, the wdt does not count. keep resetm low during pll's oscillation settling time. 2. ckio2 can be used at only clock modes 0, 1 and 2. figure 9.6 standby to manual reset status output
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 252 of 1036 rej09b0254-0600 9.6.3 timing for ca nceling sleep mode sleep to interrupt status normal normal sleep interrupt request ckio, ckio2 * note: * ckio2 can be used at only clock modes 0, 1 and 2. figure 9.7 sleep to interrupt status output sleep to power-on reset status normal normal sleep 0 to 10 bcyc 0 to 30 bcyc reset reset ckio, ckio2 * 2 resetp * 1 * 3 notes: 1. when the pll's multiplication ratio is changed by a power-on reset, keep resetp low during pll's oscillation settling time. 2. ckio2 can be used at only clock modes 0, 1 and 2. 3. undefined figure 9.8 sleep to pow er-on reset status output
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 253 of 1036 rej09b0254-0600 sleep to manual reset 0 to 80 bcyc 0 to 30 bcyc reset status normal normal sleep reset notes: 1. keep resetm low until the status becomes reset. 2. ckio2 can be used at only clock modes 0, 1 and 2. ckio, ckio2 * 2 resetm * 1 figure 9.9 sleep to manual reset status output
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 254 of 1036 rej09b0254-0600 9.7 hardware standby mode 9.7.1 transition to hardware standby mode to enter hardware standby mode, set the ca pin low. in hardware standby mode, all modules except for any modules that run with rtc clock are halted as well as in standby mode entered by sleep instruction. differences between hardware standby m ode and standby mode are as follows. 1. interrupts and manual reset are not accepted in hardware standby mode. 2. the tmu does not run in hardware standby mode. operation when the ca pin goes low depends on the cpg status. 1. in standby mode the chip enters hardware standby mode, clock remains halted. interrupts and manual reset are not accepted and the tmu halts. 2. during wdt runs when clearing standby mode with an interrupt the chip enters hardware standby mode after the cpu resumes operation once standby mode is cleared. 3. in sleep mode the chip enters hardware standby mode after the cpu resumes operation once sleep mode is cleared. note that ca pin must keep low during hardware standby mode. 9.7.2 clearing the ha rdware standby mode hardware standby mode can be cleared only by power-on reset. the clock starts oscillation by setting ca pin high while resetp pin is low. at this time, keep the resetp pin low until the clock oscillation settles. then, the cpu starts power-on reset processing after setting the resetp pin high. the operation is not guaranteed when an interrupt or manual reset is occurred.
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 255 of 1036 rej09b0254-0600 9.7.3 timing of hardware standby mode the timings of each pin in hardware standby mode are shown in figures 9.10 and 9.11. ca pin is sampled by extal2 (32.768 khz). hardware standby request is detected when two continuous cycles go low in this clock. keep ca pin low during hardware standby mode. the clock starts oscillation when the ca pin is set high after setting the resetp pin low. normal * 3 status ca ckio, ckio2 * 6 standby * 2 reset * 1 resetp * 7 2 rcyc or more * 5 0 ? 10bcyc * 4 notes: 1. reset: hh (status1 is high, status0 is high) 2. standby: lh (status1 is low, status0 is high) 3. normal: ll (status1 is low, status0 is low) 4. bcyc: bus clock cycle 5. rcyc: extal2 (32.768 khz) clock cycle 6. ckio2 can be used at only clock modes 0,1 and 2. 7. undefined figure 9.10 hardware standby mode timing (ca = low in normal operation)
section 9 power-down modes and software reset rev.6.00 mar. 27, 2009 page 256 of 1036 rej09b0254-0600 normal * 3 status ca ckio, ckio2 * 6 reset * 1 resetp * 7 2 rcyc or more * 5 0 ? 10bcyc * 4 standby * 2 wdt operation standby notes: 1. reset: hh (status1 is high, status0 is high) 2. standby: lh (status1 is low, status0 is high) 3. normal: ll (status1 is low, status0 is low) 4. bcyc: bus clock cycle 5. rcyc: extal2 (32.768 khz) clock cycle 6. ckio2 can be used at only clock modes 0,1 and 2. 7. undefined figure 9.11 hardware standby mode timing (ca = low during wdt operation while standby mode is cleared)
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 257 of 1036 rej09b0254-0600 section 10 on-chip oscillation circuits 10.1 overview the on-chip oscillation circuits consist of the clock pulse generator (cpg) and watchdog timer (wdt). the clock pulse generator (cpg) supplies all clocks to the processor and controls the power-down modes. the watchdog timer (wdt) is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary st andby, such as frequency changes. it can also be used as an ordinary watchdog timer or interval timer. 10.1.1 features the cpg has the following features: ? four clock modes: selection of four clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input. ? three clocks generated independently: an internal clock for the cpu, cache, and tlb (i ); a peripheral clock (p ) for the on-chip supporting modules; and a bus clock (ckio) for the external bus interface. ? frequency change function: internal and peripheral clock frequencies can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using frequency control register (frqcr) settings. ? power-down mode control: the clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 258 of 1036 rej09b0254-0600 the wdt has the following features: ? can be used to ensure the clock settling time: use the wdt to cancel standby mode and the temporary standby which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode: internal resets occur after counter overflow. selection of power-on reset or manual reset. ? generates interrupts in interval timer mode: internal timer interrupts occur after counter overflow. ? selection of eight counter input clocks. eight clocks ( 1 to 1/4096) can be obtained by dividing the peripheral clock.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 259 of 1036 rej09b0254-0600 10.2 overview of the cpg 10.2.1 cpg block diagram a block diagram of the on-chip clock pulse generator is shown in figure 10.1. cap1 ckio2 ckio cycle = bcyc cap2 xtal extal md2 md1 md0 frqcr internal bus bus interface stbcr pll circuit 1 ( 1, 2, 3, 4, 6) divider 1 internal clock (i ) cycle = icyc peripheral clock (p ) cycle = pcyc standby control divider 2 clock pulse generator pll circuit 2 ( 1, 4) crystal oscillator cpg control unit clock frequency control circuit standby control circuit 1 1/2 1/3 1/4 1 1/2 1/3 1/4 1/6 frqcr: frequency control register stbcr: standby control register bus clock (p ) cycle = bcyc legend: figure 10.1 block diagra m of clock pulse generator
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 260 of 1036 rej09b0254-0600 the clock pulse generator blocks function as follows: 1. pll circuit 1 pll circuit 1 doubles, triples, quadruples, se xtuples, or leaves unchanged the input clock frequency from the ckio pin or pll circuit 2. the multiplication rate is set by the frequency control register. when this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phas e of the leading edge of the ckio pin. 2. pll circuit 2 pll circuit 2 leaves quadruples the frequency of the crystal oscillator or the input clock frequency coming from the extal pin. the multiplication ratio is fixed by the clock operation mode. the clock operation mode is set by pins md0, md1, and md2. see table 10.3 for more information on clock operation modes. 3. crystal oscillator this oscillator is used when a crystal resonator element is connected to the xtal and extal pins. it operates according to th e clock operating mode setting. 4. divider 1 divider 1 generates a clock at the operating frequency used by the internal clock. the operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1, as long as it stays at or above the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 5. divider 2 divider 2 generates a clock at the operating frequency used by the peripheral clock. the operating frequencies can be 1, 1/2, 1/3,1/4, or 1/6 times the output frequency of pll circuit 1 or the clock frequency of the ckio pin, as long as it stays at or below the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 6. clock frequency control circuit the clock frequency control circuit controls the clock frequency using the md pin and the frequency control register. 7. standby control circuit the standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. frequency control register the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, pll standby, the frequency multiplication ratio of pll 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. standby control register the standby control register has bits for c ontrolling the power-down modes. see section 9, power-down modes and software reset, for more information.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 261 of 1036 rej09b0254-0600 10.2.2 cpg pin configuration table 10.1 lists the cpg pins and their functions. table 10.1 clock pulse generator pins and functions pin name symbol i/o description mode control pins md0 i set the clock operating mode. md1 i md2 i xtal o connects a crystal resonator. crystal i/o pins (clock input pins) extal i connects a crystal reso nator. also used to input an external clock. clock i/o pin ckio i/o inputs or outputs an external clock. clock out pin ckio2 o output external cl ock. level can be fixed. only clock modes 0, 1, 2 can be supported for this pin. capacitor connection pins cap1 i connects capacitor for pll circuit 1 operation (recommended value 470 pf). for pll cap2 i connects capacitor for pll circuit 2 operation (recommended value 470 pf). 10.2.3 cpg register configuration table 10.2 shows the cpg register configuration. table 10.2 register configuration register name abbreviation r/w initial value address access size frequency control register frq cr r/w h'0102 h'ffffff80 16 bits ckio2 control register 2 ckio2cr r/w h'0000 h'0400023a (h'a400023a) * 16 bits note: * when address translation by the mmu does not apply, the address in parentheses should be used.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 262 of 1036 rej09b0254-0600 10.3 clock operating modes table 10.3 shows the relationship between the mode control pin (md2 to md0) combinations and the clock operating modes. table 10.4 shows the usable frequency ranges in the clock operating modes. table 10.3 clock operating modes pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off divider 1 input divider 2 input ckio frequency 0 0 0 0 extal ckio on, multi- plication ratio: 1 on pll1 output pll1 (extal) 1 0 0 1 extal ckio on, multi- plication ratio: 4 on pll1 output pll1 (extal) 4 2 0 1 0 crystal resonator ckio on, multi- plication ratio: 4 on pll1 output pll1 (crystal) 4 7 1 1 1 ckio ? off on pll1 output pll1 (ckio) mode 0: an external clock is input from the extal pin and undergoes waveform shaping by pll circuit 2 before being supplied inside this lsi. pll circuit 1 is constantly on. an input clock frequency of 24 mhz to the maximum frequency of ckio can be used. for details on the ckio maximum frequency, see section 32, electrical characteristics. mode 1: an external clock is input from the extal pin and its frequency is multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. an input clock frequency of 6 mhz to1/4 of the maximum frequency of ckio can be used. for details on the ckio maximum frequency, see section 32, electrical characteristics. mode 2: the on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low crystal frequency to be used. a crystal resonator frequency of 6 mhz to 1/4 of the maximum frequency of ckio can be used. for details on the ckio maximum frequenc y, see section 32, electrical characteristics.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 263 of 1036 rej09b0254-0600 mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to this lsi. in modes 0 to 2, the system clock is generated from the output of this lsi?s ckio pin. consequently, if a large number of ics are operating on the clock cycle, the ckio pin load will be large. this m ode, however, assumes a comparatively large-scale system. if a large number of ics are operating on th e clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ics can operate synchronously by distributing the clocks to each one. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 264 of 1036 rej09b0254-0600 table 10.4 available combination of clock mode and frqcr values clock mode frqcr pll1 pll2 clock rate * (i:b:p) 0 h'0100 on ( 1) on ( 1) 1:1:1 h'0101 on ( 1) on ( 1) 1:1:1/2 h'0102 on ( 1) on ( 1) 1:1:1/4 h'0111 on ( 2) on ( 1) 2:1:1 h'0112 on ( 2) on ( 1) 2:1:1/2 h'0115 on ( 2) on ( 1) 1:1:1 h'0116 on ( 2) on ( 1) 1:1:1/2 h'0122 on ( 4) on ( 1) 4:1:1 h'0126 on ( 4) on ( 1) 2:1:1 h'012a on ( 4) on ( 1) 1:1:1 h'a100 on ( 3) on ( 1) 3:1:1 h'a101 on ( 3) on ( 1) 3:1:1/2 h'e100 on ( 3) on ( 1) 1:1:1 h'e101 on ( 3) on ( 1) 1:1:1/2 h'a111 on ( 6) on ( 1) 6:1:1 1, 2 h'0100 on ( 1) on ( 4) 4:4:4 h'0101 on ( 1) on ( 4) 4:4:2 h'0102 on ( 1) on ( 4) 4:4:1 h'0111 on ( 2) on ( 4) 8:4:4 h'0112 on ( 2) on ( 4) 8:4:2 h'0115 on ( 2) on ( 4) 4:4:4 h'0116 on ( 2) on ( 4) 4:4:2 h'0122 on ( 4) on ( 4) 16:4:4 h'0126 on ( 4) on ( 4) 8:4:4 h'012a on ( 4) on ( 4) 4:4:4 h'a100 on ( 3) on ( 4) 12:4:4 h'a101 on ( 3) on ( 4) 12:4:2 h'e100 on ( 3) on ( 4) 4:4:4 h'e101 on ( 3) on ( 4) 4:4:2 h?a111 on ( 6) on ( 1) 24:4:4
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 265 of 1036 rej09b0254-0600 clock mode frqcr pll1 pll2 clock rate * (i:b:p) 7 h'0100 on ( 1) off 1:1:1 h'0101 on ( 1) off 1:1:1/2 h'0102 on ( 1) off 1:1:1/4 h'0111 on ( 2) off 2:1:1 h'0112 on ( 2) off 2:1:1/2 h'0115 on ( 2) off 1:1:1 h'0116 on ( 2) off 1:1:1/2 h'0122 on ( 4) off 4:1:1 h'0126 on ( 4) off 2:1:1 h'012a on ( 4) off 1:1:1 h'a100 on ( 3) off 3:1:1 h'a101 on ( 3) off 3:1:1/2 h'e100 on ( 3) off 1:1:1 h'e101 on ( 3) off 1:1:1/2 h'a111 on ( 6) off 6:1:1 note: * taking input clock as 1 cautions: 1. the frequency ranges of the in put clock and crystal resonator shou ld be set within the specified frequency range based on the clock rate in table 10.4, and section 32.3, ac characteristics. 2. the input to divider 1 becomes the output of pll circuit 1 when pll circuit 1 is on. 3. the input of divider 2 becomes the output of: ? pll circuit 1 4. the frequency of the internal clock (i ) becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1 when pll circuit 1 is on. ? do not set the internal clock freque ncy lower than the ckio pin frequency. ? depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 mhz products: 24 mhz to 100 mhz 160 mhz products: 24 mhz to 160 mhz
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 266 of 1036 rej09b0254-0600 5. bus clock (b ) frequency: ? depending on the product, the clock ratio should be set to produce a frequency within one of the ranges indicated below. 100 mhz products: 24 mhz to 50 mhz 160 mhz products: 24 mhz to 66.64 mhz 6. the frequency of the peripheral clock (p ) becomes: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 2. ? for all products, the peripheral clock frequency (p ) should be set within the frequency range 6 mhz to 33.34 mhz and no higher than the frequency of the ckio pin. ? the peripheral clock frequency (p ) should be set to 13 mhz or higher if the usb function module is used. 7. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. 8. 1, 2, 3, 4, or 6 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, 1/ 3, and 1/4 can be selected as the division ratio of divider 1. 1, 1/2, 1/ 3, 1/4, and 1/6 can be selected as the division ratio of divider 2. set the rate in the frequency control register. the on/off state of pll circuit 2 is determined by the mode.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 267 of 1036 rej09b0254-0600 10.4 register descriptions 10.4.1 frequency cont rol register (frqcr) the frequency control register (frqcr) is a 16-bit read/write register that specify the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on the frqcr re gister. frqcr is initialized to h'0102 by a power-on reset, but retains its value in a manual reset and in standby mode. bit: 15 14 13 12 11 10 9 8 stc2 ifc2 pfc2 ? ? ? ? ? initial value: 0 0 0 0 0 0 0 1 r/w: r/w r/w r/w r r r r r bit: 7 6 5 4 3 2 1 0 ? ? stc1 stc0 ifc1 ifc0 pfc1 pfc0 initial value: 0 0 0 0 0 0 1 0 r/w: r r r/w r/w r/w r/w r/w r/w bits 15, 5 and 4?frequency multiplic ation ratio (stc2, stc1, stc0): these bits specify the frequency multiplication ratio of pll circuit 1. bit 15: stc2 bit 5: stc1 bit 4: stc0 description 0 0 0 1 (initial value) 0 0 1 2 1 0 0 3 0 1 0 4 1 0 1 6 values other than above reserved (illegal setting) note: do not set the output frequency of pll ci rcuit 1 higher than the maximum frequency of the cpu specified in ac characteristics.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 268 of 1036 rej09b0254-0600 bits 14, 3 and 2?internal clock frequency division ratio (ifc2, ifc1, ifc0): these bits specify the frequency division ratio of the internal clock with respect to the output frequency of pll circuit 1. bit 14: ifc2 bit 3: ifc1 bit 2: ifc0 description 0 0 0 1 (initial value) 0 0 1 1/2 1 0 0 1/3 0 1 0 1/4 values other than above reserved (illegal setting) note: do not set the internal clock frequency lower than the ckio frequency. bits 13, 1 and 0?peripheral clock frequency division ratio (pfc2, pfc1, pfc0): these bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of pll circuit 1 or the frequency of the ckio pin. bit 13: pfc2 bit 1: pfc1 bit 0: pfc0 description 0 0 0 1 0 0 1 1/2 1 0 0 1/3 0 1 0 1/4 1 0 1 1/6 (initial value) values other than above reserved (illegal setting) note: do not set the peripheral clock frequency higher than the frequency of the ckio pin. bits 12 to 9, 7 and 6?reserved: these bits are always read as 0. the write value should always be 0. bit 8?reserved: this bit is always read as 1. the write value should always be 1.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 269 of 1036 rej09b0254-0600 10.4.2 ckio2 control register (ckio2cr) ckio2cr controls ckio2 pin output. upper 8 bits: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r lower 8 bits: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ckio2en initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bits 15 to 1?reserved: these bits always read 0. the write value should always be 0. bit 0?ckio2 (ckio2en): selects output or not output (hi-z) for ckio2 clock. bit 0: ckio2en description 0 output (initial value) 1 not output (hi-z)
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 270 of 1036 rej09b0254-0600 10.5 changing the frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of dividers 1 and 2. all of these are controlled by software through the frequency control register. the methods are described below. 10.5.1 changing the multiplication rate a pll settling time is required when the multiplica tion rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: wtcsr register tme bit = 0: wdt stops wtcsr register cks2 to cks0 bits: division ratio of wdt count clock wtcnt counter: initial counter value 3. set the desired value in the stc2, stc1 and stc0 bits. the division ratio can also be set in the ifc2 to ifc0 bits and pfc2 to pfc0 bits. 4. the processor pauses internally and the wdt st arts incrementing. in clock modes 0 to 2 and 7, the internal and peripheral clocks both stop. 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. 10.5.2 changing the division ratio the wdt will not count unless the multiplication rate is changed simultaneously. 1. in the initial state, ifc2 to ifc0 = 000 and pfc2 to pfc0 = 010. 2. set the ifc2, ifc1, ifc0, pfc2, pfc1, and pfc0 bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication rate of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 271 of 1036 rej09b0254-0600 10.6 overview of the wdt 10.6.1 block diagram of the wdt figure 10.2 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock internal bus standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: watchdog timer control/status register watchdog timer counter legend: figure 10.2 block diagram of the wdt
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 272 of 1036 rej09b0254-0600 10.6.2 register configurations the wdt has two registers that select the clock, switch the timer mode, and perform other functions. table 10.5 shows the wdt register. table 10.5 register configuration name abbreviation r/w initia l value address access size watchdog timer counter wtcnt r/w * h'00 h'ffffff84 r: 8; w: 16 * watchdog timer control/ status register wtcsr r/w * h'00 h'ffffff86 r: 8; w: 16 * note: * write with a word access. write h'5a and h'a5, respectively, in the upper bytes. byte or longword writes are not possible. read with a byte access. 10.7 wdt registers 10.7.1 watchdog ti mer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit read/write counter that increments on the selected clock. the wtcnt differs from other registers in that it is more difficult to write to. see section 10.7.3, notes on register access, for details. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in in terval time mode. its a ddress is h'ffffff84. the wtcnt counter is initialized to h'00 by a power-on reset through the resetp pin. use a word access to write to the wtcnt counter, with h'5a in the upper byte. use a byte access to read wtcnt. bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 273 of 1036 rej09b0254-0600 10.7.2 watchdog timer contro l/status register (wtcsr) the watchdog timer control/status register (wtcsr) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. the wtcsr differs from other registers in that it is more difficult to write to. see section 10.7.3, notes on register access, for details. its ad dress is h'ffffff86. th e wtcsr register is initialized to h'00 only by a power-on reset through the resetp pin. when a wdt overflow causes an internal reset, the wtcsr retains its value. when used to count the clock settling time for canceling a standby, it retains its value afte r counter overflow. use a word access to write to the wtcsr counter, with h'a5 in the uppe r byte. use a byte access to read wtcsr. bit: 7 6 5 4 3 2 1 0 tme wt/ it rsts wovf iovf cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 7?timer enable (tme): starts and stops timer operation. clear this bit to 0 when using the wdt in standby mode or when changing the clock frequency. bit 7: tme description 0 timer disabled: count-up stops and wtcnt value is retained (initial value) 1 timer enabled bit 6?timer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or an interval timer. bit 6: wt/ it description 0 use as interval timer (initial value) 1 use as watchdog timer note: if wt/ it is modified when the wdt is running, the up-count may not be performed correctly. bit 5?reset select (rsts): selects the type of reset when the wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. bit 5: rsts description 0 power-on reset (initial value) 1 manual reset
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 274 of 1036 rej09b0254-0600 bit 4?watchdog timer overflow (wovf): indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. bit 4: wovf description 0 no overflow (initial value) 1 wtcnt has overflowed in watchdog timer mode bit 3?interval timer overflow (iovf): indicates that the wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. bit 3: iovf description 0 no overflow (initial value) 1 wtcnt has overflowed in interval timer mode bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overflow period in the table is the value when the peripheral clock (p ) is 15 mhz. bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period (when p = 15 mhz) 0 0 0 1 (initial value) 17 s 1 1/4 68 s 1 0 1/16 273 s 1 1/32 546 s 1 0 0 1/64 1.09 ms 1 1/256 4.36 ms 1 0 1/1024 17.48 ms 1 1/4096 69.91 ms note: if bits cks2 to cks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 275 of 1036 rej09b0254-0600 10.7.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers is given below. writing to wtcnt and wtcsr: these registers must be wr itten by a word transfer instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 10.3. when writing to wtcsr, set the upper byte to h'a5 and transf er the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. 15 8 7 0 h'5a write data address: h'ffffff84 wtcnt write 15 8 7 0 h'a5 write data address: h'ffffff86 wtcsr write figure 10.3 writing to wtcnt and wtcsr 10.8 using the wdt 10.8.1 cancelin g standby mode the wdt can be used to cancel standby mode with an nmi or other interrupts. the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the resetp pin low until the clock stabilizes.) 1. before transitioning to standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 276 of 1036 rej09b0254-0600 3. move to standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecting the ed ge change of the nmi signal or detecting interrupts. 5. when the wdt count overflows, the cpg st arts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. since the wdt continues counting from h?00, set the stby bit in the stbcr register to 0 in the interrupt processing program and this will stop the wdt. when the stby bit remains 1, the SH7727 again enters the st andby mode when the wdt has counted up to h?80. this standby mode can be canceled by power-on resets. 10.8.2 changing the frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequenc y, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits of wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written, the clock stops and the processor enters standby mode temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg re sumes supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. the counter stops at the values h'00 to h'01. the stop value depends on the clock ratio. 10.8.3 using watchdog timer mode 1. set the wt/ it bit in the wtcsr register to 1, set the re set type in the rsts bit, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts bit. the counter then resumes counting.
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 277 of 1036 rej09b0254-0600 10.8.4 using interval timer mode when operating in interval timer mode, interval tim er interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in the wtcsr register to 0, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets th e iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to intc. the counter then resumes counting. 10.9 notes on board design when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistor r close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. xtal extal SH7727 r cl2 cl1 avoid crossing signal lines figure 10.4 points for attent ion when using crystal resonator
section 10 on-chip oscillation circuits rev.6.00 mar. 27, 2009 page 278 of 1036 rej09b0254-0600 decoupling ca pacitors: insert a laminated ceramic capacitor of 0.01 to 0.1 f as a passive capacitor for each v ss /v cc pair. mount the passive capacitors to the sh3 power supply pins, and use components with a frequency characteristic suitable for the sh3 operating frequency, as well as a suitable capacitance value. digital system v ss /v cc pairs: 35-37, 91-93, 137-139, 155-157, 177-178, 200-202 digital system v ss q/v cc q pairs: 18-20, 29-31, 42-44, 53-55, 64-66, 75-77, 86-88, 100-102, 115- 117, 132-134, 159-161, 188-190, 207-209 on-chip oscillator v ss /v cc pairs: 1-4 when using a pll oscillator circuit: keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. ground the oscillation stabilization cap acitors c1 and c2 to v ss (pll1) and v ss (pll2), respectively. place c1 and c2 clos e to the cap1 and cap2 pins and do not locate a wiring pattern in the vicinity. in clock mode 7, connect the extal pin to v cc q or v ss q and leave the xtal pin open. cap2 v cc (pll2) v cc (pll1) v cc c1 = 470 pf c2 = 470 pf v ss cap1 v ss (pll2) v ss (pll1) avoid crossing signal lines power supply reference values c2 c1 figure 10.5 points for attentio n when using pll oscillator circuit notes on using pins ckio and ckio2 as the clock outputs: perform board design so that the sum of pin capacitances of the cpu and socket th at are connected to pins are 50 pf or less.
section 11 extend clock pulse generator for usb (excpg) rev.6.00 mar. 27, 2009 page 279 of 1036 rej09b0254-0600 section 11 extend cloc k pulse generator for usb (excpg) 11.1 overview 11.1.1 excpg the SH7727 has an on-chip usb interface (usb) which requires a fixed 48-mhz clock source. the extend clock pulse generator (excpg) generates a divided clock from the internal clock (i ), the bus clock (b ), or the external clock (uclk). because the clock sources, which can be a candidate to be used by excpg, vary from cpg setting or external clock source, user of SH7727 must adjust the divided clock, carefully to be 48 mhz. 11.2 functions 11.2.1 block diagram figure 11.1 shows a block diagram of the excpg. 1/1 select usb clock (48 mhz) 1/2 1/3 usb host usb function peripheral clock (p ) internal clock (i ) bus clock (b ) external clock (uclk) figure 11.1 block diagram of excpg
section 11 extend clock pulse generator for usb (excpg) rev.6.00 mar. 27, 2009 page 280 of 1036 rej09b0254-0600 11.2.2 pin configuration table 11.1 shows a pin configuration of the excpg. table 11.1 pin configuration pin name abbreviation i/o description external clock pin uclk input usb clock input pin (48-mhz input) note: uclk is multiplexed with ptd6. 11.2.3 register configuration the excpg has the internal registers shown in table 11.2. table 11.2 register configuration name abbreviation r/w initial value address access size excpg control register excpgcr w h?00 h'a4000236 8 11.3 register descriptions 11.3.1 excpg control register (excpgcr) the excpg control register (excpgcr) select s the source clock and division ratio for generation of the excpg clock. excpgr is initialized to h' 00 by a power-on reset. bit: 7 6 5 4 3 2 1 0 ? ? usbcks el2 usbcks el1 usbcks el0 usbdivs el2 usbdivs el1 usbdivs el0 initial value: 0 0 0 0 0 0 0 0 r/w: r r w w w w w w bits 7 and 6?reserved: these bits are always read as 0. the write value should always be 0.
section 11 extend clock pulse generator for usb (excpg) rev.6.00 mar. 27, 2009 page 281 of 1036 rej09b0254-0600 bits 5 to 3?clock select (usbcksel2 to usbcksel0): selects the clock source. although initialized as peripheral clock (p ) after power on reset, the value of usbcksel must be changed to adequate value to generate 48 mhz. to prevent malfunction, the usb host and usb function must be set in module standby state or module reset state when the value of usbcksel is changed. bits 5 to 3 function (clock selection) 000 peripheral clock (p ) (initial value) 100 internal clock (i ) 101 bus clock (b ) 110 external clock (uclk) another value reserved (setting prohibited) bits 2 to 0?divider select (usbdivsel2 to usbdivsel0): selects the dividing ratio of clock source to generate usb clock so that the usb clock is 48 mhz. bits 2 to 0 function (dividing ratio selection) 000 1/1 (initial value) 001 1/2 010 1/3 1 ** internal clock (i ), bus clock (b ), external clock (uclk) halted note: to reduce power consumption, set usbdivsel2 to 1 and halts internal clock (i ), bus clock (b ), or external cl ock (uclk) input. 11.4 usage notes by selecting lclk (lcd clock)/uclk (usb clock) as the function of the lclk/uclk/ptd[6] pin, it is possible to supply the clock input to the pin to both the lcd controller and the usb function controller. however, in this case it is necessary, using the divider select bit (usbdivsel[2:0]) in excpgcr (excpg control register), to set the us b clock so that the final clock frequency is 48 mhz. this means that the input clock frequenc y will be 48 mhz. if this frequency is not suitable as the operating clock for the lcd controlle r, consider selecting an internal clock for lclk. in addition, it may be impossible to maintain the accuracy of the usb standard clock because the cpu clock (i ) and bus clock (b ) are generated by the internal pll of the SH7727 by frequency multiplication. therefore, it is re commended that a dedicated 48 mhz external clock be input to uclk to ensure the acc uracy of the usb standard clock.
section 11 extend clock pulse generator for usb (excpg) rev.6.00 mar. 27, 2009 page 282 of 1036 rej09b0254-0600
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 283 of 1036 rej09b0254-0600 section 12 bus state controller (bsc) 12.1 overview the bus state controller (bsc) divides physical address space and output control signals for various types of memory and bus interface specifi cations. bsc functions enable this lsi to link directly with synchronous dram, sram, rom, and other memory storage devices without an external circuit. the bsc also allows direct connection to pcmcia interfaces, simplifying system design and allowing high-speed data transfers in a compact system. 12.1.1 features the bsc has the following features: ? physical address space is divided into six areas ? a maximum 64 mbytes for each of the six areas, 0, 2 to 6 ? area bus width can be selected by regi ster (area 0 is set by external pin) ? wait states can be inserted using the wait pin ? wait state insertion can be controlled through software. register settings can be used to specify the insertion of 1?10 cycles independently for each area (1?38 cycles for areas 5 and 6 and the pcmcia interface only) ? the type of memory connected ca n be specified for each area, and ? control signals are output for direct memory connection ? wait cycles are automatically inserted to av oid data bus conflict for continuous memory accesses to different areas or writes dir ectly following reads of the same area ? direct interface to synchronous dram (except if clock ratio i :b = 1:1) ? multiplexes row/column addresses accordi ng to synchronous dram capacity ? supports burst operation ? has both auto-refresh and self-refresh functions ? controls timing of synchronous dram direct-connection control signals according to register setting ? burst rom interface ? insertion of wait states controllable through software ? register setting control of burst transfers ? pcmcia direct-connection interface* ? insertion of wait states controllable through software ? bus sizing function for i/o bus width (only in the little endian mode)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 284 of 1036 rej09b0254-0600 ? refresh function ? refresh cycles will be automatically maintained in the sleep mode even after the external bus frequency is reduced to 1/4 of its normal operating frequency ? the refresh counter can be used as an interval timer ? outputs an interrupt request signal using the compare-matching function ? outputs an interrupt request signal when the refresh counter overflows ? automatically disables the output of clock signals to anywhere but the refresh counter, except during execution of external bus cycles note: * pcmcia direct interface supported by the bsc is only signals and bus protocols shown in table 12.5. for details on other control signals, refer to section 30, pc card controller (pcc) (external circuit and this lsi on-chip card controller. in this bsi, both areas 5 and 6 has pcmicia direct interface function common to the sh3 series. the on-chip pc card controller supports only area 6.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 285 of 1036 rej09b0254-0600 12.1.2 block diagram figure 12.1 shows the functional block diagram of the bsc. cs0 cs6 to cs2 ce2a to ce2b bs rd rd/ wr we3 to we0 ras cas cke iciord , iciowr iois16 internal bus bus interface wcr1 wcr2 bcr1 bcr2 mcr pcr rfcr rtcnt rtcor rtcsr comparator refresh controller memory controller area controller wait controller mode selection interrupt controller bsc peripheral bus module bus mr2 wait md5 to md3 legend: wcr: wait state contol register rfcr: refresh count register bcr: bus control register rtcnt: refresh timer count register mcr: memory control register rtcor: refresh time constant register pcr: pcmcis control register rtcsr: refresh timer control/status register figure 12.1 corresponding to logical address space and physical address space
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 286 of 1036 rej09b0254-0600 12.1.3 pin configuration table 12.1 lists the bsc pin configuration. table 12.1 pin configuration pin name signal i/o description address bus a25?a0 output address output data bus d15?d0 i/o data i/o d31?d16 i/o when 32-bit bus width, data i/o bus cycle start bs output shows start of bus cycle. during burst transfers, asserts every data cycle. chip select 0, 2?4 cs0 , cs2 ? cs4 output chip select signal to indicate area being accessed. chip select 5, 6 cs5 / ce1a , cs6 / ce1b output chip select signal to indicate area being accessed. cs5 / ce1a and cs6 / ce1b can also be used as ce1a and ce1b of pcmcia. pcmcia card select ce2a , ce2b output when pcmcia is used, ce2a and ce2b read/write rd/ wr output data bus direction indicator signal. pcmcia write indicator signal. row address strobe ras output when synchronous dram is used, ras signal. column address strobe cas output when synchronous dram is used, cas signal. data enable 0 we0 /dqmll output when memory other than synchronous dram is used, selects d7 to d0 write strobe signal. when synchronous dram is used, selects d7 to d0. data enable 1 we1 /dqmlu/ we output when memory other than synchronous dram and pcmcia is used, selects d15 to d8 write strobe signal. when synchronous dram is used, selects d15 to d8. when pcmcia is used, strobe signal that indicates the write cycle. data enable 2 we2 /dqmul/ iciord output when memory other than synchronous dram and pcmcia is used, selects d23 to d16 write strobe signal. when synchronous dram is used, selects d23 to d16. when pcmcia is used, strobe signal indicating i/o read.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 287 of 1036 rej09b0254-0600 pin name signal i/o description data enable 3 we3 /dqmuu/ iciowr output when memory other than synchronous dram and pcmcia is used, selects d31 to d24 write strobe signal. when synchronous dram is used, selects d31 to d24. when pcmcia is used, strobe signal indicating i/o write. read rd output strobe signal indicating read cycle wait wait input wait state request signal clock enable cke output clock enable control signal of synchronous dram iois16 iois16 input signal indicating pcmcia 16-bit i/o. valid only in little-endian mode. bus release request breq input bus release request signal bus release acknowledgment back output bus release acknowledge signal mode selection md5 to md3 input specifies bus widt h and endian of area 0 12.1.4 register configuration the bsc has 11 registers (table 12.2). the synchronous dram also has a built-in synchronous dram mode register. these registers control dir ect connection interfaces to memory, wait states, and refreshes.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 288 of 1036 rej09b0254-0600 table 12.2 register configuration name abbr. r/w initial value * address bus width bus control register 1 bcr1 r/w h'0000 h'ffffff60 16 bus control register 2 bcr2 r/w h'3ff0 h'ffffff62 16 wait state control register 1 wcr1 r/w h'3ff3 h'ffffff64 16 wait state control register 2 wcr2 r/w h'ffff h'ffffff66 16 individual memory control register mcr r/w h'0000 h'ffffff68 16 pcmcia control register pcr r/w h'0000 h'ffffff6c 16 refresh timer control/status register rtcsr r/w h'0000 h'ffffff6e 16 refresh timer counter rt cnt r/w h'0000 h'ffffff70 16 refresh time constant regist er rtcor r/w h'0000 h'ffffff72 16 refresh count register rfcr r/w h'0000 h'ffffff74 16 synchronous dram mode register for area 2 sdmr w ? h'ffffd000? h'ffffdfff 8 for area 3 h'ffffe000? h'ffffefff notes: for details, see section 12.2.7, synchronous dram mode register (sdmr). * initialized by power-on resets. 12.1.5 area overview space allocation: in the architecture of this lsi, both logical spaces and physical spaces have 32- bit address spaces. the logical space is divided into five areas by the value of the upper bits of the address. the physical space is divided into eight areas. logical space can be allocated at physical spaces using a memory management unit (mmu). for details, refer to section 3, memory management unit (mmu), which desc ribes area allocation for physical spaces. as listed in table 12.3, this lsi can be conn ected directly to six areas of memory/pc card interface, and it outputs chip select signals ( cs0 , cs2 to cs6 , ce2a , ce2b ) for each of them. cs0 is asserted during area 0 access; cs6 is asserted during area 6 access. when pcmcia interface is selected in area 5 or 6, in addition to cs5 / cs6 , ce2a / ce2b are asserted for the corresponding bytes accessed.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 289 of 1036 rej09b0254-0600 area 0 (cs0) internal i/o area 2 (cs2) area 3 (cs3) area 4 (cs4) area 5 (cs5) area 6 (cs6) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 h'00000000 h'04000000 h'08000000 h'0c000000 h'10000000 h'14000000 h'18000000 reserved area physical address space logical address space p0, u0 p1 p2 p3 p4 note: for logical address spaces p0 and p3, when the memory management unit (mmu) is on, it can optionally generate a physical address for the logical address. it can be applied when the mmu is off and when the mmu is on and each physical address for the logical address is equal except for upper three bits. when translating logical addresses to arbitrary physical addresses, refer to table 12.3 "physical address space map". figure 12.2 corresponding to logical address space and physical address space
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 290 of 1036 rej09b0254-0600 table 12.3 physical address space map area connectable memory physical address (a28 to a0) capacity access size 0 h'00000000 to h'03ffffff 64 mbytes 8, 16, 32 * 2 ordinary memory * 1 , burst rom h'00000000 + h'2000000 x n to h'03ffffff + h'2000000 x n shadow (n = 1 to 6) 1 internal i/o registers * 7 h'04000000 to h'07ffffff 64 mbytes 8, 16, 32 * 3 h'04000000 + h'2000000 x n to h'07ffffff + h'2000000 x n shadow (n = 1 to 6) h'08000000 to h'0bffffff 64 mbyte 8, 16, 32 * 3 * 4 2 ordinary memory * 1 , synchronous dram h'08000000 + h'2000000 x n to h'0bffffff + h'2000000 x n shadow (n = 1 to 6) 3 h'0c000000 to h'0fffffff 64 mbytes 8, 16, 32 * 3 * 4 ordinary memory, synchronous dram h'0c000000 + h'2000000 x n to h'0fffffff + h'2000000 x n shadow (n = 1 to 6) 4 ordinary memory h'10000000 to h'13ffffff 64 mbytes 8, 16, 32 * 3 h'10000000 + h'2000000 x n to h'13ffffff + h'2000000 x n shadow (n = 1 to 6) 5 h'14000000 to h'15ffffff 32 mbytes ordinary memory, pcmcia, burst rom h'16000000 to h'17ffffff 32 mbytes 8, 16, 32 * 3 * 5 h'16000000 + h'2000000 x n to h'17ffffff + h'2000000 x n shadow (n = 1 to 6) 6 h'18000000 to h'19ffffff 32 mbytes h'1a000000 to h'1bffffff 32 mbytes 8, 16, 32 * 3 * 5 ordinary memory, pcmcia, bust rom h'1a000000 + h'2000000 x n to h'1bffffff + h'2000000 x n shadow (n = 1 to 6) 7 * 6 reserved area h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n n = 0?7 notes: 1. memory wi th interface such as sram or rom. 2. use external pin to specify memory bus width. 3. use register to specify memory bus width. 4. with synchronous dram interfaces, bus width must be 16 or 32 bits. 5. with pcmcia interface, bus width must be 8 or 16 bits. 6. the access to reserved area is prohibited. 7. when the control register in area 1 is not used for address translation by the mmu, set the top three bits of the logical address to 101 to allocate in the p2 space.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 291 of 1036 rej09b0254-0600 area 0: h'00000000 area 1: h'04000000 area 2: h'08000000 a rea 3: h'0c000000 area 4: h'10000000 area 5: h'14000000 the pcmcia interface is shared by the memory and i/o card the pcmcia interface is shared by the memory and i/o card area 6: h'18000000 ordinary memory/ burst rom internal i/o ordinary memory/ synchronous dram ordinary memory/ synchronous dram ordinary memory ordinary memory/ burst rom/pcmcia ordinary memory/ burst rom/pcmcia figure 12.3 physical space allocation memory bus width: the memory bus width in this lsi can be set for each area. in area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset as setting of md4 and md3 as below table . table 12.4 correspondence be tween external pins (md4 and md3) and memory bus width in area0 md4 md3 memory size 0 0 reserved (setting prohibited) 1 8 bits 1 0 16 bits 1 32 bits for areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control register 2 (bcr2) whenever ordinary memory, rom, or burst rom are used. when the pcmcia interface is used, set the bus width to byte or word. when synchronous dram is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. when using the port function, set each of the bus widths to byte or word for all areas. for more information, see section 12.2.2, bus control register 2 (bcr2).
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 292 of 1036 rej09b0254-0600 shadow space: areas 0, 2 to 6 are decoded by physical addresses a28 to a26, which correspond to areas 000 to 110. address bits 31 to 29 ar e ignored. this means that the range of area 0 addresses, for example, is h' 00000000 to h'03ffffff, and its corresponding shadow space is the address space obtained by adding to it h'20000000 n (n = 1 to 6). the address range for area 7, which is on-chip i/o space, is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. 12.1.6 pc card support the bus controller of this lsi supports protocol signals of pcmcia standard interface specifications in physical space areas 5 and 6 as another sh3 series. pc card bus signal (ceia,ce2a,ce1b,ce2b,iois16) are supported for pc card bus protocol as same as sh7708/sh7709/sh7729 series. dynamic bus sizing of i/o bus width is supported only in the little endian made. table 12.5 SH7727 and pcmcia pins SH7727 pcmcia ce1a ce1 ce1b ce1 ce2a ce2 ce2b ce2 we we / pgm rd oe iois16 wp / iois16 iciord iord iciowr iowr a25?a0 a25?a0 d15?d0 d15?d0
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 293 of 1036 rej09b0254-0600 12.2 bsc registers 12.2.1 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or by standby mode. do not access extern al memory outside area 0 until bcr1 register initialization is complete. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pula puld hiz mem hiz cnt endi an a0 bst1 a0 bst0 a5 bst1 a5 bst0 a6 bst1 a6 bst0 dram tp2 dram tp1 dram tp0 a5 pcm a6 pcm initial value: 0 0 0 0 0/1 * 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * samples the value of the external pin (md5) designating endian at power-on reset. bit 15?pins a25 to a0 pull-up (pula): specifies whether or not pins a25 to a0 are pulled up for 4 cycles immediately after back is asserted. bit 15: pula description 0 not pulled up (initial value) 1 pulled up bit 14?pins d31 to d0 pull-up (puld): specifies whether or not pins d31 to d0 are pulled up when not in use. bit 14: puld description 0 not pulled up (initial value) 1 pulled up bit 13?hi-z memory control (hizmem): specifies the state of a25 to a0, bs , cs , rd/ wr , we /dqm, rd , ce2a , ce2b and drak0 in standby mode. bit 13: hizmem description 0 high-impedance state in standby mode. (initial value) 1 high in standby mode.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 294 of 1036 rej09b0254-0600 bit 12?high-z control (hizcnt): specifies the state of the ras and the cas signals at standby and bus right release. bit 12: hizcnt description 0 the ras and the cas signals are high-impedance state (high-z) at standby and bus right release. (initial value) 1 the ras and the cas signals are driven at standby and bus right release. bit 11?endian flag (endian): samples the value of the external pin designating endian upon a power-on reset. endian for all physical spaces is decided by this bit, which is read-only. bit 11: endian description 0 (on reset) endian setting external pin (md5) is low. indicates this lsi is set as big endian. 1 (on reset) endian setting external pin (md 5) is high. indicates this lsi is set as little endian. bits 10 and 9?area 0 burst rom control (a0bst1, a0bst0): specify whether to use burst rom in physical space area 0. wh en burst rom is used, set the number of burst transfers. bit 10: a0bst1 bit 9: a0bst0 description 0 0 access area 0 as ordinary memory (initial value) 1 access area 0 as burst rom (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 access area 0 as burst rom (8 consecutive accesses). can be used when bus width is 8 or 16. 1 access area 0 as burst rom (16 consecutive accesses). can be used only when bus width is 8.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 295 of 1036 rej09b0254-0600 bits 8 and 7?area 5 burst enable (a5bst1, a5bst0): specify whether to use burst rom and pcmcia burst mode in physical space area 5. when burst rom and pcmcia burst mode are used, set the number of burst transfers. bit 8: a5bst1 bit 7: a5bst0 description 0 0 access area 5 as ordinary memory (initial value) 1 burst access of area 5 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 5 (8 consecutive accesses). can be used when bus width is 8 or 16. 1 burst access of area 5 (16 consecutive accesses). can be used only when bus width is 8. bits 6 and 5?area 6 burst enable (a6bst1, a6bst0): specify whether to use burst rom and pcmcia burst mode in physical space area 6. when burst rom and pcmcia burst mode are used, set the number of burst transfers. bit 6: a6bst1 bit 5: a6bst0 description 0 0 access area 6 as ordinary memory (initial value) 1 burst access of area 6 (4 consecutive accesses). can be used when bus width is 8, 16, or 32. 1 0 burst access of area 6 (8 consecutive accesses). can be used when bus width is 8 or 16. 1 burst access of area 6 (16 consecutive accesses). can be used only when bus width is 8.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 296 of 1036 rej09b0254-0600 bits 4 to 2?area 2, area 3 memory type (dramtp2, dramtp1, dramtp0): designate the types of memory connected to physical space areas 2 and 3. ordinary memory, such as rom, sram, or flash rom, can be directly connected. synchronous dram can also be directly connected. bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 0 0 0 areas 2 and 3 are ordinary memory (initial value) 1 reserved (setting disabled) 1 0 area 2: ordinary memory; area 3: synchronous dram * 1 1 areas 2 and 3 are synchronous dram * 1 * 2 1 0 0 reserved (setting disabled) 1 reserved (setting disabled) 1 0 reserved (setting disabled) 1 reserved (setting disabled) notes: 1. when selecting this mode, set the same bus width for area 2 and area 3. 2. if clock rate is specified as 1 : bus clock = 1:1 , synchronous dram cannot be accessed. bit 1?area 5 bus type (a5pcm): designates whether to access physical space area 5 as pcmcia space. bit 1: a5pcm description 0 access physical space area 5 as ordinary memory (initial value) 1 access physical space area 5 as pcmcia space bit 0?area 6 bus type (a6pcm): designates whether to access physical space area 6 as pcmcia space. bit 0: a6pcm description 0 access physical space area 6 as ordinary memory (initial value) 1 access physical space area 6 as pcmcia space
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 297 of 1036 rej09b0254-0600 12.2.2 bus control register 2 (bcr2) the bus control register 2 (bcr2) is a 16-bit read/w rite register that sel ects the bus-size width of each area. it is initialized to h'3 ff0 by a power-on reset, but is not initialized by a manual reset or by standby mode. do not access external memory outside area 0 until bcr2 register initialization is complete. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? a6 sz1 a6 sz0 a5 sz1 a5 sz0 a4 sz1 a4 sz0 a3 sz1 a3 sz0 a2 sz1 a2 sz0 ? ? ? ? initial value: 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r bits 15, 14, 3, 2, 1, and 0?reserved: these bits are always read as 0. the write value should always be 0. bits 2n + 1, 2n?area n (2 to 6) bus size specification (ansz1, ansz0): specify the bus sizes of physical space area n (n = 2 to 6). bit 2n + 1: ansz1 bit 2n: ansz0 port a / b description 0 0 unused reserved (setting disabled) 1 byte (8-bit) size 1 0 word (16-bit) size 1 longword (32-bit) size 0 0 used reserved (setting disabled) 1 byte (8-bit) size 1 0 word (16-bit) size 1 reserved (setting disabled)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 298 of 1036 rej09b0254-0600 12.2.3 wait state control register 1 (wcr1) wait state control register 1 (wcr1) is a 16-bit read /write register that sp ecifies the number of idle (wait) state cycles inserted for each area. for some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. this can result in conflicts between data buses wh en consecutive memory acce sses are to different memories or when a write immediately follows a memory read. this lsi automatically inserts idle states equal to the number set in wcr1 in those cases. wcr1 is initialized to h'3ff3 by a power-on rese t. it is not initialized by a manual reset or by standby mode. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wait sel ? a6 iw1 a6 iw0 a5 iw1 a5 iw0 a4 iw1 a4 iw0 a3 iw1 a3 iw0 a2 iw1 a2 iw0 ? ? a0 iw1 a0 iw0 initial value: 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 r/w: r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r/w r/w bit 15?wait sampling timing select (waitsel): specifies the wait signal sampling timing. bit 15: waitsel description 0 set to 1 when wait signal is used. * (initial value) 1 sampled at the falling edge of ckio. note: * if low level is input to the wait by setting the waitsel bit, the lsi operation cannot be guaranteed. bits 14, 3, and 2 ?reserved: these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 299 of 1036 rej09b0254-0600 bits 2n + 1, 2n?area n (6 to 2, 0) intercycle idle specification (aniw1, aniw0): specify the number of idles inserted between bus cycles when switching between physical space area n (6 to 2, 0) to another space or between a read access to a write access in the same physical space. bit 2n + 1: aniw1 bit 2n: aniw0 description 0 0 1 idle cycle inserted 1 1 idle cycle inserted 1 0 2 idle cycles inserted 1 3 idle cycles inserted (initial value) 12.2.4 wait state control register 2 (wcr2) wait state control register 2 (wcr2) is a 16-bit read /write register that sp ecifies the number of wait state cycles inserted for each area. it also sp ecifies the pitch of data access for burst memory accesses. this allows direct connection of even lo w-speed memories without an external circuit. wcr2 is initialized to h'ffff by a power-on reset. it is not initialized by a manual reset or by standby mode. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a6 w2 a6 w1 a6 w0 a5 w2 a5 w1 a5 w0 a4 w2 a4 w1 a4 w0 a3 w1 a3 w0 a2 w1 a2 w0 a0 w2 a0 w1 a0 w0 initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 300 of 1036 rej09b0254-0600 bits 15 to 13?area 6 wait control (a6w2, a6w1, a6w0): specify the number of wait states inserted into physical space area 6. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 15: a6w2 bit 14: a6w1 bit 13: a6w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 disable 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 1 10 (initial value) enable 10 enable bits 12 to 10?area 5 wait control (a5w2, a5w1, a5w0): specify the number of wait states inserted into physical space area 5. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 12: a5w2 bit 11: a5w1 bit 10: a5w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 disable 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 1 10 (initial value) enable 10 enable
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 301 of 1036 rej09b0254-0600 bits 9 to 7?area 4 wait control (a4w2, a4w1, a4w0): specify the number of wait states inserted into physical space area 4. description bit 9: a4w2 bit 8: a4w1 bit 7: a4w0 inserted wait state wait pin 0 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable 1 0 0 4 enable 1 6 enable 1 0 8 enable 1 10 enable (initial value) bits 6 and 5?area 3 wait control (a3w1, a3w0): specify the number of wait states inserted into physical space area 3. ? for ordinary memory description bit 6: a3w1 bit 5: a3w0 inserted wait states wait pin 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable (initial value) ? for synchronous sdram description bit 6: a3w1 bit 5: a3w0 synchronous sdram: cas latency 0 0 1 1 1 1 0 2 1 3 (initial value)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 302 of 1036 rej09b0254-0600 bits 4 and 3?area 2 wait control (a2w1, a2w0): specify the number of wait states inserted into physical space area 2. ? for ordinary memory description bit 4: a2w0 bit 3: a2w0 inserted wait states wait pin 0 0 0 ignored 1 1 enable 1 0 2 enable 1 3 enable (initial value) ? for synchronous sdram description bit 4: a2w1 bit 3: a2w0 synchronous dram: cas latency 0 0 1 1 1 1 0 2 1 3 (initial value) bits 2 to 0?area 0 wait control (a0w2, a0w1, a0w0): specify the number of wait states inserted into physical space area 0. also specify the burst pitch for burst transfer. description first cycle burst cycle (excluding first cycle) bit 2: a0w2 bit 1: a0w1 bit 0: a0w0 inserted wait states wait pin number of states per data transfer wait pin 0 0 0 0 ignored 2 enable 1 1 enable 2 enable 1 0 2 enable 3 enable 1 3 enable 4 enable 1 0 0 4 enable 4 enable 1 6 enable 6 enable 1 0 8 enable 8 enable 1 10 (initial value) enable 10 enable
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 303 of 1036 rej09b0254-0600 12.2.5 individual memory control register (mcr) the individual memory control register (mcr) is a 16-bit read/write register that specifies ras and cas timing and burst control for synchronous dram (areas 2 and 3), specifies address multiplexing, and controls refresh. this enables direct connection of synchronous dram without external circuits. the mcr is initialized to h'0000 by power-on re sets, but is not initialized by manual resets or standby mode. the bits tpc1 to tpc0, rcd1 to rcd0, trwl1 to trwl0, tras1 to tras0, amx3 to amx0, and are written to at the initialization after a power-on reset and are not then modified again. when rfsh and rmode are written to, write the same values to the other bits. when using synchronous dram, do not access ar eas 2 and 3 until this register is initialized. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpc1 tpc0 rcd1 rcd0 trwl 1 trwl 0 tras 1 tras 0 ? amx3 amx2 amx1 amx0 rfsh rmo de ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14?ras precharge time (tpc1, tpc0): these bits set the minimum number of cycles until output of the next bank-active command after precharge, when the synchronous dram interface is selected for external memo ry. however, the number of cycles inserted immediately after the precharge all banks (pall) command is issued when performing auto- refresh is one fewer than the number of cycles during normal operation. description bit 15: tpc1 bit 14: tpc0 normal operation immediately after precharge command * immediately after self-refresh 0 0 1 cycle (initial value) 0 cycle (initial value) 2 cycles (initial value) 1 2 cycles 1 cycle 5 cycles 1 0 3 cycles 2 cycles 8 cycles 1 4 cycles 3 cycles 11 cycles note: * immediately after the precharge all banks (pall) command is issued when performing auto-refresh.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 304 of 1036 rej09b0254-0600 bits 13 and 12?ras?cas delay (rcd1, rcd0): when synchronous dram interface is selected, sets the bank active read/write command delay time. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 11 and 10?write-precha rge delay (trwl1, trwl0): the trwl bits set the synchronous dram write-precharge delay time. th is designates the time between the end of a write cycle and the next bank-active command. this is valid only when synchronous dram is connected. after the write cycle, the next bank- active command is not issued for the period tpc + trwl. bit 11: trwl1 bit 10: trwl0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 reserved (setting disabled) bits 9 and 8? cas -before- ras refresh ras assert time (tras1, tras0): when synchronous dram interface is selected, no bank-active command is issues during the period tpc + tras after an auto-refresh command. bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 7?reserved: this bit is always read as 0. the write value should always be 0. bits 6 to 3?address multiplex (amx3 , amx2, amx1, amx0): the amx bits specify address multiplexing for synchronous dram. the actual address shift value differs between synchronous dram interface.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 305 of 1036 rej09b0254-0600 for synchronous dram inte rface: (see table 12.12) bit6: amx3 bit5: amx2 bit 4: amx1 bit 3: amx0 description 1 1 0 1 the row address begins with a10 when bus width is 16 bit. the row address begins with a11 when bus width is 32 bit. (the a10 value is output at a1 when the row address is output. 4m 16-bit 4-bank products) 1 0 the row address begins with a11 when bus width is 16 bit. (the a11 value is output at a1 when the row address is output. 8m 16-bit 4-bank products) * 1 0 1 0 0 the row address begins with a9 when bus width is 16 bit. the row address begins with a10 when bus width is 32 bit. (the a9 value is output at a1 when the row address is output. 1m 16-bit 4-bank products) 1 the row address begins with a10 when bus width is 16 bit. the row address begins with a11 when bus width is 32 bit. (the a10 value is output at a1 when the row address is output. 2m 16-bit 4-bank products) 1 0 the row address begins with a11 when bus width is 32 bit. * 2 (the a11 value is output at a1 when the row address is output. 2m 16-bit 4-bank products) 1 the row address begins with a9 when bus width is 16 bit. the row address begins with a10 when bus width is 32 bit. (the a9 value is output at a1 when the row address is output. 512k 32-bit 4-bank products) 0 0 0 reserved. amx3 to amx0 must be set to * 1 *** before accessing synchronous dram memory. (initial value) values other than above reserved (illegal setting) notes: 1. can only be set when using a 16-bit bus width. 2. can only be set when using a 32-bit bus width.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 306 of 1036 rej09b0254-0600 bit 2?refresh control (rfsh): the rfsh bit determines whether or not the refresh operation of the synchronous dram is performed. the timer for generation of the refresh request frequency can also be used as an interval timer. bit 2: rfsh description 0 no refresh (initial value) 1 refresh bit 1?refresh mode (rmode): the rmode bit selects whethe r to perform an ordinary refresh or a self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 0, a cas- before-ras refresh or an auto-refresh is performed on synchronous dram at the period set by the refresh-related registers rtcnt, rtcor and rtcsr. when a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. when the rfsh bit is 1 and this bit is also 1, the sync hronous dram will wait for the end of any executing external bus cycle before going in to a self-refresh. all refresh requests to memory that is in the self-refresh state are ignored. bit 1: rmode description 0 cas-before-ras refresh (rfsh must be 1) (initial value) 1 self-refresh (rfsh must be 1) bit 0?reserved : this bit is always read as 0. the write value should always be 0. 12.2.6 pcmcia control register (pcr) the pcmcia control register (rcr) specifies the assert/negate timing of the oe and we signals ( rd and we1 pins of this lsi) for the pcmcia interface connected to areas 5 and 6. note that the assertion widths of oe and we are set using the wait control bits of the wcr2 register. the pcr register is a 16-bit read/write register. it is initialized at a power-on reset to h'0000. however, the register is not initialized and the contents remain unchanged at a manual reset and when in standby mode. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a6 w3 a5 w3 ? ? a5 ted2 a6 ted2 a5 teh2 a6 teh2 a5 ted1 a5 ted0 a6 ted1 a6 ted0 a5 teh1 a5 teh0 a6 teh1 a6 teh0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 307 of 1036 rej09b0254-0600 bit 15?area 6 wait control (a6w3): the a6w3 bit specifies the number of inserted wait states for area 6 combined with bits a6w2 to a6 w0 in wcr2. it also sp ecifies the number of transfer states in burst tran sfer. set this bit to 0 when area 6 is not set to pcmcia. top cycle burst cycle a6w3 a6w2 a6w1 a6w0 inserted wait state wait pin number of states per one-data transfer wait pin 0 0 0 0 0 ignored 2 enabled 1 1 enabled 2 enabled 1 0 2 enabled 3 enabled 1 3 enabled 4 enabled 1 0 0 4 enabled 5 enabled 1 6 enabled 7 enabled 1 0 8 enabled 9 enabled 1 10 (initial value) enabled 11 enabled 1 0 0 0 12 enabled 13 enabled 1 14 enabled 15 enabled 1 0 18 enabled 19 enabled 1 22 enabled 23 enabled 1 0 0 26 enabled 27 enabled 1 30 enabled 31 enabled 1 0 34 enabled 35 enabled 1 38 enabled 39 enabled bit 14?area 5 wait control (a5w3): the a5w3 bit specifies th e number of inserted wait states for area 5 combined with bits a5w2 to a5 w0 in wcr2. it also sp ecifies the number of transfer states in burst tran sfer. set this bit to 0 when area 5 is not set to pcmcia. the relationship between the setting value and the number of waits is the same as a6w3. bits 13 and 12?reserved: these bits are always read as 0. the write value should always be 0.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 308 of 1036 rej09b0254-0600 bits 11, 7, and 6?area 5 address oe / we assert delay (a5ted2, a5ted1, and a5ted0): the a5ted bits specify the address to oe / we assert delay time for the pcmcia interface connected to area 5. bit 11: a5ted2 bit 7: a5ted1 bit 6: a5ted0 description 0 0 0 0.5-cycle delay (initial value) 1 1.5-cycle delay 1 0 2.5-cycle delay 1 3.5-cycle delay 1 0 0 4.5-cycle delay 1 5.5-cycle delay 1 0 6.5-cycle delay 1 7.5-cycle delay bits 10, 5 and 4?area 6 address oe / we assert delay (a6ted2, a6ted1, and a6ted0): the a6ted bits specify the address to oe / we assert delay time for the pcmcia interface connected to area 6. bit 10: a6ted2 bit 5: a6ted1 bit 4: a6ted0 description 0 0 0 0.5-cycle delay (initial value) 1 1.5-cycle delay 1 0 2.5-cycle delay 1 3.5-cycle delay 1 0 0 4.5-cycle delay 1 5.5-cycle delay 1 0 6.5-cycle delay 1 7.5-cycle delay
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 309 of 1036 rej09b0254-0600 bits 9, 3, and 2?area 5 oe / we negate address delay(a5teh2, a5teh1, and a5teh0): the a5teh bits specify the oe / we negate address delay time for the pcmcia interface connected area 5. bit 9: a5teh2 bit 3: a5teh1 bit 2: a5teh0 description 0 0 0 0.5-cycle delay (initial value) 1 1.5-cycle delay 1 0 2.5-cycle delay 1 3.5-cycle delay 1 0 0 4.5-cycle delay 1 5.5-cycle delay 1 0 6.5-cycle delay 1 7.5-cycle delay bits 8, 1, and 0?area6 oe / we negate address delay (a6teh2, a6teh1, and a6teh0): the a6teh bits specify the oe / we negate address delay time for the pcmcia interface connected to area 6. bit 8: a6teh2 bit 1: a6teh1 bit 0: a6teh0 description 0 0 0 0.5-cycle delay (initial value) 1 1.5-cycle delay 1 0 2.5-cycle delay 1 3.5-cycle delay 1 0 0 4.5-cycle delay 1 5.5-cycle delay 1 0 6.5-cycle delay 1 7.5-cycle delay
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 310 of 1036 rej09b0254-0600 12.2.7 synchronous dram mode register (sdmr) the synchronous dram mode register (sdmr) is written to via the synchronous dram address bus and is an 8-bit write-only register. it sets synchronous dram mode for areas 2 and 3. sdmr is undefined after a power-on reset. the register contents are not initialized by a manual reset or standby mode; values remain unchanged. bit: 31 ...................... 12 11 10 9 8 7 6 5 4 3 2 1 0 sdmr address ? ? ? ? ? ? ? ? ? ? ? ? initial value: ? ............... ....... ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: ? ...................... ? w * w * w w w w w w w w ? ? note: * depending on the type of synchronous dram. writes to the synchronous dram mode register use the address bus rather than the data bus. if the value to be set is x and the sdmr address is y, the value x is written in the synchronous dram mode register by writing in address x + y. since, with a 32-bit bus width, a0 of the synchronous dram is connected to a2 of the chip and a1 of the synchronous dram is connected to a3 of the chip, the value actually written to the synchronous dram is the x value shifted two bits right. with a 16-bit bus width, the value written is the x value shifted one bit right. for example, with a 32-bit bus width, when h'0230 is written to the sdmr register of area 2, random data is written to the address h'ffffd000 (address y) + h'08c0 (value x), or h'ffffd8c0. as a result, h'0230 is written to the sdmr register. the range for value x is h'0000 to h'0ffc. when h'0230 is written to the sdmr register of area 3, random data is written to the address h'ffffe000 (address y) + h'08c0 (v alue x), or h'ffffe8c0. as a result, h'0230 is written to the sdmr register. the ra nge for value x is h'0000 to h'0ffc.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 311 of 1036 rej09b0254-0600 12.2.8 refresh timer contro l/status register (rtcsr) the refresh timer control/s tatus register (rtcsr) is a 16-bit read /write register that specifies the refresh cycle, whether to generate an interrupt, and that interrupt's cycle. it is initialized to h'0000 by a power-on reset, but is not initialized by a manual reset or standby mode. before specifying the cks2 to cks0 of rtcst, the rtcor must be specified. note: writing to the rtcsr differs from that to general registers to ensure the rtcsr is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 12.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? cmf cmie cks2 cks1 cks0 ovf ovie lmts initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?reserved: these bits are always read as 0. the write value should always be 0. bit 7?compare match flag (cmf): the cmf status flag indicates that the values of rtcnt and rtcor match. bit 7: cmf description 0 the values of rtcnt and rtcor do not match. clear condition: when a refresh is performed after 0 has been written in cmf and rfsh = 1 and rmode = 0 (to perform a cbr refresh). (initial value) 1 the values of rtcnt and rtcor match. set condition: rtcnt = rtcor * note: * contents do not change when 1 is written to cmf. bit 6?compare match interrupt enable (cmie): enables or disables an interrupt request caused when the cmf of rtcsr is set to 1. do no t set this bit to 1 when using cas-before-ras refresh or auto-refresh. bit 6: cmie description 0 disables an interrupt request caused by cmf (initial value) 1 enables an interrupt request caused by cmf
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 312 of 1036 rej09b0254-0600 bits 5 to 3?clock select bits (cks2 to cks0): select the clock input to rtcnt. the source clock is the external bus clock (bclk). the rtcnt count clock is ckio divided by the specified ratio. the specified ratios are shown below in th e normal external bus clock. before specifying the cks2 to cks0 of rtcst, the rtcor must be specified. description bit 5: cks2 bit 4: cks1 bit 3: cks0 normal external bus clock 0 0 0 disables clock input (initial value) 1 bus clock (ckio)/4 1 0 ckio/16 1 ckio/64 1 0 0 ckio/256 1 ckio/1024 1 0 ckio/2048 1 ckio/4096 bit 2?refresh count overflow flag (ovf): the ovf status flag indicates when the number of refresh requests indicated in the refresh count register (rfcr) ex ceeds the limit set in the lmts bit of rtcsr. bit 2: ovf description 0 rfcr has not exceeded the count limit value set in lmts clear conditions: when 0 is written to ovf (initial value) 1 rfcr has exceeded the count limit value set in lmts set conditions: when the rfcr value has exceeded the count limit value set in lmts * note: * contents don't change when 1 is written to ovf. bit 1?refresh count overflow interrupt enab le (ovie): ovie selects whether to suppress generation of interrupt requests by ovf wh en the ovf bit of rtcsr is set to 1. bit 1: ovie description 0 disables interrupt requests from the ovf (initial value) 1 enables interrupt requests from the ovf
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 313 of 1036 rej09b0254-0600 bit 0?refresh count overflow limit select (lmts): indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (rfcr). when the value rfcr overflows the value specified by lmts, the ovf flag is set. bit 0: lmts description 0 count limit value is 1024 (initial value) 1 count limit value is 512 12.2.9 refresh time r counter (rtcnt) rtcnt is a 16-bit read/write register. rtcnt is an 8-bit counter that counts up with input clocks. the clock select bits (cks2 to cks0) of rtcsr select the input clock. when rtcnt matches rtcor, the cmf bit of tcsr is set and rtcnt is cleared. rtcnt is initialized to h'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by standby mode and holds its values unchanged. note: writing to the rtcnt differs from that to general registers to ensure the rtcnt is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 12.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 314 of 1036 rej09b0254-0600 12.2.10 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a 16-bit read/write register. the values of rtcor and rtcnt (bottom 8 bits) are co nstantly compared. when the values match, the compare match flag (cmf) of rtcsr is set and rtcnt is cleared to 0. when the refresh bit (rfsh) of the individual memory control register (mcr) is set to 1 and the refresh mode is set to cas-before- ras refresh, a memory refresh cycle occurs when the cmf bit is set. rtcor is initialized to h'00 by a power-on reset. it is not initialized by a manual reset or standby mode, but holds its contents. make the rtcor setting before setting bits cks2 to cks0 in rtcsr. note: writing to the rtcor differs from that to general registers to ensure the rtcor is not rewritten incorrectly. use the word-transfer instruction to set the upper byte as b'10100101 and the lower byte as the write data. for details, see section 12.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w 12.2.11 refresh count register (rfcr) the refresh count register (rfcr) is a 16-bit r ead/write register. it is a 10-bit counter that increments every time rtcor and rtcnt match. when rfcr exceeds the count limit value set in the lmts of rtcsr, rtcsr's ovf bit is set and rfcr clears. rfcr is initialized to h'0000 when a power-on reset is performed. it is not initialized by a manual reset or standby mode, but holds its contents. note: writing to the rfcr differs from that to general registers to ensure the rfcr is not rewritten incorrectly. use the word-transfer in struction to set the msb and followed six bits of upper bytes as b'101001 and remaining bits as the write data. for details, see section 12.2.12, cautions on accessing refresh control related registers. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 315 of 1036 rej09b0254-0600 12.2.12 cautions on accessing re fresh control related registers rfcr, rtcsr, rtcnt, and rtcor require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 12.4). perform reads and writes using the following methods: 1. writing to rfcr, rtcs r, rtcnt, and rtcor when writing to rfcr, rtcsr, rtcnt, and rtco r, use only word transfer instructions. you cannot write with byte transfer instructions. when writing to rtcnt, rtcsr, or rtcor, place b'10100101 in the upper byte and the write data in the lower byte. when writing to rfcr, place b'101001 in the top 6 bits and the write data in the remaining bits, as shown in figure 12.4. 2. reading from rfcr, rt csr, rtcnt, and rtcor when reading from rfcr, rtcsr, rtcnt, and rtcor, carry out reads with 16-bit width. 0 is read out from undefined bit sections. 15 10 8 rtcsr, rtcnt, rtcor 0 rfcr 7 100101 15 10 10 0 9 1 0 0 1 write data write data figure 12.4 writing to rfcr, rtcsr, rtcnt, and rtcor
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 316 of 1036 rej09b0254-0600 12.3 bsc operation 12.3.1 endian/access size and data alignment this lsi supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. this switchover is designated by an external pin (md5 pin) at the time of a power-on reset. after a power-on reset, big endian is engaged when md5 is low; little endian is engaged when md5 is high. three data bus widths are available for ordinary memory (byte, word, longword) and two data bus widths (word and long word) for synchronous dram. for th e pcmcia interface, choose from byte and word. this means data alignment is done by matching the device's data width and endian. the access unit must also be matched to the devi ce's bus width. this al so means that when longword data is read from a byte-width device, the read operation must happen 4 times. in this lsi, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 12.6 to 12.11 show the relationship between endian, device data width, and access unit. table 12.6 32-bit extern al device/big endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 data 7 to 0 ? ? ? assert byte access at 1 ? data 7 to 0 ? ? assert byte access at 2 ? ? data 7 to 0 ? assert byte access at 3 ? ? ? data 7 to 0 assert word access at 0 data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 assert assert longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 317 of 1036 rej09b0254-0600 table 12.7 16-bit extern al device/big endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 ? ? data 7 to 0 ? assert ? byte access at 1 ? ? ? data 7 to 0 assert byte access at 2 ? ? data 7 to 0 ? assert ? byte access at 3 ? ? ? data 7 to 0 assert word access at 0 ? ? data 15 to 8 data 7 to 0 assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 assert assert 1st time at 0 ? ? data 31 to 24 data 23 to 16 assert assert longword access at 0 2nd time at 2 ? ? data 15 to 8 data 7 to 0 assert assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 318 of 1036 rej09b0254-0600 table 12.8 8-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 ? ? ? data 7 to 0 assert byte access at 1 ? ? ? data 7 to 0 assert byte access at 2 ? ? ? data 7 to 0 assert byte access at 3 ? ? ? data 7 to 0 assert word access at 0 1st time at 0 ? ? ? data 15 to 8 assert 2nd time at 1 ? ? ? data 7 to 0 assert word access at 2 1st time at 2 ? ? ? data 15 to 8 assert 2nd time at 3 ? ? ? data 7 to 0 assert longword access at 0 1st time at 0 ? ? ? data 31 to 24 assert 2nd time at 1 ? ? ? data 23 to 16 assert 3rd time at 2 ? ? ? data 15 to 8 assert 4th time at 3 ? ? ? data 7 to 0 assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 319 of 1036 rej09b0254-0600 table 12.9 32-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 ? ? ? data 7 to 0 assert byte access at 1 ? ? data 7 to 0 ? assert byte access at 2 ? data 7 to 0 ? ? assert byte access at 3 data 7 to 0 ? ? ? assert word access at 0 ? ? data 15 to 8 data 7 to 0 assert assert word access at 2 data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 320 of 1036 rej09b0254-0600 table 12.10 16-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 ? ? ? data 7 to 0 assert byte access at 1 ? ? data 7 to 0 ? assert byte access at 2 ? ? ? data 7 to 0 assert byte access at 3 ? ? data 7 to 0 ? assert word access at 0 ? ? data 15 to 8 data 7 to 0 assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 assert assert 1st time at 0 ? ? data 15 to 8 data 7 to 0 assert assert longword access at 0 2nd time at 2 ? ? data 31 to 24 data 23 to 16 assert assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 321 of 1036 rej09b0254-0600 table 12.11 8-bit external device/little endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 , dqmuu we2 , dqmul we1 , dqmlu we0 , dqmll byte access at 0 ? ? ? data 7 to 0 assert byte access at 1 ? ? ? data 7 to 0 assert byte access at 2 ? ? ? data 7 to 0 assert byte access at 3 ? ? ? data 7 to 0 assert word access at 0 1st time at 0 ? ? ? data 7 to 0 assert 2nd time at 1 ? ? ? data 15 to 8 assert word access at 2 1st time at 2 ? ? ? data 7 to 0 assert 2nd time at 3 ? ? ? data 15 to 8 assert longword access at 0 1st time at 0 ? ? ? data 7 to 0 assert 2nd time at 1 ? ? ? data 15 to 8 assert 3rd time at 2 ? ? ? data 23 to 16 assert 4th time at 3 ? ? ? data 31 to 24 assert
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 322 of 1036 rej09b0254-0600 12.3.2 description of areas area 0: area 0 physical addresses a28 to a26 are 0'0. addresses a31 to a29 are ignored and the address range is h'00000000 + h'20000000 n ? h'03ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories such as sram, rom, and bur st rom can be connected to this space. byte, word, or longword can be selected as the bus width using external pins md3 and md4. when the area 0 space is accessed, a cs0 signal is asserted. an rd signal that can be used as oe and the we0 to we3 signals for write control are also asserted . the number of bus cycles is selected between 0 and 10 wait cycles using the a0w2 to a0 w0 bits of wcr2. in addition, any number of waits can be inserted in each bus cycl e by means of the external wait pin ( wait ). when the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 10 according to the number of waits. area 1: area 1 physical addresses a28 to a26 are 001. addresses a31 to a29 are ignored and the address range is h'04000000 + h'20000000 n ? h'07ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). area 1 is the area specifically for the internal peripheral modules. the external memories cannot be connected. control registers of peripheral modules shown below are mapped to this area 1. their addresses are physical address, to which logical addr esses can be mapped with the mmu enabled: dmac, port, scif, adc, dac, lcdc, pcc, siof, afeif, usbf, usbh, intc (except intevt, ipra, iprb) those registers must be set not to be cached. area 2: area 2 physical addresses a28 to a26 are 010. addresses a31 to a29 are ignored and the address range is h'08000000 + h'20000000 n ? h'0bffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories like sram and rom, as well as synchronous dram, can be connected to this space. byte, word, or longword can be sel ected as the bus width using the a2sz1 to a2sz0 bits of bcr2 for ordinary memory. when the area 2 space is accessed, a cs2 signal is asserted. when ordinary memories are connected, an rd signal that can be used as oe and the we0 to we3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the a2w1 to a2w0 bits of wcr2. in addition, any nu mber of waits can be inserted in each bus cycle by means of the external wait pin ( wait ) only when the ordinary memories are connected.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 323 of 1036 rej09b0254-0600 when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll ar e all asserted and addresses multiplexed. control of ras , cas , data timing, and address multiplexing is set with mcr. area 3: area 3 physical addresses a28 to a26 are 011. addresses a31 to a29 are ignored and the address range is h'0c000000 + h'20000000 n to h'0fffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories like sram and rom, as well as synchronous dram, can be connected to this space. byte, word or longword can be select ed as the bus width using the a3sz1 to a3sz0 bits of bcr2 for ordinary memory. when area 3 space is accessed, cs3 is asserted. when ordinary memories are connected, an rd signal that can be used as oe and the we0 to we3 signals for write control are a sserted and the number of bus cy cles is selected between 0 and 3 wait cycles using the a3w1 to a3w0 bits of wcr2. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ).only when the ordinary memories are connected. when synchronous dram is connected, the ras signal, cas signal, rd/ wr signal, and byte controls dqmhh, dqmhl, dqmlh, and dqmll are all asserted and addresses multiplexed. area 4: area 4 physical addresses a28 to a26 are 1'0. addressesa31 to a29 are ignored and the address range is h'10000000 + h'20000000 n ? h'13ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). only ordinary memories like sram and rom can be connected to this space. byte, word, or longword can be selected as the bus width using the a4sz1 to a4sz0 bits of bcr2. when the area 4 space is accessed, a cs4 signal is asserted. an rd signal that can be used as oe and the we0 to we3 signals for write control are also asserted . the number of bus cycles is selected between 0 and 10 wait cycles using the a4w2 to a4w0 bits of wcr2. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). area 5: area 5 physical addresses a28 to a26 are 101. addresses a31 to a29 are ignored and the address range is the 64 mbytes at h'14000000 + h'20000000 n to h'17ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories like sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. when the pcmcia interface is used, the ic memory card interface address range-comprises the 32 mbytes at h'14000000 + h'20000000 n to h'15ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces), and the i/o card interface address range-comprises the 32 mbytes at h'16000000 + h'20000000 n to h'17ffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 324 of 1036 rej09b0254-0600 for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using the a5sz1 to a5sz0 bits of bcr2. for the pcmcia interface, byte, and word can be selected as the bus width using the a5sz1 to a5sz0 bits of bcr2. when the area 5 space is accessed and ordinary memory is connected, a cs5 signal is asserted. an rd signal that can be used as oe and the we0 to we3 signals for write control are also asserted. when the pcmcia interface is used, the ce1a signal, ce2a signal, rd signal as oe signal, and we , iciord , iciowr signal are asserted. the number of bus cycles is selected between 0 an d 10 wait cycles using the a5w2 to a5w0 bits of wcr2. with the pcmcia interface, from 0 to 38 wait cycles can be selected using the a5w2 to a5w0 bits of wcr2 and the a5w3 bit of p cr. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). when a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 11 (2 to 39 for the pcmcia interface) according to the number of waits. the setup and hold times of address/ cs5 for the read/write strobe signal can be set in the range 0.5 to 7.5 cycles using a5ted2 to a5ted0 and a5teh2 to a5teh0 bits of the pcr register. (single-cycle units) area 6: area 6 physical addresses a28 to a26 are 110. address a31 to a29 are ignored and the address range is the 64 mbytes at h'18000000 + h'20000000 n to h'1bffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). ordinary memories like sram and rom as well as burst rom and pcmcia interfaces can be connected to this space. when the pcmcia interface is used, the ic memory card interface address range is 32 mbytes at h'18000000 + h'20000000 n to h'19ffffff + h'2000'000 n and 'he i/o card interface address range is 32 mbytes at h'1a000000 + h'20000000 n to h'1bffffff + h'20000000 n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). for ordinary memory and burst rom, byte, word, or longword can be selected as the bus width using the a6sz1 to a6sz0 bits of bcr2. for the pcmcia interface, byte, and word can be selected as the bus width using the a6sz1 to a6sz0 bits of bcr2. when the area 6 space is accessed and ordinary memory is connected, a cs6 signal is asserted. an rd signal that can be used as oe and the we0 to we3 signals for write control are also asserted. when the pcmcia interface is used, the ci1b signal, ce2b signal, rd signal as oe signal, and we , iciord , and iciowr signals are asserted. the number of bus cycles is selected between 0 to 10 wait cycles using the a6w2 to a6w0 bits of wcr2. with the pcmcia interface, from 0 to 38 wait cycles can be selected using the a6w2 to a6w0 bits of wcr2 and the a6w3 bit of pcr. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). the bus cycle pitch of the burst cycle
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 325 of 1036 rej09b0254-0600 is determined within a range of 2 to 11 (2 to 39 for the pcmcia interface) according to the number of waits. the setup and hold times of address/ cs6 for the read/write strobe signals can be set in the range 0.5 to 7.5 cycles using a6ted2 to a6ted0 and a6teh2 to a6teh0 bits of the pcr register. (single-cycle units) 12.3.3 basic interface basic timing: the basic interface of this lsi uses strobe signal output in consid eration of the fact that mainly static ram will be directly connected. figure 12.5 shows the basic timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the st art of a bus cycle. the csn signal is negated on the t2 clock falling edge to secure the negation period. therefore, in case of access at minimum pitch, there is a half- cycle negation period. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the we signal for the byte to be written is asserted. for details, see section 12.3 .1, endian/access size and data alignment. read/write for cache fill or write-b ack follows the set bus width and transfers a total of 16 bytes continuously. the bus is not releas ed during this transf er. for cache misses that occur during byte or word operand accesses or bran ching to odd word bou ndaries, the fill is al ways performed by longword accesses on the chip-external inte rface. write-through-ar ea write access and non- cacheable read/write access are based on the actual address size.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 326 of 1036 rej09b0254-0600 t1 ckio a25 to a0 csn rd/wr rd d31 to d0 wen d31 to d0 bs t2 read write figure 12.5 basic timi ng of basic interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 327 of 1036 rej09b0254-0600 figures 12.6, 12.7, and 12.8 show examples of connection to 32, 16, and 8-bit data-width static ram, respectively. a16 a0 cs oe i/o7 i/o0 we a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 SH7727 128k 8 bit sram a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we figure 12.6 example of 32-bit data-width static ram connection
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 328 of 1036 rej09b0254-0600 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 d7 d0 we0 SH7727 128k 8 bit sram a16 a0 cs oe i/o7 i/o0 we figure 12.7 example of 16-bit data-width static ram connection a16 a0 csn rd d7 d0 we0 SH7727 128k 8 bit sram a16 a0 cs oe i/o7 i/o0 we figure 12.8 example of 8-bit data-width static ram connection
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 329 of 1036 rej09b0254-0600 wait state control: wait state insertion on the basic inte rface can be controlled by the wcr2 settings. if the wcr2 wait specification bits corre sponding to a particular area are not zero, a software wait is inserted in acco rdance with that specifi cation. for details, see section 12.2.4, wait state control register 2 (wcr2). the specified number of tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 12.9. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen d31 to d0 bs tw t2 read write figure 12.9 basic interface wa it timing (software wait only) when software wait insertion is specified by wcr2, the external wait input wait signal is also sampled. to input low level signal to wait , set the waitsel bit of the wcr1 register to 1. wait pin sampling is shown in figure 12.10. a 2- cycle wait is specified as a software wait.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 330 of 1036 rej09b0254-0600 sampling is performed at the transition from the tw state to the t2 state; therefore, if the wait signal has no effect if asserted in th e t1 cycle or the first tw cycle. the wait signal is sampled at the falling edge of the clock. if the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used.. however, the wait signal is ignored in the following three cases: ? when writing to an external address area using dma 16-byte transfer in dual address mode ? when transferring data from a dack-equipped external device to an external address area using dma 16-byte transfer in dual address mode ? during cache write-back access t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen d31 to d0 wait tw tw tw t2 read write bs wait states inserted by wait signal figure 12.10 basic interface wait st ate timing (wait state insertion by wait signal waitsel = 1)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 331 of 1036 rej09b0254-0600 12.3.4 synchronous dram interface synchronous dram direct connection: since synchronous dram can be selected by the cs signal, physical space areas 2 and 3 can be connected using ras and other control signals in common. if the memory type bits (dramtp2 to dramtp0) in bcr1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous dram space; if set to 011, areas 2 and 3 are both synchronous dram space. with this lsi, burst length 1 burst read/single write mode is supported as the synchronous dram operating mode. a data bus width of 16 or 32 bits can be selected. a 16-bit burst transfer is performed in a cache fill/write-back cycle, and onl y one access is performed in a write-through area write or a non-cach eable area read/write. the control signals for direct connection of synchronous dram are ras , cas , rd/ wr , cs2 or cs3 , dqmuu, dqmul, dqmlu, dqmll, and cke. all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid and fetched to the synchronous dram only when cs2 or cs3 is asserted. synchronous dram can therefore be connected in parallel to a number of areas. cke is negated (low ) only when self-refreshing is performed, and is always asserted (high) at other times. commands for synchronous dram are specified by ras , cas , rd/ wr , and special address signals. the commands are nop, auto-refresh (ref ), self-refresh (self), precharge all banks (pall), row address strobe bank active (actv), read (read), read with precharge (reada), write (writ), write with pr echarge (writa), and mode register write (mrs). byte specification is performed by dqmuu, dqmul, dqmlu, and dqmll. a read/write is performed for the byte for which the corresponding dqm is low. in big-endian mode, dqmuu specifies an access to address 4n, and dqmll speci fies an access to address 4n + 3. in little- endian mode, dqmuu specifies an access to addr ess 4n + 3, and dqmll specifies an access to address 4n. figures 12.11 and 12.12 show examples of the connection of two 1m 16-bit 4-bank synchronous drams and one 1m 16-bit 4-bank synchronous dram, respectively. ckio and ckio2 are the clock signals that can be input to the synchronous dram. when using multiple synchronous drams, use either ckio or ckio2, but not both. also to prevent big signal delays due to overloading, design the board so that the load capacity is 50 pf or less. aim to ensure wiring lengths are equal and avoid chaining the clock wiring to the synchronous drams.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 332 of 1036 rej09b0254-0600 ckio has higher drive capacity than ckio2. ck io is suitable for driving heavy load, while ckio2 offers higher resistance to emi noise an d reflection. however, as the degree of these characteristics vary depending on appli cations, their usage is not specified. a15 a14 a13 a2 ckio, ckio2 cke csn ras cas rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll SH7727 64m synchronous dram ( 1m 16-bit 4-bank ) a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml figure 12.11 example of 64-mbit synchronous dram connection (32-bit bus width)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 333 of 1036 rej09b0254-0600 SH7727 a14 a13 a12 a1 ckio, ckio2 cke csn ras cas rd/ wr d15 d0 dqmlu dqmll a13 a12 a11 a0 clk cke cs ras cas we dq15 dq0 dqmu dqml 64m synchronous dram (1m 16-bit 4-bank) figure 12.12 example of 64-mbit synchronous dram (16-bit bus width) address multiplexing: synchronous dram can be connected without external multiplexing circuitry in accordance with th e address multiplex specification bits amx3 to amx0 in mcr. table 12.12 shows the relationship between the address multiplex specification bits and the bits output at the address pins. table 12.13 shows the relationship between lsi address pins and synchronous dram address pins. a25 to a17 and a0 are not multiplexed; the original values are always output at these pins. when a0, the lsb of the synchronous dram addr ess, is connected to this lsi, it performs longword address specification. connection should therefore be made in the following order: with a 32-bit bus width, connect pin a0 of the synchronous dram to pin a2 of this lsi, then connect pin a1 to pin a3; with a 16-bit bus width, connect pin a0 of the synchronous dram to pin a1 of this lsi, then connect pin a1 and pin a2.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 334 of 1036 rej09b0254-0600 table 12.12 relationship between synchronous dram type, bus width and amx setting external address pin bus width memory type amx3 amx2 amx1 amx0 output timing a1 to a8 a9 a10 a11 a12 a13 a14 a15 a16 32 bits 256 mbits 4m 16-bit 4-bank * 1 1 0 1 column address a1?a8 a9 a10 a11 l/h a13 a23 a24 a25 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a25 128 mbits 1m 32-bit 4-bank * 0 1 0 0 column address a1?a8 a9 a10 a11 l/h a13 a22 a23 a16 row address a9?a16 a17 a18 a19 a20 a21 a22 a23 a16 2m 16-bit 4-bank * 0 1 0 1 column address a1?a8 a9 a10 a11 l/h a13 a23 a24 a16 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a16 4m 8-bit 4-bank * 0 1 1 0 column address a1?a8 a9 a10 a11 l/h a13 a24 a25 a16 row address a11?a18 a19 a20 a21 a22 a23 a24 a25 a16 64 mbits 1m 16-bit 4-bank * 0 1 0 0 column address a1?a8 a9 a10 a11 l/h a13 a22 a23 a16 row address a9?a16 a17 a18 a19 a20 a21 a22 a23 a16 2m 8-bit 4-bank * 0 1 0 1 column address a1?a8 a9 a10 a11 l/h a13 a23 a24 a16 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a16 4m 4-bit 4-bank * 0 1 1 0 column address a1?a8 a9 a10 a11 l/h a13 a24 a25 a16 row address a11?a18 a19 a20 a21 a22 a23 a24 a25 a16 512k 32-bit 4-bank 0 1 1 1 column address a1?a8 a9 a10 a11 l/h a21 a22 a15 a16 row address a9?a16 a17 a18 a19 a20 a21 a22 a23 a16 16 bits 512 mbits 8m 16-bit 4-bank * 1 1 1 0 column address a1?a8 a9 a10 l/h a12 a13 a24 a25 a16 row address a11?a18 a19 a20 a21 a22 a23 a24 a25 a16 256 mbits 4m 16-bit 4-bank 1 1 0 1 column address a1?a8 a9 a10 l/h a12 a22 a23 a24 a16 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a16 8m 8-bit 4-bank * 1 1 1 0 column address a1?a8 a9 a10 l/h a12 a23 a24 a25 a16 row address a11?a18 a19 a20 a21 a22 a23 a24 a25 a16 128 mbits 2m 16-bit 4-bank 0 1 0 1 column address a1?a8 a9 a10 l/h a12 a22 a23 a24 a16 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a16 64 mbits 1m 16-bit 4-bank 0 1 0 0 column address a1?a8 a9 a10 l/h a12 a21 a22 a15 a16 row address a9?a16 a17 a18 a19 a20 a21 a22 a23 a16 2m 8-bit 4-bank 0 1 0 1 column address a1?a8 a9 a10 l/h a12 a22 a23 a15 a16 row address a10?a17 a18 a19 a20 a21 a22 a23 a24 a16 notes: * l/h is a bit used to specify commands. it is fixed to l or h by the access mode. : bank address
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 335 of 1036 rej09b0254-0600 table 12.13 relationship between lsi address pins and synchronous dram address pins SH7727 address pin ras cycle cas cycle sdram address pin function a16 a24 a16 a14 address a15 a23 a23 a13 a14 a22 a22 a12 bank select bank address a13 a21 a13 a11 address a12 a20 l/h a10 address precharge specification a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 unused a0 a0 a0 unused burst read: in the example in figure 12.13 it is assumed that four 2m 8-bit synchronous drams are connected and a 32-bit data width is used, and the burst length is 1. following the tr cycle in which actv command output is performed, a read command is issued in the tc1, tc2, and tc3 cycles, and a reada command in the tc4 cycle, and the read da ta is accepted on the rising edge of the external command clock (ckio) from cycle td1 to cycle td4. the tpc cycle is used to wait for completion of auto-prechar ge based on the reada command inside the synchronous dram; no new access command can be i ssued to the same bank during this cycle, but access to synchronous dram for another area is possible. in this lsi, the number of tpc cycles is determined by the tpc bit specification in mcr, and commands cannot be issued for the same synchronous dram during this interval. to connect low-speed synchronous dram, the cycle can be extended by setting wcr2 and mcr bits. the number of cycles from the actv co mmand output cycle, tr, to the read command output cycle, tc1, can be specified by the rcd bit in mcr, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. in case of 2 or more cy cles, a trw cycle, in which an nop command is
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 336 of 1036 rej09b0254-0600 issued for the synchronous dram, is inserted be tween the tr cycle and the tc cycle. the number of cycles from read and reada command output cy cles tc1 to tc4 to the first read data latch cycle, td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of a2w1 and a2w0 or a3w1 and a3w0 in wcr2. this number of cycles corresponds to the number of synchronous dram cas latency cycles. ckio, ckio2 a 25 to a16, a 13 a 12 a 15, a14, a 11 to a0 cs2 or cs3 ras cas rd/ wr dqmxx d31 to d0 bs tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 tpc figure 12.13 basic timing fo r synchronous dram burst read figure 12.14 shows the burst read timing when rcd is set to 1, a3w1 and a3w0 are set to 10, and tpc is set to 1. the bs cycle, which is asserted for one cycle at the start of a bu s cycle for normal access space, is asserted in each of cycles td1 to td4 in a synchronous dram cycle. when a burst read is performed, the addres s is updated each time cas is asserted. as the unit of burst transfer is 16 bytes, address updating is performed for a3 and a2 only. the order of access is as follows: in a
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 337 of 1036 rej09b0254-0600 fill operation in the event of a cache miss, the missed da ta is read first, then 16-byte boundary data including the missed data is read in wraparound mode. ckio, ckio2 a 25 to a16, a 13 a 12 a 15, a14, a 11 to a0 cs2 or cs3 ras cas rd/ wr dqmxx d31 to d0 bs tr tc1 tc2 tc3/td1 tc4/td2 td3 tpc trw td4 figure 12.14 synchronous dram burs t read wait specification timing single read: figure 12.15 shows the timing when a single address read is performed. as the burst length is set to 1 in synchronous dram burst read /single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 338 of 1036 rej09b0254-0600 ckio, ckio2 a 25 to a16, a 13 a 12 a 15, a14, a 11 to a0 cs2 or cs3 ras cas rd/ wr dqmxx d31 to d0 bs tr tc1 td1 tpc figure 12.15 basic timing for synchronous dram single read burst write: the timing chart for a burst write is shown in figure 12.16. in this lsi, a burst write occurs only in the event of cach e write-back. in a burst write oper ation, following the tr cycle in which actv command output is performed, a writ command is issued in the tc1, tc2, and tc3 cycles, and a writa command that performs auto-precharge is issu ed in the tc4 cycle. in the write cycle, the write data is output at the same time as the write command. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in addition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait in terval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles ca n be specified by the trwl bit in mcr.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 339 of 1036 rej09b0254-0600 ckio, ckio2 csn rd/ wr ras cas dqmxx d31 to d0 (read) bs tr tc1 tc2 tc3 tc4 (tpc) (tpc) a ddress upper bits a 12, a11, a 10 or a9 a ddress lower bits figure 12.16 basic timing fo r synchronous dram burst write
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 340 of 1036 rej09b0254-0600 single write: the basic timing chart for write access is show n in figure 12.17. in a single write operation, following the tr cycle in which actv command output is performed, a writa command that performs auto-precharge is issued in the tc1 cycle. in the write cycle, the write data is output at the same time as the write co mmand. in case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous dram after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. consequently, in a ddition to the precharge wait cycle, tpc, used in a read access, cycle trwl is also added as a wait interval until precharging is started following the write command. issuance of a new command for the same bank is postponed during this interval. the number of trwl cycles can be specified by the trwl bit in mcr.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 341 of 1036 rej09b0254-0600 ckio, ckio2 csn rd/ wr ras cas dqmxx d31 to d0 bs a ddress upper bits a 12 or a10 a ddress lower bits cke tr tc1 (trwl) (tpc) figure 12.17 basic timing fo r synchronous dram single write
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 342 of 1036 rej09b0254-0600 refreshing: the bus state controller is provided with a function for controlling synchronous dram refreshing. auto-re freshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in mcr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retain is low, can be activated by setting both the rmode bit and the rfsh bit to 1. 1. auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2 to cks0 in rtcsr, and the value set in rtcor. the valu e of bits cks2 to cks0 in rtcor should be set so as to satisfy the refresh interval stipula tion for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rf sh bits in mcr, then make the cks2 to cks0 setting. when the clock is selected by cks2 to cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constan tly compared with the rtcor value, and if the two values are the same, a refresh request is gene rated and an auto-refresh is performed. at the same time, rtcnt is cleared to zero and the count -up is restarted. figure 12.18 shows the auto- refresh cycle timing. all-bank precharging is performed in the tp cycle, then an ref command is issued in the trr cycle following the interval specified by the tpc bits in mcr. after the trr cycle, new command output cannot be performed for the duration of the number of cycles specified by the tras bits in mcr plus the number of cycles specified by the tpc bits in mcr. the tras and tpc bits must be set so as to satisfy the synchronous dram refresh cycle time stipulation (active/active command delay time). auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset. rtcor value rtcnt h'00000000 rtcsr.cks(2 ? 0) cmf external bus cmf flag cleared by start of refresh cycle = 000 000 rtcnt cleared to 0 when rtcnt = rtcor auto-refresh cycle time figure 12.18 auto-refresh operation
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 343 of 1036 rej09b0254-0600 tp trr trrw trrw (tpc) ckio, ckio2 cke csn ras cas rd/ wr figure 12.19 synchronous dram auto-refresh timing 2. self-refreshing self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit to 1. the self-refresh st ate is maintained while the cke signal is low. synchronous dram cannot be accessed while in th e self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the numb er of cycles specified by the tpc bits in mcr. self-refresh timing is shown in figure 12.20. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-refreshing is activated from th e state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-re freshing is restarted if rfsh is set to 1 and rmode is cleared to 0 when self-refresh mode is cleared. if the transition from clearing of self-
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 344 of 1036 rej09b0254-0600 refresh mode to the start of auto-refreshing takes tim e, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this lsi's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in cas e of a power-on reset, the bus state controller's registers are initialized, and therefor e the self-refresh state is cleared. self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. in addition, halt usb an d lcdc before entering standby mode. when the synchronous dram is used, self-refreshing is initiated in the following procedure. 1. clear the refresh control bit to 0. 2. write h'00 to rtcnt 3. set the refresh control bit and refresh mode bit to 1. trs1 ckio , ckio2 rd/ wr csn ras cas cke (trs2) (trs2) trs3 (tpc) (tpc) tp figure 12.20 synchronous dram self-refresh timing
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 345 of 1036 rej09b0254-0600 power-on sequence: in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'ffffd000 + x fo r area 2 synchronous dram, and to address h'ffffe000 + x for area 3 synchronous dram. in th is operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/single write, cas latency 1 to 3, wrap type = sequential, and burst length 1 supported by this lsi, arbitrary da ta is written in a byte- size access to the following addresses. with 32-bit bus width: area 2 area 3 cas latency 1 ffffd840 ffffe840 cas latency 2 ffffd880 ffffe880 cas latency 3 ffffd8c0 ffffe8c0 with 16-bit bus width: area 2 area 3 cas latency 1 ffffd420 ffffe420 cas latency 2 ffffd440 ffffe440 cas latency 3 ffffd460 ffffe460 mode register setting timing is shown in figure 12.21. as a result of the write to address h'ffffd000 + x or h'ffffe000 + x, a precharge all banks (pall) command is first issued in the trp1 cycle, then a mode register write command is issued in the tmw1 cycle. address signals, when the mode-register write command is issued, are as follows: a15 to a9 = 0000100 (burst read and single write) a8 to a6 = cas latency a5 = 0 (burst type = sequential) a4 to a2 = 000 (burst length 1) before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous dram. if the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. the number of dummy auto-refresh cycles specified by the manufactur er (usually 8) or more must be executed. this is usually achieved automatically while various kinds of initialization are being
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 346 of 1036 rej09b0254-0600 performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just wh ile these dummy cycles are being executed. with simple read or write access, the address count er in the synchronous dram used for auto- refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. ckio, ckio2 a11 a12 or a10 a9 to a2 csn rd/ wr ras cas d31 to d0 cke trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) a 15 to a13 or a15 to a12 figure 12.21 synchronous dram mode write timing
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 347 of 1036 rej09b0254-0600 12.3.5 burst rom interface setting bits a0bst (1, 0), a5bst (1, 0), and a6bs t (1, 0) in bcr1 to a non-zero value allows burst rom to be connected to areas 0, 5, and 6. the burst rom interface provides high-speed access to rom that has a nibble access function. th e timing for nibble access to burst rom is shown in figure 12.22. two wait cycles are set. basically, access is performed in the same way as for normal space, but when the first cycle ends the cs0 signal is not negated, and only the address is changed before the next access is executed. when 8-bit rom is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits a0bst (1, 0), a5bst (1, 0), or a6bst (1, 0). when 16-bit rom is connected, 4 or 8 can be set in the same way. when 32-bit rom is connected, only 4 can be set. wait pin sampling is performed in the first access if one or more wait states are set, and is always performed in the seco nd and subsequent accesses. even if no wait state insertion is specified in burst rom inte rface settings, two wait cycles are automatically inserted in the second and su bsequent accesses as show n in figure 12.23. however, the wait signal is ignored in the following three cases: ? when writing to an external address area using dma 16-byte transfer in dual address mode ? when transferring data from a dack-equipped external device to an external address area using dma 16-byte transfer in single address mode ? during cache write-back access
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 348 of 1036 rej09b0254-0600 t1 tw tw tb2 tb1 tw tb2 ckio a 25 to a4 a 3 to a0 csn rd/ we rd d31 to d0 bs wait t2 note: for a write cycle, a basic bus cycle (write cycle) is performed. tb1 figure 12.22 burst rom wait access timing
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 349 of 1036 rej09b0254-0600 t1 tb2 tb1 tb2 tb1 tb2 tb1 t2 ckio a25 to a4 a3 to a0 csn rd/ we rd d31 to d0 bs wait note: for a write cycle, a basic bus cycle (write cycle) is performed. figure 12.23 burst rom basic access timing
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 350 of 1036 rej09b0254-0600 12.3.6 pcmcia interface in this lsi, setting the a5pcm bit in bcr1 to 1 makes the bus interface for physical space area 5 an ic memory card and i/o card interface as s tipulated in jeida vers ion 4.2 (pcmcia2.1). setting the a6pcm bit to 1 makes the bus interface for physical space area 6 an ic memory card and i/o card interface as stipulated in jeida version 4.2. when the pcmcia interface is used, a bus size of 8 or 16 bits can be set by bits a5sz1 and a5sz0, or a6sz1 and a6sz0, in bcr2. figure 12.24 shows an example of pcmcia card connection to this lsi. to enable active insertion of the pcmcia cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this lsi's bus interface and the pcmcia cards. as operation in big-endian mode is not explicitly stipulated in the jeida/pcmcia specifications, the pcmcia interface for this lsi in big-endian mode is stipulated independently. however, the wait signal is ignored in the following three cases: ? when writing to an external address area using dma 16-byte transfer in dual address mode ? when transferring data from a dack-equipped external device to an external address area using dma 16-byte transfer in single address mode ? during cache write-back access
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 351 of 1036 rej09b0254-0600 a24 to a0 d15 to d0 rd/ wr ce1b /( cs6 ) ce1a /( cs5 )/(ptk[3]) rd we /( we1 )/(dqmlu) iciord /( we2 )/ (dqmul)/(ptk[6]) iciowr /( we3 )/ (dqmuu)/(ptk[7]) wait iois16 /(ptg[7]) SH7727 a25 to a0 d15 to d0 ce2 oe we / pgm ( iord ) ( iowr ) wait ( iois16 ) cd1, cd2 ce1 pc card (memory/io) g g dir dir g d7 to d0 d15 to d8 a25 to a0 d15 to d0 ce2 oe we / pgm wait cd1, cd2 ce1 pc card (memory/io) g g g dir dir g d7 to d0 d15 to d8 ce2b /(pte[5]) ce2a /(pte[4]) output port card detection circuit card detection circuit g figure 12.24 example of pcmcia interface (i f internal pc card controller is not used.)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 352 of 1036 rej09b0254-0600 memory card interface basic timing: figure 12.25 shows the basic timing for the pcmcia ic memory card interface. when physical space areas 5 and 6 are designated as pcmcia interface areas, bus accesses are automatically performed as ic memory card interface accesses. with a high external bus frequency (ckio), the se tup and hold times for the address (a24 to a0), card enable ( cs5 , ce2a , cs6 , ce2b ), and write data (d15 to d0) in a write cycle, become insufficient with respect to rd and wr (the we pin in this lsi). this lsi provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the pcr register. also, software waits by means of a wcr2 register setting and hardware waits by means of the wait pin can be inserted in the same way as for the basic interface. figure 12.26 shows the pcmcia memory bus wait timing.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 353 of 1036 rej09b0254-0600 ckio tpcm1 tpcm2 a 25 to a0 cexx rd/ wr d15 to d0 (read) d15 to d0 (read) rd (read) we (write) bs figure 12.25 basic timing for pcmcia memory card interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 354 of 1036 rej09b0254-0600 ckio tpcm0 a 25 to a0 rd/ wr cexx rd (read) d15 to d0 (read) d15 to d0 (write) we (write) bs wait tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w figure 12.26 wait timing for pcmcia memory card interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 355 of 1036 rej09b0254-0600 memory card interface burst timing: in this lsi, when the ic memory card interface is selected, page mode burst access mode can be us ed, for read access only, by setting bits a5bst1 and a5bst0 in bcr1 for physical space area 5, or bits a6bst1 and a6bst0 in bcr1 for area 6. this burst access mode is not stipulated in jeida version 4.2 (pcmcia2.1), but allows high- speed data access using rom provided with a burst mode, etc. burst access mode timing is shown in figures 12.27 and 12.28. ckio tpcm1 a 25 to a4 cexx a 3 to a0 rd/ wr rd (read) d15 to d0 (read) bs tpcm2 tpcm1 tpcm2 tpcm1 tpcm2 tpcm1 tpcm2 figure 12.27 basic timi ng for pcmcia memory card interface burst access
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 356 of 1036 rej09b0254-0600 ckio tpcm0 a 25 to a4 cexx a 3 to a0 rd/ wr rd (read) d15 to d0 (read) bs wait tpcm1 tpcm1w tpcm1w tpcm1w tpcm2 tpcm1 tpcm1w tpcm2 tpcm2w figure 12.28 wait timi ng for pcmcia memory card interface burst access
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 357 of 1036 rej09b0254-0600 when the ic memory card interface uses entire 32-mbyte memory space, the reg signal to switch common memory and attribute memory can be generated by a port. if the ic card memory interface uses memory area of 16 mbytes or le ss, 32-mbyte memory space can be used as 16- mbyte common memory space and 16-mbyte attri bute memory space as shown in figure 12.29. in this case, a24 pin can be used as the reg signal. area 5: h'14000000 area 5: h'16000000 area 6: h'18000000 area 6: h'1a000000 common/attribute memory i/o space common/attriute memory i/o space area 5: h'14000000 area 5: h'15000000 area 5: h'16000000 h'17000000 area 6: h'18000000 area 6: h'19000000 area 6: h'1a000000 h'1b000000 attribute memory common memory i/o space attribute memory common memory i/o space ic memory interface = 16 mbytes or less (a24 is used for reg) ic memory interface = 32 mbytes (i/o port is used for reg) figure 12.29 pcmcia space assignment
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 358 of 1036 rej09b0254-0600 i/o card interface timing: figures 12.30 and 12.31 show the timing for the pcmcia i/o card interface. switching between the i/o card interface and the ic memory card interface is performed according to the accessed address. when pcmcia is designed for physical space area 5, the bus access is automatically performed as an i/o car d interface access when a physical address from h'16000000 to h'17ffffff is accessed. when pcmc ia is designated for physical space area 6, the bus access is automatically performed as an i/o card interface access when a physical address from h'1a000000 to h'1bffffff is accessed. when accessing a pcmcia i/o card, the access s hould be performed using a non-cacheable area in virtual space (p2 or p3 space) or an area specified as non-cacheable by the mmu. when an i/o card interface access is made to a pcmcia card in little-endian mode, dynamic sizing of the i/o bus width is possible using the iois16 pin. when a 16-bit bus width is set for area 5 or area 6, if the iois16 signal is high during a word-size i/o bus cycle, the i/o port is recognized as being 8 bits in width. in this case , a data access for only 8 bits is performed in the i/o bus cycle being executed, fo llowed automatically by a data access for the remaining 8 bits. figure 12.32 shows the basic timing for dynamic bus sizing. in big-endian mode, the iois16 signal is not supported. in big-endian mode, the iois16 signal should be fixed low.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 359 of 1036 rej09b0254-0600 ckio tpci1 tpci2 a 25 to a0 rd/ wr cexx iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs figure 12.30 basic timing fo r pcmcia i/o card interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 360 of 1036 rej09b0254-0600 ckio a 25 to a0 rd/ wr cexx iciord (read) iciowr (write) d15 to d0 (read) d15 to d0 (write) bs wait iois16 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w figure 12.31 wait timing fo r pcmcia i/o card interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 361 of 1036 rej09b0254-0600 ckio tpci0 a 25 to a1 cexx a 0 rd/ wr iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs wait iois16 tpci1 tpci1w tpci2 tpci1 tpci1w tpci2 tpci2w figure 12.32 dynamic bus sizing ti ming for pcmcia i/ o card interface
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 362 of 1036 rej09b0254-0600 12.3.7 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low- speed device may be too slow, causing a collision with data in the next access. this results in lowe r reliability or incorrect op eration. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write. if there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. there are two cases in which a wait cycle is insert ed: when an access is followed by an access to a different area, and when a read access is followed by a write access from this lsi. when this lsi performs consecutive write cycles, the data transf er direction is fixed (from this lsi to other memory) and there is no problem. with read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertio n is not performed. bits aniw1 and aniw0 (n = 0, 2 to 6) in wcr1 specify the number of idle cycles to be in serted between access cycles when a physical space area access is followed by an access to another area, or when this lsi performs a write access after a read access to physical space area n. if there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. waits are not inserted between accesses when bus ar bitration is performed, since empty cycles are inserted for arbitration purposes.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 363 of 1036 rej09b0254-0600 t1 ckio csm csn a 25 to a0 bs rd/ wr rd d31 to d0 t2 twait t1 t2 twait t1 t2 area m read area m inter-access wait specification area n inter-access wait specification area n space read area n space write figure 12.33 waits between access cycles 12.3.8 bus arbitration when a bus release request ( breq ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal ( back ) is output . the bus is not released during burst transfers for cache fills or tas instruction execution between the read cycle and write cycle. bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i. e. in the bus cycles when longword access is executed for the 8-bit memory. at the negation of breq , back is negated and bus use is restarted . see appendix a.1, pin functions, for the pin state when the bus is released.
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 364 of 1036 rej09b0254-0600 12.3.9 bus pull-up with this lsi, address pin pull-up can be perfor med when the bus is released by setting the pula bit in bcr1 to 1. the address pins are pulled up for a 4-clock period after back is asserted. figure 12.34 shows the address pin pull-up timing. similarly, data pin pull-up can be performed by setting the puld bit in bcr1 to 1. the data pins should be pulled up when the data bus is not in use. the data pin pull-up timing for a read cycle is shown in figure 12.35, and the timing for a write cycle in figure 12.36. hi-z pull-up ckio a 25 to a0 back figure 12.34 pins a25 to a0 pull-up timing pull-up ckio d31 to d0 rd csn pull-up figure 12.35 pins d31 to d0 pull-up timing (read cycle)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 365 of 1036 rej09b0254-0600 pull-up ckio d31 to d0 wen csn pull-up figure 12.36 pins d31 to d0 pull-up timing (write cycle)
section 12 bus state controller (bsc) rev.6.00 mar. 27, 2009 page 366 of 1036 rej09b0254-0600
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 367 of 1036 rej09b0254-0600 section 13 li bus state controller (lbsc) 13.1 overview the li bus state controller (lbsc) functions enable lcd controller and open hci compliant usb host controller to link directly with synchronous dram. lbsc is a slave bus state controller of bsc. 13.1.1 features the lbsc has the following features: ? direct interface to synchronous dram ? physical address space is specified only to area 3 ? a maximum 64 mbytes ? multiplexes row/column addresses accordi ng to synchronous dram capacity ? supports burst operation with various burst length; selectable from 1 to 32 ? controls timing of synchronous dram direct-connection control signals according to register setting ? 16-bit or 32-bit bus width according to register setting 13.1.2 register configuration the lbsc does not have any register inside, but refers bsc registers shown in table 13.1. table 13.1 register configuration name abbr. r/w initial value * address bus width bus control register 1 bcr1 r/w h'0000 h'ffffff60 16 bus control register 2 bcr2 r/w h'3ff0 h'ffffff62 16 wait state control register 1 wcr1 r/w h'3ff3 h'ffffff64 16 wait state control register 2 wcr2 r/w h'ffff h'ffffff66 16 individual memory control register mcr r/w h'0000 h'ffffff68 16 note: * initialized by power-on resets.
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 368 of 1036 rej09b0254-0600 13.1.3 bus control register 1 (bcr1) bus control register 1 (bcr1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. it is initialized to h'0000 by a power-on reset, but it is not initialized by a manual reset or in standby mode. do not ac cess external memory except area 0 until bcr1 register initialization is complete. bit: 15 14 13 12 11 10 9 8 pula puld hizmem hizcnt endian a0bst1 a0bst0 a5bst1 initial value: 0 0 0 0 0/1 * 0 0 0 r/w: r/w r/w r/w r/w r r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a5bst0 a6bst1 a6bst0 dram tp2 dram tp1 dram tp0 a5pcm a6pcm initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * samples the value of the external pin (md5) designating endian at power-on reset. bits 15 to 12?not referenced bit 11?endian flag (endian): samples a value at the external pin which designates endian (md5) at a power-on reset. endian for all physical spaces is decided by this bit. this bit is read- only. bit 11: endian description 0 at a reset, the endian setting external pi n (md5) is low, which indicates that the SH7727 is set as big endian. 1 at a reset, the endian setting external pin (md5) is high, which indicates that the SH7727 is set as little endian. bits 10 to 5?not referenced
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 369 of 1036 rej09b0254-0600 bits 4 to 2?area 2, area 3 memory type (dramtp2, dramtp1, dramtp0): specifies the type of memory connected to the physical space areas 2 and 3. before using lcdc and usb, set area 3 to synchronous dram (dramtp2 to dramtp0 equal to 010 or 011). bit 4: dramtp2 bit 3: dramtp1 bit 2: dramtp0 description 0 0 0 ordinary memory for areas 2 and 3 (initial value) 1 reserved (setting disabled) 1 0 ordinary memory for area 2 and synchronous dram for area 3 * 1 1 synchronous dram for areas 2 and 3 * 1 * 2 1 0 0 reserved 1 reserved 1 0 reserved (setting disabled) 1 reserved (setting disabled) notes: 1. it is not possible to acce ss synchronous dram if clock ratio i :bus clock = 1:1. 2. when selecting this mode, set the sa me bus width for area 2 and area 3. bits 1 and 0 ?not referenced
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 370 of 1036 rej09b0254-0600 13.1.4 bus control register 2 (bcr2) the bus control register 2 (bcr2) is a 16-bit read/w rite register that sets the bus-size width of each area and selects whether an 8-bit port is used or not. it is initialized to h'3ff0 by a power-on reset, but is not initialized by a manual reset or by standby mode. do not access external memory outside area 0 until bcr2 register initialization is complete. bit: 15 14 13 12 11 10 9 8 ? ? a6sz1 a6sz0 a5sz 1 a5sz0 a4sz1 a4sz0 initial value: 0 0 1 1 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3sz1 a3sz0 a2sz1 a2sz0 ? ? ? ? initial value: 1 1 1 1 0 0 0 0 r/w: r/w r/w r/w r/w r r r r bits 15 to 8 and 5 to 0 ?not referenced bits 7 and 6?area 3 bus size specification (a3sz1, a3sz0): specifies the bus sizes of physical space area 3. bit 7: a3sz1 bit 6: a3sz0 port a/b description 0 reserved (setting disabled) 0 1 reserved (setting disabled) 0 16-bit bus width 1 1 unused 32-bit bus width 0 reserved (setting disabled) 0 1 reserved (setting disabled) 0 16-bit bus width 1 1 used reserved (setting disabled)
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 371 of 1036 rej09b0254-0600 13.1.5 wait state control register 1 (wcr1) wait state control register 1 (wcr1) is a 16-bit read /write register that sp ecifies the number of idle (wait) state cycles inserted for each area. for some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. this can result in conflicts between data buses wh en consecutive memory acce sses are to different memories or when a write immediately follows a memory read. this lsi automatically inserts idle states equal to the number set in wcr1 in those cases. wcr1 is initialized to h'3ff3 by a power-on rese t. it is not initialized by a manual reset or by standby mode. bit: 15 14 13 12 11 10 9 8 wait sel ? a6iw1 a6iw0 a5iw1 a5iw0 a4iw1 a4iw0 initial value: 0 0 1 1 1 1 1 1 r/w: r/w r r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a3iw1 a3iw0 a2iw1 a2 iw0 ? ? a0iw1 a0iw0 initial value: 1 1 1 1 0 0 1 1 r/w: r/w r/w r/w r/w r r r/w r/w bits 15 to 8 and 5 to 0 ?not referenced bits 7 and 6? area 3 idle setting between cycles (a3iw1, a3iw0): specifies the number of idle state cycles to insert between bus cycles wh en switching from a read address in area 3 of the physical space to a write address in another space or within the same space. bit 7: a3iw1 bit 6: a3iw0 description 0 0 1 idle state cycle inserted 1 1 idle state cycle inserted 1 0 2 idle state cycle inserted 1 3 idle state cycle inserted (initial value)
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 372 of 1036 rej09b0254-0600 13.1.6 wait state control register 2 (wcr2) wait state control register 2 (wcr2) is a 16-bit read /write register that sp ecifies the number of wait state cycles inserted for each area. it also sp ecifies the pitch of data access for burst memory accesses. this allows direct connection of even lo w-speed memories without an external circuit. wcr2 is initialized to h'ffff by a power-on reset. it is not initialized by a manual reset or in standby mode. bit: 15 14 13 12 11 10 9 8 a6w2 a6w1 a6w0 a5w2 a5w1 a5w0 a4w2 a4w1 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 a4w0 a3w1 a3w0 a2w1 a2w0 a0w2 a0w1 a0w0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 7 and 4 to 0 ?not referenced bits 6 and 5? area 3 wait control (a3w1, a3w0): specifies the cas latency for the sdram of area 3 of the physical space. bit 6: a3w1 bit 5: a3w0 description sdram cas latency 0 1 0 1 1 1 0 2 1 3 (initial value)
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 373 of 1036 rej09b0254-0600 13.1.7 individual memory control register (mcr) the individual memory control register (mcr) is a 16-bit read/write register that specifies ras and cas timing and burst control for synchronous dram (areas 2 and 3), specifies address multiplexing, and controls refresh. this enables direct connection of synchronous dram without external circuits. the mcr is initialized to h'0000 by power-on re sets, but is not initialized by manual resets or standby mode. the bits tpc1 to tpc0, rcd1 to rcd0, trwl1 to trwl0, tras1 to tras0, and amx3 to amx0 are written to at the initializ ation after a power-on reset and should not be modified again. when rfsh and rmode are written to, write the same values to the other bits. when using synchronous dram, do not access areas 2 and 3 until this register initialization is complete. bit: 15 14 13 12 11 10 9 8 tpc1 tpc0 rcd1 rcd0 trwl1 trwl0 tras1 tras0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? amx3 amx2 amx1 amx0 rfsh rmode ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14?ras precharge time (tpc1, tpc0): when synchronous dram interface is selected, these bits set the minimum number of cycles until output of the next bank-active command after precharge. bit 15: tpc1 bit 14: tpc0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 374 of 1036 rej09b0254-0600 bits 13 and 12?ras?cas delay (rcd1, rcd0): when synchronous dram interface is selected, these bits set the bank active read/write command delay time. bit 13: rcd1 bit 12: rcd0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 11 and 10?write-precha rge delay (trwl1, trwl0): the trwl bits set the synchronous dram write-precharge delay time. th is designates the time between the end of a write cycle and the automatic precharge activation. after the write cycle, the next bank-active command is not issued for the period tpc + trwl. bit 11: trwl1 bit 10: trwl0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 reserved (setting disabled) bits 9 and 8? cas -before- ras refresh ras assert time (tras1, tras0): when synchronous dram interface is selected, no bank-active command is issues during the period tpc + tras after an auto-refresh command. bit 9: tras1 bit 8: tras0 description 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles bit 7?reserved: this bit is always read as 0 an d should only be written with 0.
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 375 of 1036 rej09b0254-0600 bits 6 to 3?address multiplex (amx3 , amx2, amx1, amx0): the amx bits specify address multiplexing for synchronous dram. bit6: amx3 bit5: amx2 bit 4: amx1 bit 3: amx0 description 1 1 0 1 when using a 16-bit bus width, the row address begins with a10. when using a 32-bit bus width, it begins with a11 . (the a10 value is output at a1 when the row address is output. 4m 16-bit 4-bank products) 1 0 when using a 16-bit bus width, the row address begins with a11. (the a11 value is output at a1 when the row address is output. 8m 16-bit 4-bank products) * 1 0 1 0 0 when using a 16-bit bus width, the row address begins with a9. when using a 32-bit bus width, it begins with a10 . (the a9 value is output at a1 when the row address is output. 1m 16-bit 4-bank products) 1 when using a 16-bit bus width, the row address begins with a10. when using a 32-bit bus width, it begins with a11 . (the a10 value is output at a1 when the row address is output. 2m 8-bit products) 0 the row address begins with a11 when bus width is 32 bit. * 2 (the a11 value is output at a1 when the row address is output. 4m 8-bit 4-bank products) 1 1 when using a 16-bit bus width, the row address begins with a9. when using a 32-bit bus width, it begins with a10 . (the a9 value is output at a1 when the row address is output. 512k 32-bit 4-bank products) * 2 0 0 0 reserved. amx3 to amx0 must be set to * 1 *** before accessing synchronous dram memory. (initial value) other values reserved (illegal setting) notes: 1. can be set only when using a 16-bit bus width. 2. can be set only when using a 32-bit bus width. bits 2 and 1?not referenced bit 0?reserved: this bit is always read as 0 an d should only be written with 0.
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 376 of 1036 rej09b0254-0600 13.2 lbsc operation 13.2.1 bus sharing architecture lcdc and usb host controller can share the system memory with cpu and dma controller, so these bus masters are able to work without any independent external memory and have huge available memory space up to 64 mbyte at area 3. since each lcdc, usb host controller, cp u, and dma controller can access area 3 individually. set addresses for each controller to avoid address sharing. 13.2.2 usable system memory lbsc works at below memories. memory area area3 memory type synchronous dram bus width 16 or 32 bits burst length 1 to 4 burst (usbh) 4 to 32 burst (lcdc) with 32-bit bus width, 8 to 64 burst (lcdc) with 16-bit bus width 13.2.3 bus arbitration lbsc accepts a request that comes from lcdc or usb host at a sa me time without any prioritization to each module. lbsc tries to get bus right from bsc at any time when it get a request from lcdc or usb host. once bsc gi ves lbsc a right, lcdc or bsc can access external memory directly. the arbiter of lbsc gi ves a bus right to lcdc or usb host as even. 13.2.4 lcdc li bus access while displaying images, the lcdc continuously reads data from the system memory with a 32 burst length. the lcdc burst length is specified by a register in the lcdc. if the data length is shorter than 32 burst length, such as the case for the edge of lcd panel, the lcdc uses a shorter burst length.
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 377 of 1036 rej09b0254-0600 13.2.5 usbh li bus access usb host issues 1 to 4 burst request to lbsc as normal read or write action. since the burst length issued by usb host is occasionally changed as fifo pointer rises up or falls, it is not supposed as 4 burst exactly. (area 3) bus li bus bus arbitration synchronous dram usbh bsc SH7727 lbsc lcdc figure 13.1 block diagra m of li bus architecture 13.2.6 setting of dma transfer wi th bus arbitration of other module this lsi has five types of bus master: cpu, dmac and refresh (bsc system), and lcdc and usbh (lbsc system). the following priority order is set for these buses. 1. the bsc and lbsc systems are the same in priority level. 2. in the bsc system, refresh has the highest priority. 3. between cpu and dmac, dmac is higher in priority when dma burst setting is made. in cycle steal, cpu and dmac are the same in priority level. 4. lcdc and usbh are the same priority level in the lbsc system. in cycle steal, the priority level of dma transfer is very low. th erefore, if the dmac transfer speed may cause problems, it is recommended to use the level-input burst transfer setting for dmac, especially when dreq signals from an external device can be negated.
section 13 li bus state controller (lbsc) rev.6.00 mar. 27, 2009 page 378 of 1036 rej09b0254-0600
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 379 of 1036 rej09b0254-0600 section 14 direct memory access controller (dmac) 14.1 overview this chip includes a four-channel direct me mory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip supporting modules (siof, scif, usbf, a/d converter, and d/a converter). using the dmac reduces the burden on the cp u and increases overall operating efficiency. 14.1.1 features the dmac has the following features. ? four channels ? 4-gb physical address space ? selectable data transfer length: 8-bit, 16-bit, 32-bit, or 16-byte transfer (in 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) ? maximum of 16 m times of transfers (16777216 times) ? address mode: dual address mode and single addr ess mode are supported. in addition, direct address transfer mode or indirect addr ess transfer mode can be selected. ? dual address mode transfer: both the transf er source and transfer destination are accessed by address. dual address mode has direct address transfer mode and indirect address transfer mode. direct address transfer mode: the values sp ecified in the dmac re gisters indicates the transfer source and transfer destination. two bus cycles are required for one data transfer. indirect address transfer mode: data is tran sferred with the address stored prior to the address specified in the transfer source addr ess in the dmac. other operations are the same as those of direct address transfer mode. this function is only valid in channel 3. four bus cycles are requested for one data transfer. ? single address mode transfer: either the transfer source or transfer destination peripheral device is accessed (selected) by means of th e dack signal, and the other device is accessed by address. one transfer unit of data is transferred in one bus cycle. ? channel functions: transfer mode that can be specified is different in each channel. ? channel 0: can accept requests from pe ripheral modules and external requests. ? channel 1: can accept reques ts from peripheral modules. ? channel 2: can accept requests from periphera l modules. this channel has a source address reload function, which reloads a so urce address for each 4 transfers.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 380 of 1036 rej09b0254-0600 ? channel 3: can accept requests from periphera l modules. direct address transfer mode or indirect address transfer mode can be specified. ? reload function: the value that was specifi ed in the source address register can be automatically reloaded every 4 dma transfers. this function is only valid in channel 2. ? three types of transfer requests ? external requests (from two dreq pins (channels 0 only). dreq can be detected either by falling edge or by low level) ? on-chip module requests (requests from on-chip supporting modules such as serial communications interface (siof, scif), a/d converter (a/d) and a timer (cmt) . this request can be accepted in all the channels) ? auto requests (the transfer request is generated automatically within the dmac) ? selectable bus modes: cycl e-steal mode or burst mode ? selectable channel priority levels: fixed mode: the channel priority is fixed. round-robin mode: the priority of the channel in which the ex ecution request was accepted is made the lowest. ? interrupt request: an interrupt request can be generated to the cpu after the specified number of times of transfers.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 381 of 1036 rej09b0254-0600 14.1.2 block diagram figure 14.1 is a block diagram of the dmac. peripheral bus internal bus dreq0 scif a/d converter cmt dein interation control sarn dmac module register control start-up control request priority control bus interface bus state controller on-chip supporting module selector chrar usbf siof ch0 to ch3 darn dmatcrn chcrn dmaor external ram external rom external i/o (memory mapped) external i/o (with acknowledge) dack0 , drak0 x/y memory dmaor: sarn: darn: dmatcrn: chcrn: chrar: dein: n: dmac operation register dmac source address register dmac destination address register dmac transfer count register dmac channel control register dma channel assign register dma transfer-end interrupt request to cpu 0 to 3 legend: figure 14.1 dmac block diagram
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 382 of 1036 rej09b0254-0600 14.1.3 pin configuration table 14.1 shows the dmac pins. table 14.1 pin configuration channel name symbol i/o function 0 dma transfer request dreq0 input dma transfer request input from external device to channel 0 dreq acknowledge dack0 output str obe output to an external i/o at dma transfer request from external device to channel 0 dma request acknowledge drak0 output output showing that dreq0 has been accepted 14.1.4 register configuration table 14.2 summarizes the dmac registers. dmac has a total of 18 registers, four registers for each channel and two registers for controlling all channels. table 14.2 dmac registers channel name abbrevi- ation r/w initial value address register size access size 0 dma source address register 0 sar0 r/w undefined h'04000020 (h'a4000020) * 4 32 bits 16, 32 * 2 dma destination address register 0 dar0 r/w undefined h'04000024 (h'a4000024) * 4 32 bits 16, 32 * 2 dma transfer count register 0 dmatcr0 r/w undefined h'04000028 (h'a4000028) * 4 24 bits 16, 32 * 3 dma channel control register 0 chcr0 r/w * 1 h'00000000 h'0400002c (h'a400002c) * 4 32 bits 8, 16, 32 * 2 1 dma source address register 1 sar1 r/w undefined h'04000030 (h'a4000030) * 4 32 bits 16, 32 * 2 dma destination address register 1 dar1 r/w undefined h'04000034 (h'a4000034) * 4 32 bits 16, 32 * 2 dma transfer count register 1 dmatcr1 r/w undefined h'04000038 (h'a4000038) * 4 24 bits 16, 32 * 3 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'0400003c (h'a400003c) * 4 32 bits 8, 16, 32 * 2
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 383 of 1036 rej09b0254-0600 channel name abbrevi- ation r/w initial value address register size access size 2 dma source address register 2 sar2 r/w undefined h'04000040 (h'a4000040) * 4 32 bits 16, 32 * 2 dma destination address register 2 dar2 r/w undefined h'04000044 (h'a4000044) * 4 32 bits 16, 32 * 2 dma transfer count register 2 dmatcr2 r/w undefined h'04000048 (h'a4000048) * 4 24 bits 16, 32 * 3 dma channel control register 2 chcr2 r/w * 1 h'00000000 h'0400004c (h'a400004c) * 4 32 bits 8, 16, 32 * 2 3 dma source address register 3 sar3 r/w undefined h'04000050 (h'a4000050) * 4 32 bits 16, 32 * 2 dma destination address register 3 dar3 r/w undefined h'04000054 (h'a4000054) * 4 32 bits 16, 32 * 2 dma transfer count register 3 dmatcr3 r/w undefined h'04000058 (h'a4000058) * 4 24 bits 16, 32 * 3 dma channel control register 3 chcr3 r/w * 1 h'00000000 h'0400005c (h'a400005c) * 4 32 bits 8, 16, 32 * 2 shared dma operation register dmaor r/w * 1 h'0000 h'04000060 (h'a4000060) * 4 16 bits 8, 16 * 2 dma channel assign register chrar r/w h?0000 h?0400022a (h?a400022a) * 4 16 bits 16 notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only a write of 0 after a read of 1 to clear a flag is enabled for bit 1 in chcr0 to chcr3 and bits 1 and 2 in dmaor. 2. if sar0 to sar3, dar0 to dar3, and ch cr0 to chcr3 are accessed in 16 bits, the 16 bit values that were not accessed are held. 3. dmatcr comprises the 24 bits from bit 0 to bit 23. the upper 8 bits, bits 24 to 31, cannot be written with 1 and are always read as 0. 4. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 384 of 1036 rej09b0254-0600 14.2 register descriptions 14.2.1 dma source address regi sters 0 to 3 (sar0 to sar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 ? 0 ? initial value: ? ? ? ? ? ? r/w: r/w r/w r/w r/w ? r/w the dma source address registers 0 to 3 (sar0 to sar3) are 32-b it read/write registers that specify the source address of a dma transfer. duri ng a dma transfer, these registers indicate the next source address. to transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. when transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. if any other address is sp ecified, correct operation is not guaranteed. initial values are undefined after a reset. the previous values are held in standby mode.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 385 of 1036 rej09b0254-0600 14.2.2 dma destination address registers 0 to 3 (dar0 to dar3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 ? 0 ? initial value: ? ? ? ? ? ? r/w: r/w r/w r/w r/w ? r/w the dma destination address registers 0 to 3 (dar0 to dar3) are 32-bit read/write registers that specify the destination address of a dma transf er. these registers include count functions, and during a dma transfer, these registers indicate the next destination address. to transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary. when transferring data in 16-byte units, always se t a value at a 16-byte bou ndary (16n address) as the destination address. if any other address is specified, correct operatio n is not guaranteed. initial values are undefined after a reset. the previous value is held in standby mode.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 386 of 1036 rej09b0254-0600 14.2.3 dma transfer count registers 0 to 3 (dmatcr0 to dmatcr3) bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r r r r r r r r bit: 23 22 21 20 ... 0 ... initial value: ? ? ? ? ... ? r/w: r/w r/w r/w r/w ... r/w the dma transfer count registers 0 to 3 (d matcr0 to dmatcr3) are 24-bit read/write registers that specify the dma transfer count (bytes, words, or longwords). the number of transfers is 1 when the setting is h'000001, and 16777216 (the maximum) when h'000000 is set. during a dma transfer, these registers in dicate the remaining transfer count. to transfer data in 16 bytes, one 16-b yte transfer (128 b its) counts one. the upper eight bits in dmatcr are always read as 0 and should only be written with 0. initial values are undefined after a reset. the previous value is held in standby mode.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 387 of 1036 rej09b0254-0600 14.2.4 dma channel control registers 0 to 3 (chcr0 to chcr3) bit: 31 ... 21 20 19 18 17 16 ? ... ? di ro rl am al initial value: 0 ... 0 0 0 0 0 0 r/w: r ... r (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 (r/w) * 2 bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ds tm ts1 ts0 ie te de initial value: 0 0 0 0 0 0 0 0 r/w: r (r/w) * 2 r/w r/w r/w r/w r/(w) * 1 r/w notes: 1. only a write of 0 after a read of 1 is enabled for the te bit. 2. di, ro, rl, am, al, and ds bits are not included in some channels. the dma channel control registers 0 to 3 (chcr0 to chcr3) are 32-bit read /write registers that specify operation mode, transfer method, or others in each channel. writing to bits 31 to 21 and 7 in this register is invalid, and th ese bits are always read as 0. bit 20 is only used in chcr3. it is not used in chcr0 to chcr2. consequently, writing to this bit is invalid in chcr0 to chcr2, and this bit is always read as 0. bit 19 is only used in chcr2. it is not used in chcr0, chcr1, and chcr3. consequently, writing to this bit is invalid in chcr0, chcr1, an d chcr3, and this bit is always read as 0. bits 6 and 16 to 18 are only used in chcr0 and chcr1. they are not used in chcr2 and chcr3. consequently, writing to these bits is invalid in chcr2 and chcr3, and these bits are always read as 0. these registers are initialized to 0 after a power-on reset. the previous values are held in standby mode. bits 31 to 21?reserved: these bits are always read as 0 and should only be written with 0.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 388 of 1036 rej09b0254-0600 bit 20?direct/indirect selection (di): di selects direct address m ode operation or indirect address mode operation for a channel 3 source address. this bit is only valid in chcr3. this bit in chcr0 to chcr2 is always read as 0 and should only be written with 0. when using 16-byte transfer, direct address mode must be specified. operation is not guaranteed if indirect address mode is specified. bit 20: di description 0 direct address mode (initial value) 1 indirect address mode bit 19?source address reload (ro): ro selects whether the source address initial value is reloaded in channel 2. this bit is only valid in chcr2. this bit in chcr0, chcr1, and chcr3 is always read as 0 and should only be written with 0. when using 16-byte transfer, this bit must be clear ed to 0, specifying non-reloading. operation is not guaranteed if reloading is specified. bit 19: ro description 0 a source address is not reloaded (initial value) 1 a source address is reloaded bit 18?request check level (rl): rl specifies the drak (acknowledge of dreq ) signal output is high active or low active. this bit is only valid in chcr0. this bit in chcr1, chcr2 and chcr3 is always read as 0 and should only be written with 0. bit 18: rl description 0 low-active output of drak (initial value) 1 high-active output of drak
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 389 of 1036 rej09b0254-0600 bit 17?acknowledge mode (am): am specifies whether dack is ou tput in data read cycle or in data write cycle in dual address mode. in single address mode, dack is always output regardless of this bit specification. this bit is only valid in chcr0. this bit in chcr1, chcr2 and chcr3 is always read as 0 and should only be written with 0. bit 17: am description 0 dack output in read cycle (initial value) 1 dack output in write cycle bit 16?acknowledge level (al): al specifies the dack (acknowledge) signal output is high active or low active. this bit is only valid in chcr0. this bit in chcr1, chcr2 and chcr3 is always read as 0 and should only be written with 0. bit 16: al description 0 low-active output of dack (initial value) 1 high-active output of dack bits 15 and 14?destination address mode 1, 0 (dm1 and dm0): dm1 and dm0 select whether the dma destination address is incremented, decremented, or fixed. bit 15: dm1 bit 14: dm0 description 0 0 fixed destination address * (initial value) 1 destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit trans fer, +16 in 16-byte transfer) 1 0 destination address is decrement ed (?1 in 8-bit transfer, ?2 in 16-bit transfer, ?4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 reserved (illegal setting) note: * this setting cannot be used to perform 16-byte transfers with a destination in x/y memory.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 390 of 1036 rej09b0254-0600 bits 13 and 12?source address mode 1, 0 (s m1 and sm0): sm1 and sm0 select whether the dma source address is incremented, decremented, or fixed. bit 13: sm1 bit 12: sm0 description 0 0 fixed source address * (initial value) 1 source address is incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit trans fer, +16 in 16-byte transfer) 1 0 source address is decremented (?1 in 8-bit transfer, ?2 in 16- bit transfer, ?4 in 32-bit transfer; illegal setting in 16-byte transfer) 1 reserved (illegal setting) note: * this setting cannot be used to perform 16-byte transfers with a destination in x/y memory. if the transfer source is specified in indirect addr ess, specify the address (indirect address) where the address of data to be transferred is stored as data, in source address register 3 (sar3). specification of sar3 increment or decrement in indirect address mode depends on sm1 and sm0 settings. in this case, however, the sar3 increm ent or decrement value is +4, ?4, or fixed to 0 regardless of the transfer data size specified in ts1 and ts0.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 391 of 1036 rej09b0254-0600 bits 11 to 8?resource 3 to 0 (rs3 to rs0): rs3 to rs0 specify which transfer requests will be sent to the dmac. bit 11: rs3 bit 10: rs2 bit 9: rs1 bit 8: rs0 description 0 0 0 0 external request * 1 , dual address mode (initial value) 1 illegal setting 1 0 external request * 1 /single address mode external address space external device with dack 1 external request * 1 /single address mode external device with dack external address space 1 0 0 auto request 1 illegal setting 1 0 illegal setting 1 illegal setting 1 0 0 0 select dma request expansion * 3 1 illegal setting 1 0 illegal setting 1 illegal setting 1 0 0 scif transmission * 2 1 scif reception * 2 1 0 internal a/d * 2 1 cmt * 2 notes: 1. external request specification is valid only for channels 0. none of the request sources can be selected for channels 1, 2 and 3. 2. when using 16-byte transfer, the following settings must not be made: 1100 scif transmission 1101 scif reception 1110 a/d converter 1111 cmt operation is not guaranteed if these settings are made. 3. when dma transfer is provided with t he usb function controller or siof, set rs3 to rs0 to 1000 and select a desired module with the chrar register.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 392 of 1036 rej09b0254-0600 bit 6? dreq select (ds): ds selects the sampling method of the dreq pin that is used in external request mode is detection in low level or at the falling edge. this bit is only valid in chcr0. this bit in chcr1, chcr2 and chcr3 is always read as 0 and should only be written with 0. also, it should be cleared to 0 (low-level detection) if an on-chip supporting module is specified as a transfer request source in channel 0. bit 6: ds description 0 dreq detected in low level (initial value) 1 dreq detected at falling edge bit 5?transmit mode (tm): tm specifies the bus mode when transferring data. bit 5: tm description 0 cycle steal mode (initial value) 1 burst mode bits 4 and 3?transmit size 1, 0 (ts1 and ts0): ts1 and ts0 specify the size of data to be transferred. bit 4: ts1 bit 3: ts0 description 0 0 byte size (8 bits) (initial value) 0 1 word size (16 bits) 1 0 longword size (32 bits) 1 1 16-byte unit (4 longword transfers) bit 2?interrupt enable (ie): setting this bit to 1 generates an interrupt request when the number of times of data transfers specified with dmatcr has completed (te = 1). bit 2: ie description 0 interrupt request is not generated even when data transfer ends by the specified count (initial value) 1 interrupt request is generated when data transfer ends by the specified count
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 393 of 1036 rej09b0254-0600 bit 1?transfer end (te): te is set to 1 when data transfer ends by the count specified in dmatcr. at this time, if the ie bit is set to 1, an interrupt request is generated. before this bit is set to 1, if data transfer ends due to an nmi interrupt, a dmac address error, or clearing the de bit or the dme bit in dmaor, this bit is not set to 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. bit 1: te description 0 data transfer does not end by the count specified in dmatcr (initial value) clear condition: writing 0 after te = 1 read at power-on reset or manual reset 1 data transfer ends by the specified count bit 0?dmac enable (de): de enables channel operation. bit 0: de description 0 disables channel operation (initial value) 1 enables channel operation if the auto request is specified in rs3 to rs0, tran sfer starts when this bit is set to 1. for an external request or an on-chip module request, transfer starts if a transfer request is generated after this bit is set to 1. clearing this bit during transfer can te rminate transfer. even if the de bit is set, transfer is not enabled when the te bit is 1, the dme bit in dmaor is 0, or the nmif bit or ae bit in dmaor is 1.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 394 of 1036 rej09b0254-0600 14.2.5 dma channel request assign register (chrar) the dma channel request assign register (chrar) is a 16-bit read/write registers that assign requests from usbf or siof to each dma channel, to each expanded dma. it is initialized to 0 at power-on reset, or in hardware standby mode or software standby mode. these register values are initialized to 0s after a power-on reset. the previous value is held in standby mode. bit: 15,14,13,12 11,10,9,8 ch3rid3 to ch0rid0 ch2rid3 to ch2rid0 initial value: 0 0 r/w: r/w r/w bit: 7,6,5,4 3,2,1,0 ch1rid3 to ch1rid0 ch0rid3 to ch0rid0 initial value: 0 0 r/w: r/w r/w bits 15 to 12 ?dma channel 3 request assign 3 to 0 (ch3rid3 to ch3rid0): these bits select dma requests from dma channel 3. bits 15 to 12: ch3rid3 to ch3rid0 description 0000 unused (initial value) 0001 usbf (usb function) reception req uests to the dma are selected from channel 3 0010 usbf (usb function) transmission requests to the dma are selected from channel 3 1001 siof reception requests to the dma are selected from channel 3 1010 siof transmission requests to the dma are selected from channel 3
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 395 of 1036 rej09b0254-0600 bits 11 to 8 ? dma channel 2 request assign 3 to 0 (ch2rid3 to ch2rid0): these bits select dma requests from dma channel 2. bits 11 to 8: ch2rid3 to ch2rid0 description 0000 unused (initial value) 0001 usbf (usb function) reception req uests to the dma are selected from channel 2 0010 usbf (usb function) transmission requests to the dma are selected from channel 2 1001 siof reception requests to the dma are selected from channel 2 1010 siof transmission requests to the dma are selected from channel 2 bits 7 to 4? dma channel 1 request assign 3 to 0 (ch1rid3 to ch1rid0): these bits select dma requests from dma channel 1. bits 7 to 4: ch1rid3 to ch1rid0 description 0000 unused (initial value) 0001 usbf (usb function) reception req uests to the dma are selected from channel 1 0010 usbf (usb function) transmission requests to the dma are selected from channel 1 1001 siof reception requests to the dma are selected from channel 1 1010 siof transmission requests to the dma are selected from channel 1 bits 3 to 0? dma channel 0 request assign 3 to 0 (ch0rid3 to ch0rid0): these bits select dma requests from dma channel 0. bits 3 to 0: ch0rid3 to ch0rid0 description 0000 unused (initial value) 0001 usbf (usb function) reception req uests to the dma are selected from channel 0 0010 usbf (usb function) transmission requests to the dma are selected from channel 0 1001 siof reception requests to the dma are selected from channel 0 1010 siof transmission requests to the dma are selected from channel 0
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 396 of 1036 rej09b0254-0600 14.2.6 dma operation register (dmaor) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? pr1 pr0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/(w) * r/(w) * r/w note: * only a write of 0 after a read of 1 is enabled for the ae and nmif bits. the dma operation register (dmaor) is a 16-bit read/write register that controls the dmac transfer mode. this register is initialized to 0 by a power-on reset. the previous values are held in standby mode. bits 15 to 10?reserved: these bits are always read as 0 and should only be written with 0. bits 9 and 8?priority mode 1, 0 (pr1 and pr0): pr1 and pr0 select the priority level between channels when transfer requests are gene rated for multiple channels simultaneously. bit 9: pr1 bit 8: pr0 description 0 0 ch0 > ch1 > ch2 > ch3 (initial value) 1 ch0 > ch2 > ch3 > ch1 1 0 ch2 > ch0 > ch1 > ch3 1 round-robin bits 7 to 3?reserved: these bits are always read as 0 and should only be written with 0.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 397 of 1036 rej09b0254-0600 bit 2?address error flag (ae): ae indicates that an addr ess error occurred during dma transfer. if this bit is set during data transfer, transfers on all channels are suspended. the cpu cannot write 1 to this bit. this bit can only be cleared by writing of 0 after reading of 1. bit 2: ae description 0 no dmac address error. dma transfer is enabled. (initial value) clear conditions: when this bit is written with 0 after it is read as 1 by a power-on reset by a manual reset 1 dmac address error. dma transfer is disabled. setting condition: when a dmac address error occurred bit 1?nmi flag (nmif): nmif indicates that an nmi interrupt occurred. this bit is set both in operating state and in halt state. th e cpu cannot write 1 to this bit. this bit can only be cleared by writing of 0 after reading of 1. bit 1: nmif description 0 no nmi input. dma transfer is enabled. (initial value) clear conditions: when this bit is written with 0 after it is read as 1 by a power-on reset by a manual reset 1 nmi input. dma transfer is disabled. setting condition: when an nmi interrupt is generated bit 0?dma master enable (dme): dme enables or disables dma transfer for all channels. if the dme bit and the de bit corresponding to eac h channel in chcr are set to 1, transfer is enabled in the corresponding channel. if this bit is cleared during transfer, transfer in all the channels can be terminated. even if the dme bit is set, transfer is not enable d when the te bit is 1 or the de bit is 0 in chcr, or the nmif bit is 1 in dmaor. bit 0: dme description 0 disable dma transfer for all channels (initial value) 1 enable dma transfer for all channels
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 398 of 1036 rej09b0254-0600 14.3 operation when a dma transfer request is generated, th e dmac starts the transfer according to the predetermined channel priority order. when a tr ansfer end condition is satisfied, it ends the transfer. three types of transfer requests can be, auto request, external request, and on-chip module request. for the dual address mode, the direct address transfer mode and indirect address transfer mode are supported. for the bus mode, th e burst mode or the cycle steal mode can be selected. 14.3.1 dma transfer flow when transfer conditions have been set to the dma source address registers (sar), dma destination address registers (dar), dma tran sfer count registers (dmatcr), dma channel control registers (chcr), and dma operation re gister (dmaor), the dmac transfers data according to the following procedure: 1. checks that transfer is enabled (de = 1, dme = 1, ae = 0, te = 0, nmif = 0) 2. when transfer is enabled and a transfer reque st is generated, the dmac transfers 1 transfer unit of data (set with the ts0 and ts1 bits). in auto request mode, the transfer operation begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented on each transfer. th e actual transfer flows vary according to the address mode and bus mode. 3. when the specified number of transfers have been completed (when dmatcr reaches 0), the transfer operation ends normally. if the ie bit in chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an nmi interrupt is generated, the transfer operation is aborted. th e transfer operation is also aborted when the de bit in chcr or the dme bit in dmaor is changed to 0. figure 14.2 shows a flowchart of this procedure.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 399 of 1036 rej09b0254-0600 normal end does ae = 1 or nmif = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor) transfer (1 transfer unit); dmatcrd1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and ae, nmif, te = 0? does ae = 1 or nmif = 1 or de = 0 or dme = 0? transfer end notes: 1. in auto-request mode, transfer begins when ae, nmif and te are all 0 and the de and dme bits are set to 1. 2. dreq = level detection in burst mode (external request) or cycle-steal mode. 3. dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 14.2 dmac transfer flowchart
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 400 of 1036 rej09b0254-0600 14.3.2 dma transfer requests dma transfer requests are basically generated in e ither the data transfer so urce or destination, but they can also be generated by devices and on-chip supporting modules that are neither the source nor the destination. there are three types of transf er requests, an auto request, an external request and an on-chip module request. the request mode is selected with the rs3 to rs0 bits in the dma channel control registers 0 to 3 (chcr0 to chcr3). auto-request mode: when no transfer request signal is in put from an external source, such as transfer between memories or between memory and an on-chip supporting module on which a transfer request is disabled, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits in chcr0 to chcr3 and the dme bit in dmaor are set to 1, a transfer is started. at this time, the te bits in chcr0 to chcr3 and the nmif bit in dmaor should be all 0. external request mode: a transfer is started by the transfer request signal ( dreq ) from an external device. choose one of the modes shown in table 14.3 according to the application system. if dreq is input when the dma transfer is enable d (de = 1, dme = 1, te = 0, nmif = 0), a dma transfer starts. select whether dreq is detected on the falling edge or low level with the ds bit in chcr0 (level detection when ds = 0, edge detection when ds = 1). the source of the transfer request does not have to be the data transfer source or destination. table 14.3 selecting external request modes with the rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 0 0 dual address mode arbitrary * arbitrary * 1 0 single address mode external memory, memory-mapped external device external device with dack 1 external device with dack external memory, memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, on-chip supporting module (excluding dmac, ubc, and bsc) on-chip module request mode: a transfer is starte d by the transfer request signal (interrupt request signal) from an on-chip supporting module. this mode cannot be set in case of 16-byte transfer. there are eight types of transfer request signals, a receive data full interrupt (rxi) and a transmit data empty interrupt (txi) from the serial communication interface (scif), an a/d conversion end interrupt (adi) from the a/d conve rter, an compare-match timer interrupt (cmi)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 401 of 1036 rej09b0254-0600 from cmt, a transmit request (tdreq) and a receive request (rdreq) from sior, and a transmit request (dreqn1) and a receive reque st (dreqn0) from usbf. tdreq, rdreq, dreqn1, and dreqn0 are supported for expansion. when the dma transfer is enabled (de = 1, dme = 1, te = 0, and nmif = 0) in this mode, a transfer is started by the transfer request signal input. the source of the transfer request does not have to be the data transfer source or destination. when rxi2 is set as a transfer request, however, the transfer source must be the scif's receive data register (rdr2). likewise, when txi2 is set as a transfer request, the transfer source must be the scif's transmit data register (tdr2). in a ddition, when the transfer requester is the a/d converter, the data transfer source mu st be the a/d data register (addr). table 14.4 selection of on-chip module request modes using rs3 to rs0 bits rs3 rs2 rs1 rs0 dma transfer request source dma transfer request signal source destination bus mode 1 0 0 0 expansion usbf receiver dreqn[0] (dma transfer request output) epdr1 arbitrary * cycle steal usbf transmitter dreqn[1] (dma transfer request output) arbitrary * epdr2 cycle steal siof receiver rdreq (receive-data transfer request) sirdr arbitrary * cycle steal siof transmitter tdrq (transmit-data transfer request) arbitrary * sitdr cycle steal 1 0 0 scif transmitter txi2 (scif transmit data empty interrupt) arbitrary * tdr2 cycle steal 0 1 scif receiver rxi2 (scif receive data full interrupt) rdr2 arbitrary * cycle steal 1 0 a/d converter adi (a/d conversion end interrupt) addr arbitrary * cycle steal 1 1 cmt cmi (compare-match timer interrupt) arbitrary * arbitrary * burst/ cycle steal note: * external memory, memory-mapped external device, on-chip supporting module (excluding dmac, bsc, ubc)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 402 of 1036 rej09b0254-0600 in order to output a transfer request from an on-chip supporting module, set the corresponding interrupt enable bit for outputting the interrupt signal. when the interrupt request signal from an on-chip supporting module is used as a dma transfer request signal, an interrupt is not generated to the cpu. the dma transfer request signal s shown in table 14.4 are auto matically canceled when the corresponding dma transfer is completed. this opera tion is provided at the first transfer in cycle steal mode, and at the last transfer in burst mode. 14.3.3 channel priority when the dmac receives multiple transfer requests simultaneously, it provides transfer operation according to a specified priority order. the fixed mode or round- robin mode can be selected for the channel priority with the pr1 and pr0 b it in the dma operation register (dmaor). fixed mode: the channel priority is fixed. there are three kinds of orders as follows: ch0 > ch1 > ch2 > ch3 ch0 > ch2 > ch3 > ch1 ch2 > ch0 > ch1 > ch3 the priority is selected by the pr1 and pr0 bits in the dma operation register (dmaor). round-robin mode: the priority order is rotated each tim e one transfer unit (word, byte, or longword) of data has been transferred. the channel on which the transfer was just finished is located at the lowest in priority. the round-robin mode operation is shown in figure 14.3. the priority of the round-robin mode is ch0 > ch1 > ch2 > ch3 immediately after a reset.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 403 of 1036 rej09b0254-0600 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 (1) when channel 0 transfers initial priority order initial priority order initial priority order priority order afrer transfer priority order afrer transfer initial priority order channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were higher than channel 1, are also shifted. channel 0 becomes bottom priority. the priority of channel 0, which was higher than channel 3, is also shifted. channel 0 becomes bottom priority priority order afrer transfer priority order afrer transfer priority order afrer transfer post-transfer priority order when there is an immediate transfer request to channel 1 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 3 transfers figure 14.3 operation in round-robin mode
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 404 of 1036 rej09b0254-0600 figure 14.4 shows how the priority order changes when transfer requests for channel 0 and channel 3 are generated simultaneously and a transfer request for channel 1 is requested during the channel 0 transfer. the dm ac operates as follows: 1. transfer requests are generated simultaneously for channels 0 and 3. 2. channel 0 has the higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 has the lowest priority. 5. at this time, channel 1 has the higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 has the lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority order so that channel 3 has the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 14.4 channel priority order in round-robin mode
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 405 of 1036 rej09b0254-0600 14.3.4 dma transfer types the dmac supports the transfer s shown in table 14.5. the dual address mode comprises the direct address mode and indirect address mode. in the direct address mode, an output address value is the data transfer target address. in the indirect address m ode, the value stored in the output address, not the output address value itself, is the data transfer target addr ess. the data transfer timing differs depending on the bus mode. the bus mode comprises the cycle steal mode and burst mode. table 14.5 dma transfers destination source external device with dack external memory memory- mapped external device on-chip supporting module xy memory external device with dack not available dual, single dual, single not available not available external memory dual, single dual dual dual dual memory-mapped external device dual, single dual dual dual dual on-chip supporting module not available dual dual dual dual x/y memory not available dual dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. the dual address mode includes the di rect address mode and the indirect address mode. 4. 16-byte transfer is not available for on-chip supporting modules. address mode: ? dual address mode in the dual address mode, the tr ansfer source and destination are accessed by addresses. both external and internal addresses can be used for th e transfer source or des tination. the dual address mode consists of the direct address transfer mode (1) and indirect address transfer mode (2).
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 406 of 1036 rej09b0254-0600 (1) direct address transfer mode dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in th e transfer between external memories as shown in figure 14.5, data is read from one external memory to the dmac in a data read cycle, and then that data is written to the other external memory in a write cycle. figures 14.6 to 14.8 show examples of this operation timing data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar data is read from the transfer source module using the sar value as the address, and the read data is stored in the dmac temporarily. first bus cycle second bus cycle the value stored in the dmac is written to the transfer destination module using the dar value as the address. dmac dmac figure 14.5 operation in direct address mode
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 407 of 1036 rej09b0254-0600 (1st cycle) (2nd cycle) data read cycle data write cycle transfer source address transfer destination address ckio a25 to a0 csn d31 to d0 rd wen dackn note: when dack is output in a read cycle during transfer between external memories, the output timing is the same as that of csn . figure 14.6 example of dma transfer timing in the direct address mode (transfer source: ordinary memory, tr ansfer destination: ordinary memory)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 408 of 1036 rej09b0254-0600 transfer source address +4 +8 +12 transfer destination address +4 +8 +12 data read cycle (1st cycle) (2nd cycle) a25 to a0 ckio csn rd wem dack d31 to d0 note: when dack is output in a read cycle during transfer between external memories, the output timing is the same as that of csn . figure 14.7 example of dma transfer timing in the direct address mode (16-byte transfer, transfer source: ordinary memory, transfer destination: ordinary memory) transfer source address transfer destination address +4 +8 +12 a25 to a0 ckio csn ras cas rd/ wr dack d31 to d0 data read cycle (1st cycle) (2nd cycle) data write cycle note: when dack is output in a read cycle during transfer between external memories, the output timing is the same as that of csn . figure 14.8 example of dma transfer timing in the direct address mode (16-byte transfer, transfer source: synchronous dram, transfer destination: ordinary memory)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 409 of 1036 rej09b0254-0600 (2) in the indirect address transfer mode the address of the memory in which data to be tr ansferred is stored is specified in the transfer source address register (sar3) in the dmac. 16-byte transfer is not provided in this mode. the address value specified in the transfer source address register in the dmac is read first, and this value is temporarily stored in the dmac. next, the read value is output as an address, and data on that address is stored in in the dm ac again. then, the value read afterwards is written to the address specified by the transfer destination address register; thus one dma transfer is completed. figure 14.9 shows an example of this operation. in this exam ple, the transfer destination, transfer source, and storage destination of the i ndirect address are all in external memories, and the transfer data size is 16 or 8 bits. figure 14.10 shows an example of the transfer timing. in this mode, one nop cycle (ck1 cycle shown in figure 14.10) is required to output data which was read as an indirect address to an address bus. for a 32-bit data transfer, third and fourth bus cycles shown in figure 14.10 are required twice for each; a total of six bus cycles and one nop cycle are required.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 410 of 1036 rej09b0254-0600 memory transfer source module transfer destination module sar3 dar3 data buffer temporary buffer d m a c data is read from memory using the sar3 value as the data address, and the read data is stored in the temporary buffer. the read data must be a 32-bit value because it is used as an address. two bus cycles are required if a 16-bit data bus is used to connect to an external device. memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c memory transfer source module data bus address bus transfer destination module sar3 dar3 data buffer temporary buffer d m a c first and second bus cycles data is read from the source module using the temporary buffer value as the address, and the read data is transferred to the data buffer. third bus cycle fourth bus cycle the data buffer value is written to the destination module using the dar3 value as the destination address. the above description uses the memory, transfer source module, or transfer destination module; in practice, any module can be connected in the addressing space. note: data bus address bus figure 14.9 operation in indirect address mode (when the external memory space is set to 16-bit width)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 411 of 1036 rej09b0254-0600 ck a25 to a0 csn d31 to d0 internal address bus internal data bus dmac indirect address buffer dmac data buffer rd wen (1st) (2nd) (3rd) nop cycle data read cycle (4th) data write cycle notes: 1. the internal address bus value does not change, and controlled by the port. 2. the dmac does not fetch the value until 32-bit data is output to the internal data bus. address read cycle transfer source address (h) transfer source address (l) indirect address nop transfer desti- nation address indirect address (h) indirect address (l) transfer data transfer data nop transfer source address * 1 transfer data transfer data transfer source address * 2 transfer data indirect address indirect address transfer between external memories (external memories is 16-bit bus width) figure 14.10 example of transfer timing in indirect address mode (transfer between external memories, ex ternal memory with 16-bit width)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 412 of 1036 rej09b0254-0600 ? single address mode the single address mode is used when transfer is performed between external devices including external memories, one of which is accessed (s elected) by the dack signal and the other of which is accessed by address. in this mode, the dmac outputs the transf er request acknowledge signal dack to one external device, and simultaneously outputs an address to the other device; thus dma transfer is performed in one bus cycle. an example of transfer between an external memory and an external device with dack is show n in figure 14.11. th e external device outputs data to a data bus and the data is written to the external memory in a single bus cycle. dmac SH7727 dack dreq external address bus external data bus external memory external device with dack data flow figure 14.11 data flow in single address mode two kinds of transfer are possible in single address mode: (1) transf er between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and an external memory. in both cases, only the extern al request signal ( dreq ) is used as a transfer request. figures 14.12 and 14.13 show examples of the dma transfer timing in single address mode.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 413 of 1036 rej09b0254-0600 address output to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space external device with dack (active-low) ck a25 to a0 d31 to d0 dackn csn we bs ck a25 to a0 d31 to d0 dackn csn rd bs figure 14.12 example of dma transf er timing in single address mode
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 414 of 1036 rej09b0254-0600 ckio a25 to a0 d31 to d0 rd wen dackn csn transfer source address +4 +8 +12 figure 14.13 example of dma transf er timing in single address mode (external memory space (ordinary memory) external device with dack) bus modes: there are two types of bus modes, cycle st eal mode and burst mode. select the mode in the tm bits in chcr0 to chcr3. ? cycle-steal mode in the cycle-steal mode, the bus right is moved to another bus master after one transfer unit (byte, word, longword, or 16-byte unit) of dma transfer. if another transfer request occurs after the bus right moving, the bus right are re-moved to the dmac. then, the dmac performs transfer for one transfer unit and releases the bus right again. this operation is repeated until the transfer end condition is satisfied. in the cycle-steal mode, transfer areas are not aff ected by settings of the transfer request source, transfer source, and transfer destination. figu re 14.14 shows an example of the dma transfer timing in the cycle steal mode. in this example, the following conditions are set: ? dual address mode ? dreq level detection
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 415 of 1036 rej09b0254-0600 cpu cpu cpu dmac dmac cpu dmac dmac cpu cpu dreq bus cycle bus right returned to cpu read write write read figure 14.14 transfer example in cycle-steal mode ? burst mode once the dmac obtains the bus right, the transfer is continued until the transfer end condition is satisfied. however, when the dreq pin is driven high in the external request mode with low level detection of the dreq pin, the bus right is passed to the other bus master after the dma transfer request that has already been accepted ends, even if the transfer end condition has not been satisfied. the burst mode cannot be used when the tran sfer request source is set to the serial communications interface with fifo (scif). figu re 14.15 shows a timing of the dma transfer operation in the burst mode. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 14.15 example of transfer in burst mode relationship between request mode and bus mode: table 14.6 shows the relationship between request mode and bus mode for each co mbination of dma transfer areas.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 416 of 1036 rej09b0254-0600 table 14.6 relationship of request modes and bus modes address mode transfer areas request mode bus mode transfer size (bits) usable channels dual external device with dack and external memory external b/c 8/16/32/128 0 external device with dack and memory-mapped external device external b/c 8/16/32/128 0 external memory and external memory all * 1 b/c 8/16/32/128 0?3 * 5 external memory and memory- mapped external device all * 1 b/c 8/16/32/128 0?3 * 5 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0?3 * 5 external memory and on-chip supporting module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 memory-mapped external device and on-chip supporting module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 on-chip supporting module and on- chip supporting module all * 2 b/c * 3 8/16/32 * 4 0?3 * 5 x/y memory and x/y me mory all b/c 8/16/32/128 0?3 x/y memory and memory-mapped external device all * 1 b/c 8/16/32/128 0?3 x/y memory and on-chip supporting module all * 2 b/c * 3 8/16/32 0?3 x/y memory and external memory all b/c 8/16/32/128 0?3 single external device with dack and external memory external b/c 8/16/32/128 0 external device with dack and memory-mapped external device external b/c 8/16/32/128 0 b: burst c: cycle steal notes: 1. external requests, auto requests and on-chip supporting module (cmt) requests are all available. 2. external requests, auto requests and on-chip supporting module requests are all available. when the siof, usbf, scif, or a/ d converter is the transfer request source, the transfer destination or transfer source must be also the siof, usbf, scif, or a/d converter, respectively. 3. the siof, usbf, scif, or a/d converte r can be specified for the transfer request source in the cycle-steal mode only. 4. the access size permitted when the transfer destination or source is an on-chip supporting module register. 5. if the transfer request is an external request, only channel 0 is available.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 417 of 1036 rej09b0254-0600 bus mode and channel priority order: for example, when chan nel 1 provides transfer operation in burst mode and then a transfer reque st to channel 0 with the higher priority is generated, the transfer of chan nel 0 will begin immediately. at this time, if the priority is set in the fixe d mode (ch0 > ch1), the ch annel 1 transfer will be continued after the channel 0 transfer has completely finished, even if channel 0 is set to the cycle steal mode or burst mode. if the round-robin mode is selected, channel 1 w ill begin operating again after channel 0 completes the transfer of one transf er unit, even if channel 0 is set to the cycle steal mode or burst mode. the bus is moved between the two in the order channel 1, channel 0, channel 1, channel 0. even if the fixed mode or in the round-robin mode is selected, the bus is not passed to the cpu since channel 1 is in the burst mode. figure 14.16 shows an example of operation in the round- robin mode. cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu ch0 ch1 ch0 round-robin mode in dmac ch0 and ch1 dmac ch1 burst mode cpu cpu priority: round-robin mode ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 14.16 bus state in multiple channel operation
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 418 of 1036 rej09b0254-0600 14.3.5 number of bus cycle states and dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in th e same way as when the cpu is the bus master. for details, see section 12, bus state controller (bsc). dreq pin sampling timing: in external request mode, the dreq pin is sampled with the clock pulse (ckio) falling edge detection or low level detection. when a dreq input is detected, a dmac bus cycle is generated and dma transf er starts three or more states later. the second and subsequent dreq sampling operations are started two cycles after the first sample. operation ? cycle-steal mode in cycle-steal mode, the dreq sampling timing does not change according to the dreq detection method, the level detection or edge detection. for example, as shown in figure 14.17 (cycle-steal mode, level detection), dma transfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. if dreq is not detected at this time, sampling is performed in each subsequent cycle. thus, dreq sampling is performed one step in advance. the third sampling operation is not performed until the idle cycle following the end of the first dma transfer. the above operation is performed continuously for the desired cpu transfer cycles or dma transfer cycles, as shown in figures 14.18 and 14.19. figures 14.17 and 14.18 show examples in which dack is output in a read and in a write, respectively. in both cases, dack is output for the same period as csn . figure 14.20 shows an example in which sampling is executed in all subsequent cycles when dreq cannot be detected. figure 14.21 shows an example of operation in cycle steal mode with the edge detection.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 419 of 1036 rej09b0254-0600 ? burst mode, level detection in the case of burst mode with level detection, the dreq sampling timing is the same as in the cycle-steal mode. for example, as shown in figure 14.22, dmac tr ansfer begins, at the earliest, three cycles after the first sampling is performed. the second sampling is started two cycles after the first. subsequent sampling operations are performed in the idle cycle following the end of the dma transfer cycle. in the burst mode, also, the dack output period is the same as that in the cycle-steal mode. ? burst mode, edge detection in the case of burst mode with edge detection, dreq sampling is performed only once. for example, as shown in figure 14.23, dmac tr ansfer begins, at the earliest, three cycles after the first sampling is performed. after this , dmac transfer is executed continuously until the number of data transfers set in th e dmatcr register have been completed. dreq is not sampled during this operation. to restart dma transfer after it has been suspended by an nmi, first clear nmif, then input an edge request again. in the burst mode, also, the dack output period is the same as that in the cycle-steal mode.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 420 of 1036 rej09b0254-0600 ckio drak dreq dack bus cycle dmac(r) cpu dmac(w) dmac(r) cpu dmac(w) 1st sampling 2nd sampling 3rd sampling figure 14.17 cycle-steal mode, le vel input (cpu access: 2 cycles)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 421 of 1036 rej09b0254-0600 cpu cpu ckio drak dreq dack dmac(r) dmac(w) dmac(r) 1st sampling 2nd sampling 3rd sampling bus cycle figure 14.18 cycle-steal mode, le vel input (cpu access: 3 cycles)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 422 of 1036 rej09b0254-0600 ckio drak (high output) bus cycle dreq dack (rd output) dmac(w) cpu dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 14.19 cycle-steal mo de, level input (cpu access: 2 cycles, dma rd access: 4 cycles)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 423 of 1036 rej09b0254-0600 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu 3rd sampling is performed, but since dreq is high, per-cycle sampling starts 2nd sampling is performed, but since dreq is high, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling figure 14.20 cycle-steal mode, le vel input (cpu access: 2 cycles, dreq input delayed)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 424 of 1036 rej09b0254-0600 ckio drak bus cycle dreq dack (rd output) cpu cpu dmac(w) dmac(r) dmac(w) dmac(r) cpu high high high high 2nd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts 3rd sampling is performed, but since there is no dreq falling edge, per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling note: when a dreq falling edge is detected, dreq must be high for at least one cycle before the sampling point. figure 14.21 cycle-steal mode, ed ge input (cpu access: 2 cycles)
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 425 of 1036 rej09b0254-0600 ckio drak dreq dack bus cycle dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) cpu 1st sampling 2nd sampling 3rd sampling figure 14.22 burst mode, level input
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 426 of 1036 rej09b0254-0600 ckio drak dreq dack bus cycle cpu dmac(r) dmac(w) dmac(r) dmac(w) dmac(r) 1st sampling figure 14.23 burst mode, edge input
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 427 of 1036 rej09b0254-0600 14.3.6 source address reload function channel 2 includes a reload function, in which the value set in the source address register (sar2) is restored every four transfers when the ro bit in chcr2 is set to 1. this function cannot be used with the 16-byte transfer. figure 14.24 shows this operation. figure 14.25 shows a timing chart of the source address reload function with the following conditions: burst mode, auto request, 16-bit transfer data size, sar2 count-up, dar2 fixed, reload function on, and usage of only channel 2. sar2 (initial value) dmac transfer request dmac control reload control 4 time count chcr2 dmatcr2 sar2 ro bit = 1 count signal reload signal reload signal address bus figure 14.24 source address reload function diagram
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 428 of 1036 rej09b0254-0600 ck internal address bus internal data bus sar2 dar2 dar2 dar2 dar2 sar2+2 sar2+4 sar2+6 sar2 sar2 data sar2+2 data sar2+4 data sar2+6 data first transfer of channel 2 second transfer third transfer fourth transfer fifth transfer sar2 output dar2 output sar2+2 output dar2 output sar2+4 output dar2 output sar2+6 output dar2 output sar2 reload sar2 output dar2 output figure 14.25 timing chart of source address reload function the reload function can be used for the 8-, 16- and 32-bit data transfer. dmatcr2, which specifies a transfer count, is incremented by 1 each time a transfer ends regardless of the reload function setting. consequently, be sure to specify the value multiple of four in dmatcr2 when the reload function is on. if other values are spec ified, correct operation is not guaranteed. the counters that count transfers of four times for the reload function are reset by clearing the dme bit in dmaor or the de bit in chcr2, by setting the transfer end fl ag (te bit in chcr2), by inputting an nmi, besides by a reset or in standby mode. however, the sar2, dar2, dmatcr2 registers are not reset. therefore, the above reset source is generated, some counters are initialized but some are not in the dmac, which may cause a malfunction when the dmac is restarted. to avoid this problem, if a reset so urce except the te bit setting is generated when the reload function is used, set sar2, dar2, and dmatcr2 again.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 429 of 1036 rej09b0254-0600 14.3.7 dma transfer ending dma transfer ending conditions to terminate transfer differ according to the ending types, individual channel ending and all channel ending. at a transfer end, the following conditions are applied except the case when the dma transfer count register (dmatcr) value reaches 0. (a) cycle-steal mode (external request, internal request, and auto request) when a transfer ending condition is satisfied, dm ac transfer request acceptance is suspended. the dmac stops operation after completing the number of transfers that has accepted before the ending conditions are satisfied. in the cycle-steal mode, the same operation is provided regardless of the transfer request detection method; the level detection or the edge detection. (b) burst mode, edge detection (external requ est, internal request, and auto request) the timing of dmac operation ending after an ending condition is satisfied differs from that in cycle steal mode. in the edge detection in the burst mode, though only one transfer request is generated at the dmac start-up, a stop request sampling is performed in the same timing as a transfer request sampling in the cycle-steal mode . as a result, the period when a stop request is not sampled is regarded as the period when a transfer request is generated, and after performing the dma transfer for this period, the dmac stops operation. (c) burst mode, level detection (external request) same as described in (a). (d) bus timing when transfers are suspended transfer is suspended when one tr ansfer ends. even if a transf er ending condition is satisfied during a read with the direct address transfer in the dual ad dress mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, dmac operation suspends.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 430 of 1036 rej09b0254-0600 conditions for individual-channel ending: when one of the following conditions is satisfied, transfer in the corres ponding channel ends. when the value in the dma transfer count register (dmatcr) is 0 when the de bit in chcr is cleared to 0. ? when dmatcr is 0: when the dmatcr value reaches 0, the dma transfer in the corresponding channel ends and the transfer end flag bit (te) in chcr is set. if the ie (interrupt enable) bit is set at this time, a dm ac interrupt (dei) is requested to the cpu. the conditions described in (a) to (d) above are not applied for this transfer ending. ? when de in chcr is 0: when the de bit in chcr is cleared, the dma transfer in the corresponding channel stops. the conditions descri bed in (a) to (d) above are not applied for this transfer ending. conditions for all- channel ending: when one of the following conditions is satisfied, transfer in all channels end simultaneously. when the nmif (nmi flag) bit in dmaor is set to 1 when the dme bit in dmaor is cleared to 0. ? when the nmif bit in dmaor is set to 1: when an nmi interrupt occurs, the nmif bit in dmaor is set to 1 and all channels stop their tr ansfers according to the conditions in (a) to (d) described above, and pass the bus right to another bus master. consequently, even if the nmi bit is set to 1 during transfer, the sar, dar , dmatcr are updated. then the te bit is not set. to resume the transfer after the nmi interr upt exception handling, clear the nmif bit to 0. at this time, for the channels that should not be restarted, clear the corresponding de bit in chcr. ? when dme is cleared to 0 in dmaor: clearing the dme bit to 0 in the dmaor forcibly aborts the transfers on a ll channels. then the te bit is not set. all channels abor t their transfers according to the conditions (a) to (d) described in section 14.3.7, dmac transfer ending, in the same way as that at the generation of an address error by the dmac or nmi interrupt generation. in this case, the values in sar, dar, and dmatcr are also updated.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 431 of 1036 rej09b0254-0600 14.4 compare-match timer (cmt) 14.4.1 overview the dmac has an on-chip compare-match timer (c mt) to generate dma transfer requests. the cmt is 16-bit counter. features the cmt has the following features: ? four types of counter input clocks can be selected ? one of four internal clocks (p /4, p /8, p /16, and p /64) can be selected. ? generates a dma transfer request when a compare-match occurs. block diagram figure 14.26 shows a cmt block diagram. internal bus bus interface control circuit clock selection cmstr cmcsr0 cmcor0 comparator cmcnt0 module bus cmt p /4 p /8 p /16 p /64 cmstr: cmcsr0: cmcor0: cmcnt0: compare match timer start register compare match timer control/status register 0 compare match timer constant register 0 compare match timer counter 0 figure 14.26 cmt block diagram
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 432 of 1036 rej09b0254-0600 register configuration table 14.7 summarizes the cm t register configuration. table 14.7 register configuration name abbreviation r/w initial value address access size (bits) compare-match timer start register cmstr r/(w) h'0000 h'04000070 (h'a4000070) * 2 8, 16, 32 compare-match timer control/status register 0 cmcsr0 r/(w) * 1 h'0000 h'04000072 (h'a4000072) * 2 8, 16, 32 compare-match counter 0 cmcnt0 r/w h'0000 h'04000074 (h'a4000074) * 2 8, 16, 32 compare-match constant register cmcor0 r/w h'ffff h'04000076 (h'a4000076) * 2 8, 16, 32 notes: 1. only a 0 can be written to cmf bits in cmcsr0, to clear the flag. 2. when the address conversion by the mmu is not provided, use the address in parentheses. 14.4.2 register descriptions compare-match timer start register (cmstr) the compare-match timer start register (cmstr) is a 16-bit register that selects whether compare- match counter 0 (cmcnt0) is operated or halted. cmstr is initialized to h'0000 by a reset, but it retains its previous values in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bits 15 to 2?reserved: these bits are always read as 0 and should only be written with 0.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 433 of 1036 rej09b0254-0600 bit 1?reserved: this is a readable/writable bit, but the write value should be always be 0. bit 0?count start 0 (str0): selects whether the compare-match timer counter 0 is operated or halted. bit 0: str0 description 0 cmcnt0 count operation is halted (initial value) 1 cmcnt0 count operation is provided compare-match timer control/s tatus register 0 (cmcsr0) the compare-match timer control/status register 0 (cmcsr0) is a 16-bit regi ster that indicates a compare-match occurrence and sets the incrementation clock. cmcsr0 is initialized to h'0000 by a reset, but it retains its previous values in standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf ? ? ? ? ? cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r r r r r/w r/w note: * only a 0 can be written, to clear the flag. bits 15 to 8 and 5 to 2?reserved: these bits are always read as 0and should only be written with 0. bit 7?compare-match flag (cmf): this flag indicates that a compare-match of the compare- match timer counter 0 (cmcnt0) and compare-match constant register 0 (cmcor0) occurred. bit 7: cmf description 0 cmcnt0 and cmcor0 have not matched (initial value) clear condition: write 0 to cmf after reading cmf = 1 1 a compare-match of cmcnt0 and cmcor0 occurred bit 6?reserved: this is a readable/writable bit, but the write value should be always be 0.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 434 of 1036 rej09b0254-0600 bits 1 and 0?clock select 1, 0 (cks1, cks0): these bits select the clock input to cmcnt from four clocks which are divided from the peripheral clock (p ). when the str0 bit in cmstr is set to 1, the cmcnt0 starts incrementati on with the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 0 0 p /4 (initial value) 1 p /8 1 0 p /16 1 p /64 compare-match counter 0 (cmcnt0) the compare-match counter 0 (cmcnt0) is a 16-b it register that is used as an up-counter. when the clock is selected with the cks1 and cks0 bits in cmcsr0 and the str0 bit in cmstr is set to 1, cmcnt0 starts incrementati on with the selected clock. when the cmcnt0 value matches that in the compare-match constant register 0 (cmcor0), the cmcnt0 is cleared to h'0000 and the cmf flag in cmcsr0 is set to 1. cmcnt0 is initialized to h'0000 by a reset, but it retains its previous values in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 435 of 1036 rej09b0254-0600 compare-match constant register 0 (cmcor0) the compare-match constant register 0 (cmcor0) is a 16-bit register that sets the period until a compare-match of cmcnt0 and cmcor0 occurs. the cmcor0 is initialized to h'ffff by a reset, but it retains its previous values in standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 14.4.3 operation period count operation when the clock is selected with the cks1 and cks0 bits in cmcsr0 and the str0 bit in cmstr is set to 1, the cmcnt0 starts increm entation with the selected clock. when the cmcnt value matches that in cmcor0, cmcnt0 is cleared to h'0000 and the cmf flag in cmcsr0 is set to 1. the cmcnt0 counter starts incrementation again from h'0000. figure 14.27 shows the compare-match counter operation. counter cleared by cmcor0 compare match cmcnt0 value cmcor0 h'0000 time figure 14.27 counter operation
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 436 of 1036 rej09b0254-0600 cmcnt0 count timing one of four peripheral clocks (p /4, p /8, p /16, p /64) which are divided from the clock (p ) can be selected with the cks1 and cks0 bits in cmcsr0. figure 14.28 shows the timing. n+1 peripheral clock (p ) cmt clock cmcnt0 input clock cmcnt0 n-1 n figure 14.28 count timing 14.4.4 compare-match compare-match flag set timing when the cmcor0 register an d the cmcnt0 counter match, a compare-match signal is generated and the cmf bit in the cmcsr0 regist er is set to 1. the compare-match signal is generated upon the final state of the match (timing at which the cmcnt0 counter value is updated). consequently, after the cmcor0 regist er and the cmcnt0 counter match, a compare- match signal will not be generated until a cmcnt0 counter input clock occurs. figure 14.29 shows a timing of the cmf bit setting.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 437 of 1036 rej09b0254-0600 peripheral clock (p ) cmcor0 cmcnt0 input clock compare match signal cmf cmi cmcnt0 n n 0 figure 14.29 timing of cmf setting compare-match flag clear timing the cmf bit in the cmcsr0 register is cleared by writing 0 to the bit after reading 1. figure 14.30 shows the timing when the cmf bit is cleared by the cpu. peripheral clock (p ) cmf cmcsr0 write cycle t 1 t 2 figure 14.30 timing of cmf clear by the cpu
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 438 of 1036 rej09b0254-0600 14.5 examples for use 14.5.1 example of dma transfer between a/d converter and external memory (address reload on) in this example, dma transfer is performed between the on-chip a/d converter (transfer source) and the external memory (transfer destination) with the address reload function on. table 14.8 shows the transfer conditi ons and register settings. table 14.8 transfer conditions and register settings for transfer between on-chip a/d converter and ex ternal memory transfer conditions register setting transfer source: on-chip a/d converter sar2 h'04000080 transfer destination: external memory dar2 h'00400000 number of transfers: 128 (reloading 32 times) dmatcr2 h'00000080 transfer source address: incremented chcr2 h'00089e35 transfer destination address: decremented transfer request source: a/d converter bus mode: burst transfer unit: long word interrupt request generated at end of transfer channel priority order: 0 > 2 > 3 > 1 dmaor h'0101 when the address reload function is turned on, the value set in sar returns to the initially set value at each four transfers. in this example, when an interrupt request is generated from the ad converter, longword data is read from the register in address h'04000080 of the a/d converter, and the data is written to external memory address h'00400000. since longword data has been transferred, the values in sar and dar are h'04 000084 and h'003ffffc, respectively. the bus right is retained and data transfers are successively performed because this transfer is in the burst mode. after four transfers end, fifth and sixth transfers are performed when the address reload function is turned off, and the value in sar is incremented by 4, such as h'0400008c, h'04000090, h'04000094,.... when the address reload function is on, the dma transfer stops after the fourth transfer ends and the bus request signal to the cpu is cleared. at this time, the value stored in sar is not incremented from h'0400008c to h'04000090, but returns to the initially set value h'04000080. the value in dar continues being incremented regardless of the address reload function setting.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 439 of 1036 rej09b0254-0600 the state in the dmac differ depending on the address reload function setting as shown in table 14.9. table 14.9 dmac sate after the fourth transfer ends items address reload on address reload off sar h'04000080 h'04000090 dar h'003ffffc h'003ffffc dmatcr h'0000007c h'0000007c bus right released held dmac operation stops continues operating interrupt not generated not generated transfer request source flag clear executed not executed notes: 1. when the value in dmatcr reaches 0 and the ie bit in chcr has been set to 1, interrupts are generated regardless of the address reload function setting. 2. when the value in dmatcr reaches 0, the transfer request source flag is cleared regardless of the address reload function setting. 3. specify the burst mode when using the ad dress reload function. this function may not be correctly executed in the cycle steal mode. 4. set the dmatcr value to a multiple of four when using the address reload function. this function may not be correctly execut ed if other values are specified. 14.5.2 example of dma transfer between external memory and scif transmitter (indirect address on) in this example, dma transfer is performed be tween the external memory specified with the indirect address (transfer source) and the scif transmitter (transfer destination) using dmac channel 3. table 14.10 shows th e transfer conditions and regist er settings. in addition, it is recommendable that the trigger fo r the number of transmit fifo da ta is set to 1 (ttrg1 = ttrg0 = 1 in scfcr).
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 440 of 1036 rej09b0254-0600 table 14.10 transfer conditions and register settings for transfer between external memory and scif transmitter transfer conditions register setting transfer source: external memory sar3 h'00400000 value stored in address h'00400000 ? h'00450000 value stored in address h'04500000 ? h'55 transfer destination: on-chip scif tdr2 dar3 h'04000156 number of transfers: 10 dmatcr3 h'0000000a transfer source address: incremented chcr3 h'00011c01 transfer destination address: fixed transfer request source: scif (txi2) bus mode: cycle steal transfer unit: byte no interrupt request generated at end of transfer channel priority order: 0 > 1 > 2 > 3 dmaor h'0001 when the indirect address is on, data stored in th e address set in sar is no t used as transfer source data. in the indirect address, after the value stored in the address set in sar is read, the read value is used as an address again, and the value stored in the address is read and stored in the address set in dar. in the example shown in table 14.10, when an scif transfer request is generated, the dmac reads the value in address h'00400000 that is set in sar3. since the value h'00450000 is stored in the address, the dmac reads the value h'00450000. next, the dmac uses the read value as an address again, and reads the value h'55 stored in that address. then, the dmac writes the value h'55 to address h'04000156 that is set in dar3; thus one indirect address transfer has completed. in the indirect address, when data is read first from the address set in sar3, the data transfer size is always longword regardless of the settings of the ts0 and the ts1 bits that specify the transfer data size. however, whether the transfer source ad dress is fixed, incremented, or decremented is specified with the sm0 and sm1 bits. therefore, in this example, though the transfer data size is specified as byte, the value in sar3 is h'0040000 4 when one transfer ends . the write operation is the same as that in the normal dual address transfer.
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 441 of 1036 rej09b0254-0600 14.6 usage notes 1. the dma channel control registers (chcr0 to chcr3) can be accessed with any data size. the dma operation register (dmaor) must be accessed in byte (8 bits ) or word (16 bits) units; other registers must be accessed in word (16 bits) or longwor d (32 bits) units. 2. when modifying the rs0 to rs3 bits in chcr0 to chcr3, first clear the de bit to 0 (when modifying chcr with a byte address, be sure to set the de bit to 0 in advance). 3. if an nmi interrupt is input when the dmac is not operating, the nmif bit of the dmaor is set. 4. a transition to standby mode should be made after the dme bit in dmaor is cleared to 0 and the transfers that has been acc epted by the dmac end. 5. the on-chip supporting modu les that the dmac can access are, siof, scif, usbf, a/d converter, d/a converter, and i/o ports. do not access the other on-chip supporting modules by the dmac. 6. when starting up the dmac, set chcr or dmaor last. specifying other registers last does not guarantee normal operation. 7. when the dma transfer ends normally and subsequently the maximum number of transfers is performed in the same channel, write 0 to dmatcr. otherwise, normal dma transfer may not be performed. 8. when using the address reload function, specify the burst mode for the transfer mode. in the cycle-steal mode, normal dma transf er may not be performed. 9. when using the address reload function, set a multiple of four to dmatcr. specifying other values does not guarantee normal operation. 10. when detecting an external request at the falling edge, keep the external request pin high when setting the dmac. 11. do not access the space from h'4000062 to h' 400006f, which is not used by the dmac. accessing that space may cause malfunctions. 12. the wait signal is ignored when writing to an external address area using dma 16-byte transfer in dual address mode, and also when transferring data from a dack-equipped external device to an external address ar ea using dma 16-byte transfer in single address mode. 13. big-endian access is used when transferring data from xy memory using the dmac if all of the following conditions are met: conditions: (1) transfer source address in xy memory (2) indirect addressing mode (3) byte size data (4) little-endian data transfer
section 14 direct memory access controller (dmac) rev.6.00 mar. 27, 2009 page 442 of 1036 rej09b0254-0600 measures to avoid the problem: the problem described above occurs only when all of the above conditions are met. it does not arise if even one of the conditions is no t met. one of the methods listed below should therefore be employed when using the dm ac to transfer data from xy memory: (1) use the direct address mode (2) use long word size or word size data (3) use big-endian data transfer 14. do not use the dmac when in sleep m ode. alternately, set the clock ratio to i :b = 1:1 when using sleep mode. normal operation cannot be guaranteed otherwise. 15. do not use the dmac when only the ifc[2:0] bits in the frequency control register (frqcr) are modified and the clock ratio is set to other than i :b = 1:1. normal operation cannot be guaranteed otherwise. however, there is no problem if the stc[2:0] bits are modified simultaneously with the ifc[2:0] bits in the frequency control register (frqcr).
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 443 of 1036 rej09b0254-0600 section 15 timer (tmu) 15.1 overview this lsi has an on-chip 32-bit timer unit (tmu) comprised of three 32-bit timer channels (channels 0 to 2). 15.1.1 features the tmu has the following features: ? auto-reload 32-bit down-c ounters for each channel ? auto-reload 32-bit constant registers and 32-bit do wn counters that can be read or written to at any time for each channel ? interrupt request generation at the counter underflow: interrupt requests can be generated when the 32-bit down counter underflows (h'00000000 h'ffffffff) in each channel. ? selection of six counter input clocks for each channel: on-chip rtc output clock (16 khz), p /4, p /16, p /64, and p /256 ? all channels can operate when the SH7727 is in standby mode: when the rtc output clock is used as the counter input clock, the count operation is normally performed in standby mode. ? synchronized read: tcnt is a 32-bit register that is successively modified. since the internal bus for the SH7727 on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. to correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built in the tcnt so that the entire 32-bit data in the tcnt can be read at once. ? the maximum 2 mhz operating frequency fo r the 32-bit counter in each channel: operate the SH7727 so that the clock input to each channel timer counter does not exceed the maximum operating frequency, by dividing the external clock and peripheral clock (p ) with the prescaler.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 444 of 1036 rej09b0254-0600 15.1.2 block diagram figure 15.1 shows a block diagram of the tmu. prescaler tstr tcr0 tcnt0 module bus internal bus tcor0 tcr1 tcnt1 tcor1 counter controller p rtcclk tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 tcr2 tcnt2 tcor2 tmu ch. 1 ch. 2 clock controller tstr: tcr: timer start register timer control register tcnt: tcor: 32-bit timer counter 32-bit timer constant register legend: figure 15.1 tmu block diagram
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 445 of 1036 rej09b0254-0600 15.1.3 register configuration table 15.1 shows the tmu register configuration. table 15.1 tmu register configuration channel register abbre- viation r/w initial value * address access size common timer start register tstr r/w h'00 h'fffffe92 8 0 timer constant register 0 tcor0 r/w h'ffffffff h'fffffe94 32 timer counter 0 tcnt0 r/w h'ffffffff h'fffffe98 32 timer control register 0 tcr0 r/w h'0000 h'fffffe9c 16 1 timer constant register 1 tcor1 r/w h'ffffffff h'fffffea0 32 timer counter 1 tcnt1 r/w h'ffffffff h'fffffea4 32 timer control register 1 tcr1 r/w h'0000 h'fffffea8 16 2 timer constant register 2 tcor2 r/w h'ffffffff h'fffffeac 32 timer counter 2 tcnt2 r/w h'ffffffff h'fffffeb0 32 timer control register 2 tcr2 r/w h'0000 h'fffffeb4 16 note: * initialized by a power-on reset or manual reset.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 446 of 1036 rej09b0254-0600 15.2 tmu registers 15.2.1 timer start register (tstr) tstr is an 8-bit read/write register that selects starting or stopping of the timer counters (tcnt) for channels 0 to 2. tstr is initialized to h'00 by a power-on reset or manual reset. tstr is not initialized in standby mode when the on-chip rtc clock (rtcclk) is selected as the input clock for the channel. however, only if the peripheral clock (p ) is selected for the channels, it is initialized in standby mode when the multiplying ratio of pll circuit 1 is modified and when the mstp2 bit in stbcr is set to 1. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? str2 str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 3?reserved: these bits are always read as 0 and should be written with 0. bit 2?counter start 2 (str2): selects starting or stopping of the timer counter 2 (tcnt2). bit 2: str2 description 0 halts tcnt2 operation (initial value) 1 starts tcnt2 operation bit 1?counter start 1 (str1): starting or stopping of the timer counter 1 (tcnt1). bit 1: str1 description 0 halts tcnt1 operation (initial value) 1 starts tcnt1 operation bit 0?counter start 0 (str0): selects starting or stopping of the timer counter 0 (tcnt0). bit 0: str0 description 0 halts tcnt0 operation (initial value) 1 starts tcnt0 operation
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 447 of 1036 rej09b0254-0600 15.2.2 timer control register (tcr) the timer control registers (tcr) are 16-bit read/write registers that control the timer counters (tcnt) and interrupts. the tmu has a total of three tcr registers, one for each channel. the tcr registers control the interrupt generated when the flag that indicates the timer counter (tcnt) underflow has been set to 1, and select the counter clock. when an external clock has been selected, the clock edge can also be selected. tcr is initialized to h'0000 by a power-on reset or manual reset. in standby mode, it is not initialized and retains the value. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? unf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? unie ? ? tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w r r r/w r/w r/w bits 15 to 9, 7, 6, 4, and 3?reserved: these bits are always read as 0 and should only be written with 0. bit 8?underflow flag (unf): this is a status flag that i ndicates that tcnt underflowed. bit 8: unf description 0 tcnt has not underflowed. clear condition: when 0 is written to unf (initial value) 1 tcnt has underflowed (h'00000000 h'ffffffff). setting condition: when tcnt underflows * note: * when a write of 1 is provided to unf, it is not modified and the previous value is retained.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 448 of 1036 rej09b0254-0600 bit 5?underflow interrupt control (unie): controls enabling or disabling of interrupt generation when the status flag (unf) that indicates tcnt underflow has been set to 1. bit 5: unie description 0 interrupt due to unf (tuni) is disabled. (initial value) 1 interrupt due to unf (tuni) is enabled. bits 2 to 0?timer prescalers 2 to 0 (tpsc2 to tpsc0): these bits select the tcnt count clock. bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 counts on peripheral clock p /4 (initial value) 1 counts on peripheral clock p / 16 1 0 counts on peripheral clock p /64 1 counts on peripheral clock p /256 1 0 0 counts on on-chip rtc clock outputs (rtcclk) 1 reserved (setting disabled) 1 0 reserved (setting disabled) 1 reserved (setting disabled) 15.2.3 timer constant register (tcor) the tmu has a total of three tcor registers, on e for each channel. the tcor registers are 32- bit read/write registers that specify a value to be set to the tcnt counter after a tcnt counter underflow occurred. tcor is initialized to h'ffffffff by a power-on reset or manual reset. in standby mode, it is not initialized and retains the value.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 449 of 1036 rej09b0254-0600 bit: 31 30 29 28 27 26 25 24 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 15.2.4 timer counters (tcnt) the tmu has a total of three timer counters (t cnt), one for each channel. the tcnt counters are 32-bit read/write registers th at are decremented according to the input clock. the input clock can be selected with the tpsc2 to tpsc0 bits in the timer control register (tcr). when a tcnt decrementation results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the decrementation continues from that value. the tcnt counter is a 32-bit readable/writable re gister. because the intern al bus for the SH7727 on-chip peripheral modules is 16 bits wide, a time lag occurs when reading data from 32-bit registers because the upper 16 bits and lower 16 bits are read separately. since tcnt counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. to prevent this, a buffer register is connected to tcnt so that upper and lower halves are not read separately. thus all 32 bits in tcnt can thus be read at once and no timing discrepancies occur when reading data.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 450 of 1036 rej09b0254-0600 tcnt is initialized to h'ffffffff by a power-on re set or manual reset. in standby mode, it is not initialized and retains the value. bit: 31 30 29 28 27 26 25 24 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 451 of 1036 rej09b0254-0600 15.3 tmu operation 15.3.1 overview each channel has a 32-bit timer counter (tcnt) an d a 32-bit timer constant register (tcor). the tcnt is a down-counter. the auto-reload function can be used to enable synchronized counting and counting by external events. 15.3.2 basic functions counter operation: when the str0 to str2 bits in the ti mer start register (tstr) are set, the corresponding timer counters (tcnt) start d ecrementation. when tcnt underflows, the unf flag in the corresponding timer control register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the decrementation is continued. the decrementation is set as follows (figure 15.2): select operation select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (3) (4) (5) (1) select the counter clock with the tpsc2 to tpsc0 bits in the timer control register (tcr). (2) set whether or not an interrupt is generated when tcnt underflows, with the unie bit in tcr. (3) set a value in the timer constant register (tcor) (the cycle is the set value plus 1). (4) set the initial value in the timer counter (tcnt). (5) set the str bit in the timer start register (tstr) to 1 to start operation. note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. figure 15.2 setting the count operation
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 452 of 1036 rej09b0254-0600 auto-reload count operation: figure 15.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0 to str2 unf tcor value set to tcnt during underflow time figure 15.3 auto-reload counter operation tcnt count timing: ? internal clock operation select one of the four internal clocks (p /4, p /16, p /64, p /256), which are divided from the peripheral clock p , with the tpsc2 to tpsc0 bits in tcr. figure 15.4 shows the timing. p divided clock tcnt input clock tcnt n + 1 n n ? 1 figure 15.4 count timing when internal clock is operating
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 453 of 1036 rej09b0254-0600 ? on-chip rtc clock operation select the on-chip rtc clock as the timer clock with the tpsc2 to tpsc0 bits in tcr. rtc output clock tcnt input clock tcnt n + 1 n n ? 1 figure 15.5 count timing when on-chip rtc clock is operating 15.4 interrupts there is only one source for tmu interrupts: underflow interrupts (tuni). 15.4.1 status flag set timing the unf bit is set to 1 when tcnt underflows. figure 15.6 shows the timing. p tcnt underflow signal unf tuni tcor value h'00000000 figure 15.6 unf set timing
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 454 of 1036 rej09b0254-0600 15.4.2 status flag clear timing the status flag is cleared when 0 is written by the cpu. figure 15.7 shows the timing. p peripheral address bus unf tcr address t1 t2 tcr write cycle t3 figure 15.7 status flag clear timing 15.4.3 interrupt sou rces and priorities the tmu generates underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the correspon ding interrupt is requested. when an interrupt is generated, codes are set in the interrupt ev ent register (intevt, intevt2). provide the appropriate interrupt handlin g according to the codes. the channel priority can be changed using the interrupt controller (see section 4, exception handling, and section 7, interrupt controller (i ntc)). table 15.2 lists tmu interrupt sources. table 15.2 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 low
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 455 of 1036 rej09b0254-0600 15.5 usage notes 15.5.1 writing to registers synchronous processing is not performed for timer count operation during register writes. when writing to registers, always clear the start bits (str2 to str0) for the desired channel in the timer start register (tstr) to halt timer counting. 15.5.2 reading registers synchronous processing is performed for timer count operation during register reads. when timer counting and register read processi ng are performed simultaneously, the register value prior to the tcnt decrementation is read with the synchronous processing.
section 15 timer (tmu) rev.6.00 mar. 27, 2009 page 456 of 1036 rej09b0254-0600
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 457 of 1036 rej09b0254-0600 section 16 realtime clock (rtc) 16.1 overview this lsi has a realtime clock (rtc) with its own 32.768-khz crysta l oscillation circuit. 16.1.1 features the rtc has the following features: ? clock and calendar functions (bcd display): seconds, minutes, hours, date, day of the week, month, and year ? 1 to 64-hz timer (binary display) ? start/stop function ? 30-second adjustment ? alarm interrupt: frame comparisons of seconds, minutes, hours, date, day of the week, and month can be selected for the alarm interrupt condition ? periodic interrupts: the interrupt cycle can be selected from 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds ? carry interrupt: a carry interrupt indicates when a carry occurs during a counter read ? automatic leap year correction
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 458 of 1036 rej09b0254-0600 16.1.2 block diagram figure 16.1 shows a block diagram of the rtc. module bus rtc internal bus interrupt control circuit prescaler ( 2) rtcclk bus interface carry detection circuit ati pri cui r64cnt reset rseccnt rmincnt rhrcnt rwkcnt 16.384 khz rdaycnt rmoncnt ryrcnt comparator rsecar rminar rhrar rwkar rdayar rcr1 rcr2 30- second adj extal2 32.768 khz 128 hz xtal2 externally connected circuit oscillator circuit prescaler ( 128) rmonar r64cnt: rseccnt: rmincnt: rhrcnt: rwkcnt: rdaycnt: rmoncnt: ryrcnt: 64-hz counter second counter minute counter hour counter day of the week counter date counter month counter year counter rsecar: rhrar: rminar: rwkar: rdayar: rmonar: rcr1: rcr2: second alarm register minute alarm register hour alarm register day of the week alarm register date alarm register month alarm register rtc control register 1 rtc control register 2 legend: figure 16.1 rtc block diagram
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 459 of 1036 rej09b0254-0600 16.1.3 pin configuration table 16.1 shows the rtc pin configuration. table 16.1 rtc pin configuration pin abbreviation i/o description rtc oscillator crystal pin extal2 i connects crystal to rtc oscillator * 1 rtc oscillator crystal pin xtal2 o connects crystal to rtc oscillator * 1 power-supply pin dedicated for rtc vcc-rtc ? power-supply pin for rtc oscillator * 1 gnd pin dedicated for rtc vss-rtc ? gnd pin for rtc oscillator * 2 notes: 1. when the rtc is not used, set extal2 to pull-up (to vcc-rtc) and make no connection for xtal2. 2. input of external noise via the vss-rtc pin can cause the device to malfunction. to prevent external noise input via the vss-rtc, the system and circuitry should include a noise elimination circuit.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 460 of 1036 rej09b0254-0600 16.1.4 rtc register configuration table 16.2 shows the rtc register configuration. table 16.2 rtc registers name abbreviation r/w initia l value address access size 64-hz counter r64cnt r undefined h'fffffec0 8 second counter rseccnt r/w undefined h'fffffec2 8 minute counter rmincnt r/w undefined h'fffffec4 8 hour counter rhrcnt r/w undefined h'fffffec6 8 day of week counter rwkcnt r/w undefined h'fffffec8 8 date counter rdaycnt r/w undefined h'fffffeca 8 month counter rmoncnt r/w undefined h'fffffecc 8 year counter ryrcnt r/w undefined h'fffffece 8 second alarm register rsecar r/w undefined * h'fffffed0 8 minute alarm register rminar r/w undefined * h'fffffed2 8 hour alarm register rhrar r/w undefined * h'fffffed4 8 day of week alarm register rwkar r/w undefined * h'fffffed6 8 date alarm register rdayar r/w undefined * h'fffffed8 8 month alarm register rmonar r/w undefined * h'fffffeda 8 rtc control register 1 rcr1 r/w h'00 h'fffffedc 8 rtc control register 2 rcr2 r/w h'09 h'fffffede 8 note: * only the enb bit in each register is initialized.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 461 of 1036 rej09b0254-0600 16.2 register descriptions 16.2.1 64-hz counter (r64cnt) the 64-hz counter (r64cnt) is an 8-bit read-onl y register that indicates the state of the rtc divider circuits (rtc prescaler or r64cnt) between 64 hz and 1 hz. r64cnt is reset to h'00 when the reset bit in rtc control register 2 (rcr2) or the adj bit in rcr2 is set to 1. r64cnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit 7 is always read as 0. bit: 7 6 5 4 3 2 1 0 ? 1hz 2hz 4hz 8hz 16hz 32hz 64hz initial value: 0 ? ? ? ? ? ? ? r/w: r r r r r r r r 16.2.2 second counter (rseccnt) the second counter (rseccnt) is an 8-bit read/wr ite register that is used for setting/counting in the bcd-coded second section of the rtc. the co unt operation is performed by a carry for each second of the 64-hz counter. the settable range is 00 to 59 in decimal. if other values are set, correct op eration is not provided. when modifying rseccnt, check that the count operation has been halted with the start bit in rcr2. rseccnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit: 7 6 5 4 3 2 1 0 ? 10 seconds 1 second initial value: 0 ? ? ? ? ? ? ? r/w: r r/w r/w r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 462 of 1036 rej09b0254-0600 16.2.3 minute counter (rmincnt) the minute counter (rmincnt) is an 8-bit read/w rite register used for setting/counting in the bcd-coded minute section of the rtc. the count operation is performed by a carry for each minute of the second counter. the settable range is 00 to 59 in decimal. if other values are set, correct op eration is not provided. when modifying rmincnt, check that the count operation has been halted with the start bit in rcr2. rmincnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit: 7 6 5 4 3 2 1 0 ? 10 minutes 1 minute initial value: 0 ? ? ? ? ? ? ? r/w: r r/w r/w r/w r/w r/w r/w r/w 16.2.4 hour counter (rhrcnt) the hour counter (rhrcnt) is an 8-bit read/wr ite register used for setting/counting in the bcd- coded hour section of the rtc. th e count operation is performed by a carry for each 1 hour of the minute counter. the settable range is 00 to 23 in decimal. if other values are set, correct op eration is not provided. when modifying rhrcnt, check that the count operation has been halted with the start bit in rcr2. rhrcnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit: 7 6 5 4 3 2 1 0 ? ? 10 hours 1 hour initial value: 0 0 ? ? ? ? ? ? r/w: r r r/w r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 463 of 1036 rej09b0254-0600 16.2.5 day of the week counter (rwkcnt) the day of the week counter (rwkcnt) is an 8-bit read/write register used for setting/counting in the bcd-coded day of week section of the rt c. the count operation is performed by a carry for each day of the date counter. the settable range is 0 to 6 in decimal. if other va lues are set, correct operation is not provided. when modifying rwkcnt, check that the count operation has been halted with the start bit in rcr2. rwkcnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? day of week initial value: 0 0 0 0 0 ? ? ? r/w: r r r r r r/w r/w r/w days of the week are coded as shown in table 16.3. table 16.3 day-of-week codes (rwkcnt) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 464 of 1036 rej09b0254-0600 16.2.6 date counter (rdaycnt) the date counter (rdaycnt) is an 8-bit read/write register used for setting/counting in the bcd-coded date section of the rtc. the count operation is performed by a carry for each day of the hour counter. the settable range is 01 to 31 in decimal. if other values are set, correct op eration is not provided. when modifying rdaycnt, check that the count operation has been halted with the start bit in rcr2. rdaycnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. the settable rdaycnt range differs according to the month and leap year. please confirm the correct setting. bit: 7 6 5 4 3 2 1 0 ? ? 10 days 1 day initial value: 0 0 ? ? ? ? ? ? r/w: r r r/w r/w r/w r/w r/w r/w 16.2.7 month counter (rmoncnt) the month counter (rmoncnt) is an 8-bit read/w rite register used for setting/counting in the bcd-coded month section of the rtc. the count operation is performed by a carry for each month of the date counter. the settable range is 01 to 12 in decimal. if other values are set, correct op eration is not provided. when modifying rmoncnt, check that the count operation has been halted with the start bit in rcr2. rmoncnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. bit: 7 6 5 4 3 2 1 0 ? ? ? 10 months 1 month initial value: 0 0 0 ? ? ? ? ? r/w: r r r r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 465 of 1036 rej09b0254-0600 16.2.8 year counter (ryrcnt) the year counter (ryrcnt) is an 8-bit read/wr ite register used for setting/counting in the bcd- coded year section of the rtc. the least significant 2 digits of the western calendar year are displayed. the count operation is performed by a carry for each year of the month counter. the settable range is 00 to 99 in decimal. if other values are set, correct op eration is not provided. when modifying ryrcnt, check that the count operation is halted with the start bit in rcr2. ryrcnt is not initialized by a power-on reset or manual reset, or in standby mode, and the operation is continued. leap years are recognized by divi ding the year counter value by 4 and obtaining a fractional result of 0. note that a counter value of 00 is treated as a leap year. bit: 7 6 5 4 3 2 1 0 10 years 1 year initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w 16.2.9 second alarm register (rsecar) the second alarm register (rsecar) is an 8-bit re ad/write alarm register that corresponds to the bcd-coded second section counter rseccnt of the rtc. when the enb bit is set to 1in rsecar, the rsecar value and rseccnt value are compared. in this way, the rsecar, rminar, rhrar, rwkar, rday ar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corr esponding counter are compar ed. if all values in the specified alarm registers and the correspondi ng counters match, an rtc alarm interrupt is generated. the settable range is ?00 to 59 in decimal + enb b it?. if other values are set, correct operation is not provided. only the enb bit in rsecar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rsecar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10 seconds 1 second initial value: 0 ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 466 of 1036 rej09b0254-0600 16.2.10 minute alarm register (rminar) the minute alarm register (rminar) is an 8-bit re ad/write alarm register that corresponds to the bcd-coded minute section counter rmincnt of th e rtc. when the enb bit is set to 1in rminar, the rminar value and rmincnt value are compared. in this way, the rsecar, rminar, rhrar, rwkar, rday ar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corr esponding counter are compar ed. if all values in the specified alarm registers and the correspondi ng counters match, an rtc alarm interrupt is generated. the settable range is ?00 to 59 in decimal + enb b it?. if other values are set, correct operation is not provided. only the enb bit in rminar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rminar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb 10 minutes 1 minute initial value: 0 ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w 16.2.11 hour alarm register (rhrar) the hour alarm register (rhrar) is an 8-bit read /write alarm register th at corresponds to the bcd-coded hour section counter rhrcnt of the rtc. when the enb bit is set to 1in rhrar, the rhrar value and rhrcnt value are comp ared. in this way, the rsecar, rminar, rhrar, rwkar, rdayar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corresponding counter are compared. if all values in the specified alarm registers and the corresponding counters match, an rtc alarm interrupt is generated. the settable range is ?00 to 23 in decimal + enb b it?. if other values are set, correct operation is not provided. only the enb bit in rhrar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rhrar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb ? 10 hours 1 hour initial value: 0 0 ? ? ? ? ? ? r/w: r/w r r/w r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 467 of 1036 rej09b0254-0600 16.2.12 day of the week alarm register (rwkar) the day of the week alarm register (rwkar) is an 8-bit read/write alarm register that corresponds to the bcd-coded day of week section counter rwkcnt of the rtc. when the enb bit is set to 1in rwkar, the rwkar valu e and rwkcnt value are compared. in this way, the rsecar, rminar, rhrar, rwkar, rdayar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corresponding counter are compared. if all values in the specified alarm registers and the co rresponding counters match, an rtc alarm interrupt is generated. the settable range is ?0 to 6 in decimal + enb bit?. if other values are set, correct operation is not provided. only the enb bit in rwkar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rwkar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb ? ? ? ? day of week initial value: 0 0 0 0 0 ? ? ? r/w: r/w r r r r r/w r/w r/w days of the week are coded as shown in table 16.4. table 16.4 day-of-week codes (rwkar) day of week code sunday 0 monday 1 tuesday 2 wednesday 3 thursday 4 friday 5 saturday 6 16.2.13 date alarm register (rdayar) the date alarm register (rdayar) is an 8-bit read /write alarm register th at corresponds to the bcd-coded date section counter rdaycnt of th e rtc. when the enb bit is set to 1in rdayar, the rdayar value and rdaycnt value are compared. in this way, the rsecar,
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 468 of 1036 rej09b0254-0600 rminar, rhrar, rwkar, rday ar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corr esponding counter are compar ed. if all values in the specified alarm registers and the correspondi ng counters match, an rtc alarm interrupt is generated. the settable range is ?01 to 31 in decimal + enb b it?. if other values are set, correct operation is not provided. the settable rdaycnt range differs according to the month and leap year. please confirm the correct setting. only the enb bit in rdayar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rdayar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb ? 10 days 1 day initial value: 0 0 ? ? ? ? ? ? r/w: r/w r r/w r/w r/w r/w r/w r/w 16.2.14 month alarm register (rmonar) the month alarm register (rmonar) is an 8-bit re ad/write alarm register that corresponds to the bcd-coded month section counter rmoncnt of the rtc. when the enb bit is set to 1in rmonar, the rmonar value and rmoncnt value are compared. in this way, the rsecar, rminar, rhrar, rwkar, rday ar, and rmonar registers are checked, and when the enb bit is set to 1, the alarm register and the corr esponding counter are compar ed. if all values in the specified alarm registers and the correspondi ng counters match, an rtc alarm interrupt is generated. the settable range is ?01 to 12 in decimal + enb b it?. if other values are set, correct operation is not provided. only the enb bit in rmonar is initialized to 0 by a power-on reset, and the other bits are not initialized. the rmonar contents are retained after a manual reset or in standby mode. bit: 7 6 5 4 3 2 1 0 enb ? ? 10 months 1 month initial value: 0 0 0 ? ? ? ? ? r/w: r/w r r r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 469 of 1036 rej09b0254-0600 16.2.15 rtc control register 1 (rcr1) the rtc control register 1 (rcr1) is an 8-bit read /write register that contains carry flags and alarm flags. it also selects wh ether to generate interrupts for each flag. avoid the use of read- modify-write processing for this register becaus e flags are sometimes set after an operand read. rcr1 is an 8-bit read/write regist er. the cie, aie, and af bits ar e initialized by a power-on reset or manual reset. however, the value of the cf flag is undefined after a power-on reset or manual reset. it must therefore be initialized without fail before use. this register is not initialized in standby mode. bit: 7 6 5 4 3 2 1 0 cf ? ? cie aie ? ? af initial value: ? 0 0 0 0 0 0 0 r/w: r/w r r r/w r/w r r r/w bit 7?carry flag (cf): status flag that indicates that a carry has occurred. cf is set to 1 when a carry occurs in r64cnt or rseccn t. if the count register is read at this time, the value is not guaranteed; therefore, another read is required. bit 7: cf description 0 no carry in r64cnt or rseccnt. clearing condition: when 0 is written to cf 1 setting condition: carry occurred in rseccnt read of r64cnt at carry occurrence when 1 is written to cf bits 6, 5, 2, and 1?reserved: these bits are always read as 0 and should only be written with 0. bit 4?carry interrupt enable flag (cie): enables or disables interrupt generation when the carry flag (cf) is set to 1. bit 4: cie description 0 a carry interrupt is not generated when the cf flag is set to 1 (initial value) 1 a carry interrupt is generated when the cf flag is set to 1
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 470 of 1036 rej09b0254-0600 bit 3?alarm interrupt enable flag (aie): enables or disables interrupt generation when the alarm flag (af) is set to 1. bit 3: aie description 0 an alarm interrupt is not generated when the af flag is set to 1 (initial value) 1 an alarm interrupt is generated when the af flag is set to 1 bit 0?alarm flag (af): the af flag is set to 1 when the al arm time set in alarm registers (only for the registers with enb bit set to 1) match the clock and calendar time. this flag is cleared to 0 when 0 is written, but the previous value is retained when 1 is to be written. bit 0: af description 0 clock/calendar and alarm register have not matched since last reset to 0. clearing condition: when 0 is written to af (initial value) 1 setting condition: clock/calendar and al arm register have matched (only for the registers with enb set to 1) * note: * the value is not modified when 1 is written to af. 16.2.16 rtc control register 2 (rcr2) the rtc control register 2 (rcr2) is an 8-bit read/w rite register that controls periodic interrupts, 30-second adjustment adj, divider circuits reset, and starting and stopping of the rtc count. it is initialized to h'09 by a power-on reset. by a manual reset, bits except rtcen and start are initialized. rcr2 is not initialized and retains its contents in standby mode. bit: 7 6 5 4 3 2 1 0 pef pes2 pes1 pes0 rtcen adj reset start initial value: 0 0 0 0 1 0 0 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 471 of 1036 rej09b0254-0600 bit 7?periodic interrupt flag (pef): indicates that interrupts are generated with the period designated by the pes bits. when this bit is set to 1, periodic interrupts are generated. bit 7: pef description 0 interrupts not generated with the period designated by the pes bits. clearing condition: when 0 is written to pef (initial value) 1 setting condition: when interrupts are generated with t he period designated by the pes bits when 1 is written to pef bits 6 to 4?periodic interrupt flags (pes2 to pes0): these bits specify the periodic interrupt. bit 6: pes2 bit 5: pes1 bit 4: pes0 description 0 0 0 no periodic interrupts generated (initial value) 1 periodic interrupt generated every 1/256 second 1 0 periodic interrupt generated every 1/64 second 1 periodic interrupt generated every 1/16 second 1 0 0 periodic interrupt generated every 1/4 second 1 periodic interrupt generated every 1/2 second 1 0 periodic interrupt generated every 1 second 1 periodic interrupt generated every 2 seconds bit 3?rtcen: controls the operation of the crystal oscillator for the rtc. bit 3: rtcen description 0 halts the crystal oscillator for the rtc. * 1 runs the crystal oscillator for the rtc. * (initial value) note: * rtcen should be set to 0 when the rtc is not used.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 472 of 1036 rej09b0254-0600 bit 2?30 second adjustment (adj): when the adj bit is written with 1, the time of 29 seconds or less will be rounded to 00 seconds and the time of 30 seconds or more to 1 minute. the divider circuits (rtc prescaler and r64cnt) will be simultaneously reset. this bit is always read as 0. bit 2: adj description 0 normal operation (initial value) 1 (write) 30-second adjustment. bit 1?reset (reset): when 1 is written to the reset bit, the divider circuits (rtc prescaler and r64cnt) are initialized. this bit is always read as 0. bit 1: reset description 0 runs normally. (initial value) 1 (write) divider circuits are reset. bit 0?start bit (start): halts and restarts the counter (clock). bit 0: start description 0 second, minute, hour, day, week, month, and year counters are halted. * 1 second, minute, hour, day, week, month, and year counters operate normally. * (initial value) note: * the 64-hz counter operates normally until it is stopped with the rtcen bit.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 473 of 1036 rej09b0254-0600 16.3 rtc operation 16.3.1 initial settings of registers after power-on all rtc registers should be set initia lly after the power is turned on. 16.3.2 setting the time figures 16.2 (a) and 16.2 (b) show how to set the time after stopping the clock. this procedure can be used to set the entire calendar and clock function. it can be programmed easily. usage notes 1. initialization timing for 64 hz counter (r64cnt) if it is necessary, after initializing the counter by means of the reset bit in the rtc?s rcr2 register, to confirm that the change has taken e ffect by reading the r64cnt value, wait at least 107 s after setting the reset bit to 1 before reading the r64cnt counter. note that the divider circuit (rtc prescaler) is also initialized when the reset bit is set to 1. 2. incrementing rseccnt by initializing r64cnt either method (a) or method (b) below may be used. (a) after setting the reset bit to 1 and confirming that r64cnt has been initialized, set the start bit to 1. this process is shown in figure 16.2 (a). (b) set the start bit to 1 and the reset bit to 1 at the same time. this process is shown in figure 16.2 (b). note that the processing indicated by the asterisk (*) in figure 16.2 (b) may be omitted if nothing is written to the rcr2 register during an interval of approximately 107 s after the start bit is set to 1.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 474 of 1036 rej09b0254-0600 write 1 to reset and 0 to start in the rcr2 register write 1 to start in the rcr2 registe r confirm r64cnt is 0 start clock set seconds, minutes, hour, day, day of the week, month and year yes no confirm r64cnt is not 0 stop clock reset divider circuit order is irrelevant figure 16.2(a) setting the time write 1 to reset and 0 to start in the rcr2 registe r order is irrelevant write to rcr2 set seconds, minutes, hour, day, day of the week, month and year confirm r64cnt is 0 yes no confirm r64cnt is not 0 stop clock reset divider circuit * * start clock reset divider circuit write 1 to reset and 1 to start in the rcr2 registe r * figure 16.2(b) setting the time
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 475 of 1036 rej09b0254-0600 16.3.3 reading the time figure 16.3 shows how to read the time. if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. the method of reading the time without using interrupts is shown at (a) in figure 16.3, and the method using carry interrupts is shown at (b). to keep the program simple, meth od (a) is used normally. write 0 to cf in rcr1 note: set af to 1 so that alarm flag is not cleared. read rcr1 and check cf write 0 to cie in rcr1 write 0 to cie in rcr1 carry flag = 1? no yes clear the carry flag disable the carry interrupt read counter register write 1 to cie in rcr1, and write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. interrupt generated? no yes enable the carry interrupt clear the carry flag disable the carry interrupt read counter register to read the time without using interrupts b. to use interrupts a. figure 16.3 reading the time
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 476 of 1036 rej09b0254-0600 16.3.4 alarm function figure 16.4 shows how to use the alarm function. alarm can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. set the enb bits (bit 7) in the desired alarm registers to 1, and then set the alarm time in the lower bits. clear the enb bits in the registers which are not used for the alarm to 0. when the clock and alarm time match, the af bit (bit 0) in rcr1 is set to 1. the alarm detection can be checked by reading this bit, but normally it is checked by the interrupt generation. if the aie bit (bit 3) in rcr1 is written with 1, an interrupt is generated when an alarm occurs. clock running set alarm time cancel alarm interrupt clear alarm flag monitor alarm time (wait for interrupt or check alarm flag) disables interrupts (clears the aie bit in rcr1 to 0) in order to prevent erroneous interrupts, and then writes 1. always reset the alarm flag, since a flag may have been set while the alarm time was being set (clear the af bit in rcr1 register to 0). figure 16.4 using the alarm function
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 477 of 1036 rej09b0254-0600 16.3.5 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 16.5, and the rtc crystal oscillator circuit in figure 16.5. table 16.5 recommended oscillator circu it constants (recommended values) f osc c in c out 32.768 khz 10 to 22 pf 10 to 22 pf SH7727 extal2 xtal2 xtal c in c out r f r d notes: 1. select either the c in or c out side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. built-in resistance value r f (typ value) = 10 m , r d (typ value) = 400 k 3. c in and c out values include floating capacitance due to the wiring. take care when using a ground plane. 4. the crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2, xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 16.5 example of crystal oscillator circuit connection
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 478 of 1036 rej09b0254-0600 16.4 usage notes 16.4.1 writing registers during rtc count operation during the rtc count operation (rcr2 bits 0 = 1), the following registers cannot be written. rseccnt, rmicnt, rhrcnt, rdaycn t, rwkcnt, rmoncnt, and ryrcnt to write these registers, the rtc count operation should be stopped. 16.4.2 rtc periodic interrupts figure 16.6 shows the periodic interrupt function setting flow. periodic interrupts can be generated with the period specified by the periodic interrupt enable flag (pes) in the rtc control register (rcr2). when the time period specified by pes passed, the periodic interrupt flag (pef) is set to 1. pef is cleared to 0 when pes is set and a periodic interrupt is generated. the periodic interrupt generation can be checked by reading this bit, but is usually checked by the interrupt function. pes is set and pef is cleared in rcr2. pef is cleared to 0. set pes and clear pef period set by pes passed clears pef figure 16.6 periodic interrupt function setting
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 479 of 1036 rej09b0254-0600 16.4.3 using the adj bit in the real time clock (rtc) (1) description the maximum amount of time from when the adj bit in rcr2 of the rtc is set to 1 and when the value read from the second counter (rseccnt) is reflected is approximately 91.6 s (the time required for pin of the extal2 to connect to the 32.768 khz crystal resonator). note that the second counter itself performs a 30-second adjustment when the adj bit is set to 1, so the above delay causes no problems with the functioning of the rtc. (2) precautions if it is necessary to ensure that the 30-second ad justment triggered by the adj bit in rcr2 of the rtc is properly read and its value reflected, the second counter should not be read until a minimum of approximately 91.6 s has passed following the setting of the adj bit.
section 16 realtime clock (rtc) rev.6.00 mar. 27, 2009 page 480 of 1036 rej09b0254-0600
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 481 of 1036 rej09b0254-0600 section 17 serial communication interface (sci) 17.1 overview this lsi has an on-chip serial communication inte rface (sci) that supports both asynchronous and clock synchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more proces sors. the sci supports a smart card interface, which is a serial communications feature for ic card interfaces that conforms to the iso/iec standard 7816-3 for identification cards data transmission protocol type t = 0. see section 18, smart card interface, fo r more information. 17.1.1 features select asynchronous or clock synchronous as the serial communications mode. ? asynchronous mode: ? serial data communications are synched by start-stop in character units. the sci can communicate with a universal as ynchronous receiver /transmitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous serial system. it can also communicate with two or more other processors using the multiprocessor communication function. there are 12 selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? receive error detection: parity , overrun, and framing errors ? break detection: by reading the rxd0 level directly from the port sc data register (scsptr) when a framing error occurs ? clock synchronous mode: ? serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a clock synchronous communication function. there is one serial data communication format. ? data length: eight bits ? receive error detecti on: overrun errors ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 482 of 1036 rej09b0254-0600 ? on-chip baud rate generator with selectable bit rates ? internal or external transmit/receive clock source: from either baud rate generator (internal) or sck0 pin (external) ? four types of interrupts: transmit-data-empty , transmit-end, receive-d ata-full, and receive- error interrupts are requested independently. ? when the sci is not in use, it can be stopped by halting the clock supplied to it, saving power. 17.1.2 block diagram figure 17.1 shows an sci block diagram. rxd0 txd0 sck0 sci scbrr scssr scscr sctdr sctsr scrdr scrsr scsmr scpdr scpcr scssr parity generation parity check clock external clock module data bus internal data bus p p /4 p /16 p /64 txi tei rxi eri bus interface baud rate generator transmit/ receive control scrsr: scrdr: sctsr: sctdr: scsmr: receive shift register receive data register transmit shift register transmit data register serial mode register scscr: scssr: scbrr: scpdr: scpcr: serial control register serial status register bit rate register sc port data register sc port control register legend: figure 17.1 sci block diagram
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 483 of 1036 rej09b0254-0600 figures 17.2 to 17.4 show the block diagrams of the sci i/o port. sci pin i/o and data control is performed by bits 3 to 0 of scpcr and bits 1 and 0 of scpdr. for details, see section 17.2.8, port sc control register (scpcr)/port sc data register (scpdr). internal data bus output enable clock input enable sci serial clock output serial clock input r scp1md0 pcrw reset c q q d r scp1md1 pcrw reset c q d r scp1dt1 pdrw reset scpt[1]/sck0 c d pdrw: scpdr write pdrr: pcrw: scpdr read scpcr write pdrr * note: * when reading the sck0 pin, clear the c/ a bit in scsmr and the cke1 and cke0 bits in scscr to 0, and set the scp1md1 bit in scpcr to 1 (see section 17.2.8). legend: figure 17.2 scpt[1]/sck0 pin
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 484 of 1036 rej09b0254-0600 internal data bus output enable sci serial transmission output q r scp0dt1 pdrw reset scpt[0]/txd0 c d pcrw: pdrw: scpcr write scpdr write r scp0md0 pcrw reset c q d r scp0md1 pcrw reset c q d legend: figure 17.3 scpt[0]/txd0 pin
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 485 of 1036 rej09b0254-0600 sci serial receive data internal data bus pdrr * scpt[0]/rxd0 pdrr: pdr read note: * when reading the rxd0 pin, set the re bit in scscr to 1. legend: figure 17.4 scpt[0]/rxd0 pin 17.1.3 pin configuration the sci has the serial pins summarized in table 17.1. table 17.1 sci pins pin name abbreviation i/o function serial clock pin sck0 i/o clock i/o receive data pin rxd0 input receive data input transmit data pin txd0 ou tput transmit data output note: they are made to function as serial pins by performing sci operation settings with the te, re, ckei, and ckeo bits in scscr and the c/ a bit in scsmr. break state transmission and detection can be performed by means of the sci?s scsptr register.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 486 of 1036 rej09b0254-0600 17.1.4 register configuration table 17.2 summarizes the sci inte rnal registers. these register s select the communication mode (asynchronous or clock synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. table 17.2 registers name abbreviation r/w initial value address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w) * 1 h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 port sc data register scpdr r/w h'00 h'04000136 (h'a4000136) * 2 8 port sc control register scpcr r/w h'8008 h'04000116 (h'a4000116) * 2 16 notes: registers with addresses beginning at h'04 are located in area 1 of physical space. consequently, when the cache is on, either a ccess these registers from the p2 area of logical space or else make an appropriate se tting using the mmu so that these registers are not cached. 1. the only value that can be wr itten is 0 to clear the flags. 2. when address translation by the mmu is not executed, the address in parentheses should be used.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 487 of 1036 rej09b0254-0600 17.2 register descriptions 17.2.1 receive shift register (scrsr) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? the receive shift register (scrsr) receives serial data. data input at the rxd0 pin is loaded into the scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to the scrdr. the cpu cannot read or write the scrsr directly. 17.2.2 receive data register (scrdr) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the receive data register (scrdr ) stores serial receive data. the sci completes the reception of one byte of se rial data by moving the received data from the receive shift register (scrsr) into the scrdr fo r storage. the scrsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the cpu can read but not write to scrdr. scrdr is initialized to h'00 by a reset and in standby or module standby mode.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 488 of 1036 rej09b0254-0600 17.2.3 transmit shift register (sctsr) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? the transmit shift register (sctsr) transmits serial data. the sci loads transmit data from the transmit data register (sctdr) into the sctsr, then transmits the data serially from the txd0 pin, lsb (bit 0) first. after transmitting one-byte data, the sci automatically loads the next transmit data from the sctdr into the sctsr and starts transmitting ag ain. if the tdre bit of the scssr is 1, however, the sci does not load the sctdr contents into the sctsr. the cpu cannot read or write the sctsr directly. 17.2.4 transmit data register (sctdr) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the transmit data register (sctdr) is an eight-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (sctsr) is empty, it moves transmit data written in the sctdr into the sctsr and star ts serial transmission. continuous serial transmission is possible by writing the next transm it data in the sctdr during serial transmission from the sctsr. the cpu can always read and write the sctdr. th e sctdr is initialized to h'ff by a reset or in standby and module standby modes.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 489 of 1036 rej09b0254-0600 17.2.5 serial mode register (scsmr) bit: 7 6 5 4 3 2 1 0 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial mode register (scs mr) is an eight-bit register th at specifies the sci serial communication format and selects the cloc k source for the baud rate generator. the cpu can always read and write the scsmr. the scsmr is initialized to h'00 by a reset or in standby and module standby modes. bit 7?communication mode (c/ a ): selects whether the sci operat es in the asynchronous or clock synchronous mode. bit 7: c/ a description 0 asynchronous mode (initial value) 1 clock synchronous mode bit 6?character length (chr): selects seven-bit or eight-bit data in the asynchronous mode. in the clock synchronous mode, the data length is always eight bits, regardless of the chr setting. bit 6: chr description 0 eight-bit data (initial value) 1 seven-bit data * note: * when seven-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted. bit 5?parity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data, in the asynchronous mode . in the clock synchronous mode, a parity bit is neither added nor checked, regardless of the pe setting.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 490 of 1036 rej09b0254-0600 bit 5: pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. bit 4?parity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity addition and check. the o/ e setting is ignored in the clock synchronous mode, or in the asynchronous mode when parity addition and check is disabled. bit 4: o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. bit 3?stop bit length (stop): selects one or two bits as the stop bit length in the asynchronous mode. this setting is used only in the asynchronous mode. it is ignored in the clock synchronous mode because no stop bits are added. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the se cond stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. in transmitting, a single bit of 1 is added at the end of eac h transmitted character. 2. in transmitting, two bits of 1 are added at the end of each transmitted character.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 491 of 1036 rej09b0254-0600 bit 2?multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. the mp bit setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. for the multiprocessor communication function, see section 17.3.3, multiprocessor communication. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1 and cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available. p , p /4, p /16 and p /64. for further information on the clock source, bit rate register settings, and baud rate, see section 17.2.9, bit rate register (scbrr). bit 1: cks1 bit 0: cks0 description 0 0 p (initial value) 1 p /4 1 0 p /16 1 p /64 note: p : peripheral clock 17.2.6 serial control register (scscr) bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial control register (scscr) operates the sci transmitter/r eceiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. th e cpu can always read and write the scscr. the scscr is initialized to h'00 by a reset or in standby and module standby modes.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 492 of 1036 rej09b0254-0600 bit 7?transmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register em pty bit (tdre) in the serial status register (scssr) is set to 1 due to transfer of serial transmit data from the sctdr to the sctsr. bit 7: tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. bit 6?receive interrupt enable (rie): enables or disables the r eceive-data-full interrupt (rxi) requested when the receive data regi ster full bit (rdrf) in the serial status register (scssr) is set to 1 due to transfer of serial receive data fr om the scrsr to the scrdr. it also enables or disables receive-error interrupt (eri) requests. bit 6: rie description 0 receive-data-full interrupt (rxi) and re ceive-error interrupt (eri) requests are disabled * (initial value) 1 receive-data-full interrupt (rxi) and re ceive-error interrupt (eri) requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. bit 5?transmit enable (te): enables or disables the sci serial transmitter. bit 5: te description 0 transmitter disabled * 1 (initial value). 1 transmitter enabled * 2 notes: 1. the transmit data register empty bit (t dre) in the serial status register (scssr) is fixed to 1. 2. serial transmission starts when the transmi t data register empty (tdre) bit in the serial status register (scssr) is cleared to 0 a fter writing of transmit data into the sctdr. select the transmit format in t he scsmr before setting te to 1. bit 4?receive enable (re): enables or disables the sci serial receiver.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 493 of 1036 rej09b0254-0600 bit 4: re description 0 receiver disabled * 1 (initial value) 1 receiver enabled * 2 notes: 1. clearing re to 0 does not affect t he receive flags (rdrf, fer, per, orer). these flags retain their previous values. 2. serial reception starts when a start bi t is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. select the receive format in the scsmr before setting re to 1. bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (mp) in the serial mode register (scsmr) is set to 1 during reception. the mpie setting is ignored in the clock synchronous mode or when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) [clear conditions] 1. when mpie is cleared to 0 2. when the multiprocessor bit (mpb) is set to 1 in receive data 1 multiprocessor interrupts are enabled * receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (scssr) are disabled until data with a multiprocessor bit of 1 is received. note: * the sci does not transfer receive data from the scrsr to the scrdr, does not detect receive errors, and does not set the rdrf, fe r, and orer flags in the serial status register (scssr). when it receives data that includes mpb = 1, the scssr?s mpb flag is set to 1, and the sci automatically clears mp ie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scscr are set to 1), and allows the fer and orer bits to be set. bit 2?transmit-end inte rrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if sctdr does not contain new transmit data when the msb is transmitted. bit 2: teie description 0 transmit-end interrupt (tei) requests are disabled * (initial value) 1 transmit-end interrupt (tei) requests are enabled * note: * the tei request can be cleared by reading t he tdre bit in the serial status register (scssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0, or by clearing the teie bit to 0.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 494 of 1036 rej09b0254-0600 bits 1 and 0?clock enable 1 and 0 (cke1 and cke0): these bits select the sci clock source and enable or disable clock output from the sck0 pin. depending on the combination of cke1 and cke0, the sck0 pin can be used for serial clock output or serial clock input. the cke0 setting is valid only when the asynchro nous mode and the internal clock are selected (cke1 = 0). the cke0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (cke1 = 1). before selecting the sci operating mode in the serial mode register (scsmr), set cke1 and cke0. for further details on selection of the sci clock source, see table 17.10 in section 17.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock, sck0 pin used for input pin (input signal is ignored) * 1 clock synchronous mode internal clock, sck0 pin used for synchronous clock output * 1 1 asynchronous mode internal clock, sck0 pin used for clock output * 2 clock synchronous mode internal clock, sck0 pin used for synchronous clock output 1 0 asynchronous mode external clock, sck0 pin used for clock input * 3 clock synchronous mode external clock, sck0 pin used for synchronous clock input 1 asynchronous mode external clock, sck0 pin used for clock input * 3 clock synchronous mode external clock, sck0 pin used for synchronous clock input notes: 1. initial value 2. the output clock frequency is the same as the bit rate. 3. the input clock frequency is 16 times the bit rate.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 495 of 1036 rej09b0254-0600 17.2.7 serial status register (scssr) bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * the only value that can be wri tten is a 0 to clear the flag. the serial status register (scs sr) is an 8-bit register containing multiprocessor bit values, and status flags that indi cate sci operating state. the cpu can always read and write the scssr, bu t cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. the scssr is initialized to h'84 by a reset or in standby and module standby modes. bit 7?transmit data register empty (tdre): indicates that the sci has loaded transmit data from the sctdr into the sctsr and new serial transmit data can be written in the sctdr. bit 7: tdre description 0 sctdr contains valid transmit data [clear condition] when software reads tdre after it has been set to 1, then writes 0 in tdre or data is written in sctdr. 1 sctdr does not contain valid transmit data (initial value) [setting conditions] 1. when the chip is reset or enters standby mode 2. when the te bit in the serial cont rol register (scscr) is cleared to 0 3. when sctdr contents are loaded into sctsr, so new data can be written in sctdr.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 496 of 1036 rej09b0254-0600 bit 6?receive data register full (rdrf): indicates that scrdr contains received data. bit 6: rdrf description 0 scrdr does not contain valid received data (initial value) [clear conditions] 1. when the chip is reset or enters standby mode 2. when software reads rdrf after it has been set to 1, then writes 0 in rdrf. 1 scrdr contains valid received data [setting condition] when serial data is received normally and transferred from scrsr to scrdr. note: the scrdr and rdrf are not affected by detec tion of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of th e next data ends, an overrun error (orer) occurs and the received data is lost. bit 5?overrun error (orer): indicates that data reception aborted due to an overrun error. bit 5: orer description 0 receiving is in progress or has ended normally * 1 (initial value) [clear conditions] 1. when the chip is reset or enters standby mode 2. when orer=1 is read and then 0 is written to orer. 1 a receive overrun error occurred * 2 [setting condition] when reception of the next serial data ends when rdrf is set to 1. notes: 1. clearing the re bit to 0 in the serial co ntrol register does not affect the orer bit, which retains its previous value. 2. scrdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. in the clock synchronous mode, serial transmitting is also disabled.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 497 of 1036 rej09b0254-0600 bit 4?framing error (fer): indicates that data reception abor ted due to a framing error in the asynchronous mode. bit 4: fer description 0 receiving is in progress or has ended normally * 1 (initial value) [clear conditions] 1. when the chip is reset or enters standby mode 2. when fer=1 is read and then 0 is written to fer. 1 a receive framing error occurred fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0. * 2 notes: 1. clearing the re bit to 0 in the serial control register does not affect the fer bit, which retains its previous value. 2. when the stop bit length is two bits, only t he first bit is checked. the second stop bit is not checked. when a framing error occurs, t he sci transfers the receive data into the scrdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in the clock synchronous mode, serial transmitting is also disabled. bit 3?parity error (per): indicates that data reception (with parity) aborted due to a parity error in the asynchronous mode. bit 3: per description 0 receiving is in progress or has ended normally * 1 (initial value) [clear conditions] 1. when the chip is reset or enters standby mode 2. when per=1 is read and then 0 is written to per. 1 a receive parity error occurred * 2 [setting condition] when the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (scsmr). notes: 1. clearing the re bit to 0 in the serial control register does not affect the per bit, which retains its previous value. 2. when a parity error occurs, the sci transfe rs the receive data into the scrdr but does not set rdrf. serial receiving cannot contin ue while per is set to 1. in the clock synchronous mode, serial transmitting is also disabled.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 498 of 1036 rej09b0254-0600 bit 2?transmit end (tend): indicates that when the last bit of a serial character was transmitted, the sctdr did not contain valid data, so transmission has ended. tend is a read- only bit and cannot be written. bit 2: tend description 0 transmission is in progress [clear condition] when tdre=1 is read and then 0 is written to tdre. 1 end of transmission (initial value) [setting conditions] 1. when the chip is reset or enters standby mode 2. when te is cleared to 0 in the serial control register (scscr) 3. if tdre is 1 when the last bit of a one-byte serial character is transmitted. bit 1?multiprocessor bit (mpb): stores the value of the multip rocessor bit in receive data when a multiproces sor format is selected for receiving in the asynchronous mode. the mpb is a read-only bit and cannot be written. bit 1: mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if re is cleared to 0 when a multiprocesso r format is selected, the mpb retains its previous value. bit 0?multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. the mpbt setting is ignored in the clock synchr onous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 0: mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 499 of 1036 rej09b0254-0600 17.2.8 port sc control register (s cpcr)/port sc data register (scpdr) the port sc control register (scp cr) and port sc data register (scpdr) control i/o and data for the port multiplexed with the serial communication interface (sci) pins. scpcr settings are used to perform i/o control, to enable data written in scpdr to be output to the txd0 pin, and input data to be read from the rxd0 pin, and to control serial transmission/reception breaks. it is also possible to read data on the sck0 pin, and write output data. scpcr bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scp7 md1 scp7 md0 scp6 md1 scp6 md0 scp5 md1 scp5 md0 scp4 md1 scp4 md0 scp3 md1 scp3 md0 scp2 md1 scp2 md0 scp1 md1 scp1 md0 scp0 md1 scp0 md0 initial value: 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w scpdr bit: 7 6 5 4 3 2 1 0 scp7dt scp6dt scp5dt scp4dt scp3dt scp2dt scp1dt scp0dt initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w sci pin i/o and data control are performed by bits 3 to 0 of scpcr and bits 1 and 0 of scpdr. scpcr bits 3 and 2?serial clock port i/o (scp1md1, scp1md0): these bits specify serial port sck0 pin i/o. when the sck0 pin is ac tually used as a port i/o pin, clear the c/ a bit of scsmr and bits cke1 and cke0 of scscr to 0. bit 3: scp1md1 bit 2: scp1md0 description 0 0 scp1dt bit value is not output to sck0 pin 1 scp1dt bit value is output to sck0 pin 1 0 sck0 pin value is read from scp1dt bit 1 (initial values: 1 and 0)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 500 of 1036 rej09b0254-0600 scpdr bit 1?serial clock port data (scp1dt): specifies the serial port sck0 pin i/o data. input or output is specified by the scp1md0 and scp1md1 bits. in output mode, the value of the scp1dt bit is output from the sck0 pin. bit 1: scp1dt description 0 i/o data is low (initial value) 1 i/o data is high scpcr bits 1 and 0?serial port break i/o (scp0md1, scp0md0): these bits specify the serial port txd0 pin output condition. when the txd0 pin is actually used as a port output pin and outputs the value set with the scp0dt bit, clear the te bit of scscr to 0. bit 1: scp0md1 bit 0: scp0md0 description 0 0 scp0dt bit value is not output to txd0 pin (initial value) 0 1 scp0dt bit value is output to txd0 pin scpdr bit 0?serial port break data (scp0dt): specifies the serial port rxd0 pin input data and txd0 pin output data. the txd0 pin output condition is specified by the scp0md0 and scp0md1 bits. when the txd0 pin is set to outp ut mode, the value of the scp0dt bit is output to the txd0 pin. the rxd0 pin value is read from the scp0dt bit regardless of the values of the scp0md0 and scp0md1 bits, if re in the scscr is set to 1. the initial value of this bit after a power-on reset is undefined. bit 0: scp0dt description 0 i/o data is low (initial value) 1 i/o data is high block diagrams of the sci i/o ports are shown in figures 17.2 to 17.4. 17.2.9 bit rate register (scbrr) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 501 of 1036 rej09b0254-0600 the bit rate register (scbrr) is an eight-bit regist er that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (scsmr), determines the serial tr ansmit/receive bit rate. the cpu can always read and write the scbrr. the scbrr is initialized to h'ff by a reset or in module standby or standby mode. each channel has independent baud rate generator control, so different values can be set in two channels. the scbrr setting is calculated as follows: asynchronous mode: n = p 64 2 2n?1 b 10 6 ? 1 clock synchronous mode: n = p 8 2 2n?1 b 10 6 ? 1 b: bit rate (bit/s) n: scbrr setting for baud rate generator (0 n 255) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 17.3.) table 17.3 scsmr settings scsmr settings n clock source cks1 cks0 0 p 0 0 1 p /4 0 1 2 p /16 1 0 3 p /64 1 1 note: find the bit rate error for the asynchronous mode by the following formula: p 10 6 error ( % ) = (n + 1) b 64 2 2n?1 ? 1 100 table 17.4 lists examples of scbrr settings in the asynchronous mode; table 17.5 lists examples of scbrr settings in the clock synchronous mode.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 502 of 1036 rej09b0254-0600 table 17.4 bit rates and scbrr sett ings in asynchronous mode (1) p (mhz) 2 2.097152 2.4576 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 2400 0 25 0.16 0 26 1.14 0 31 0.00 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 19200 0 2 8.51 0 2 13.78 0 3 0.00 31250 0 1 0.00 0 1 4.86 0 1 22.88 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 table 17.4 bit rates and scbrr sett ings in asynchronous mode (2) p (mhz) 3 3.6864 4 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 ?2.34 0 23 0.00 0 25 0.16 9600 0 9 ?2.34 0 11 0.00 0 12 0.16 19200 0 4 ?2.34 0 5 0.00 0 6 ?6.99 31250 0 2 0.00 ? ? ? 0 3 0.00 38400 ? ? ? 0 2 0.00 0 2 8.51
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 503 of 1036 rej09b0254-0600 table 17.4 bit rates and scbrr sett ings in asynchronous mode (3) p (mhz) 4.9152 5 6 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 86 0.31 2 88 ?0.25 2 106 ?0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 ?1.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 ?2.34 19200 0 7 0.00 0 7 1.73 0 9 ?2.34 31250 0 4 ?1.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 ?2.34 table 17.4 bit rates and scbrr sett ings in asynchronous mode (4) p (mhz) 6.144 7.3728 8 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 0.00 0 5 0.00 0 6 ?6.99
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 504 of 1036 rej09b0254-0600 table 17.4 bit rates and scbrr sett ings in asynchronous mode (5) p (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00 table 17.4 bit rates and scbrr sett ings in asynchronous mode (6) p (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 505 of 1036 rej09b0254-0600 table 17.4 bit rates and scbrr sett ings in asynchronous mode (7) p (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 506 of 1036 rej09b0254-0600 table 17.5 bit rates and scbrr sett ings in clock synchronous mode p (mhz) 4 8 16 28.7 30 bit rate (bits/s) n n n n n n n n n n 110 ? ? ? ? ? ? ? ? ? ? 250 2 249 3 124 3 249 ? ? ? ? 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 ? ? 0 29 500k 0 1 0 3 0 7 ? ? 0 14 1m 0 0 * 0 1 0 3 ? ? ? ? 2m 0 0 * 0 1 ? ? ? ? notes: settings with an error of 1 % or less are recommended. blank: no setting possible ?: setting possible, but error occurs. (ref er to section 17.2.9 , bit rate register (scbrr)) * : continuous transmit/receive not possible as transfer capability to the buffer becomes insufficient.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 507 of 1036 rej09b0254-0600 table 17.6 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. tables 17.7 and 17.8 list the maximum rates for external clock input. table 17.6 maximum bit rates for variou s frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 508 of 1036 rej09b0254-0600 table 17.7 maximum bit rates during external clock input (asynchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 17.8 maximum bit rates during external clock input (clock synchronous mode) p (mhz) external input clock (mhz) maximum bit rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 509 of 1036 rej09b0254-0600 17.3 operation 17.3.1 overview for serial communication, the sci has an as ynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (scsmr), as listed in table 17 .9. the sci clock source is selected by the combination of the c/ a bit in the serial mode register (scsmr) and the cke1 and cke0 bits in the serial control register (scscr), as listed in table 17.10. asynchronous mode: ? data length is selectable: seven or eight bits. ? parity and multiprocessor bits are selectable. so is the stop bit length (one or two bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing erro rs, parity errors, overrun errors and breaks. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) clock synchronous mode: ? the transmission/reception format ha s a fixed eight-bit data length. ? in receiving, it is possible to detect overrun errors. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and outputs a synchronous clock signal to external devices. ? when an external clock is selected, the sci operates on the input synchronous clock. the on-chip baud rate generator is not used.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 510 of 1036 rej09b0254-0600 table 17.9 serial mode register se ttings and sci communication formats scsmr settings sci communication format bit 7 c/ a bit 6 chr bit 5 pe bit 2 mp bit 3 stop mode data length parity bit multipro- cessor bit stop bit length 0 0 0 0 0 8-bit not set not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 1 0 0 7-bit not set 1 bit 1 2 bits 1 0 set 1 bit 1 asynchronous 2 bits 0 * 1 0 8-bit not set set 1 bit * 1 2 bits 1 * 0 7-bit 1 bit * 1 asynchronous (multiprocessor format) 2 bits 1 * * * * clock synchronous 8-bit not set none note: * don?t care. table 17.10 scsmr and scscr setting s and sci clock source selection scsmr scscr settings sci transmit/receive clock bit 7 c/ a bit 1 cke1 bit 0 cke0 mode clock source sck0 pin function 0 0 0 internal sci does not use the sck0 pin 1 outputs a clock with frequency matching the bit rate 1 0 external 1 asynchronous mode inputs a clock with frequency 16 times the bit rate 1 0 0 internal outputs the synchronous clock 1 1 0 external inputs the synchronous clock 1 clock synchronous mode
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 511 of 1036 rej09b0254-0600 17.3.2 operation in asynchronous mode in the asynchronous mode, each tr ansmitted or received character begi ns with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sc i are independent, so fu ll duplex communication is possible. the transmitter and r eceiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous tran smitting and receiving. figure 17.5 shows the general format of asyn chronous serial communicat ion. in asynchronous serial communication, the communication line is norm ally held in the mark (high) state. the sci monitors the line and starts serial communicati on when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in the asynchronous mode, the sc i synchronizes on the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock w ith a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (character or frame) idling (marking) parity bit stop bit 1 or no bit 1 or 2 bits figure 17.5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) transmit/receive formats table 17.11 lists the 12 communication formats that can be selected in the asynchronous mode. the format is selected by settings in the serial mode register (scsmr).
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 512 of 1036 rej09b0254-0600 table 17.11 serial communication formats (asynchronous mode) scsmr bits serial transmit/receive format and frame length chr pe mp stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 start 8-bit data stop 0 0 0 1 start 8-bit data stop stop 0 1 0 0 start 8-bit data p stop 0 1 0 1 start 8-bit data p stop stop 1 0 0 0 start 7-bit data stop 1 0 0 1 start 7-bit data stop stop 1 1 0 0 start 7-bit data p stop 1 1 0 1 start 7-bit data p stop stop 0 ? 1 0 start 8-bit data mpb stop 0 ? 1 1 start 8-bit data mpb stop stop 1 ? 1 0 start 7-bit data mpb stop 1 ? 1 1 start 7-bit data mpb stop stop notes: ?: don?t care bits start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 513 of 1036 rej09b0254-0600 clock an internal clock generated by the on-chip baud rate generator or an external clock input from the sck0 pin can be selected as the sci transmit/recei ve clock. the clock sour ce is selected by the c/ a bit in the serial mode register (scsmr) an d bits cke1 and cke0 in the serial control register (scscr) (table 17.10). when an external clock is input at the sck0 pin, it must have a frequency equal to 16 times the desired bit rate. when the sci operates on an internal clock, it can output a clock signal at the sck0 pin. the frequency of this output clock is equal to the bit rate . the phase is aligned as in figure 17.6 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 d0d1d2d3d4d5d6d70/1 1 1 1 frame figure 17.6 relationship between output clock and transfer data phase (asynchronous mode) transmitting and receiving data sci initialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci as follows. when changing the operation mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clear ing te to 0 sets tdre to 1 and initializes the transmit shift register (sctsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags or receive data register (scrdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 17.7 is a sample flowchart for initializing the sci. the procedure for initializing the sci is:
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 514 of 1036 rej09b0254-0600 initialize clear te and re bits in scscr to 0 select transmit/receive format in scsmr set value to scbrr set cke1 and cke0 bits in scscr (te and re bits are 0) wait set te or re in scscr to 1. also set rie, tie, teie, and mpie as necessary. has a 1-bit interval elapsed? end (2) (3) (1) (4) no yes (1) select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te, and re cleared to 0. if clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to scscr. (2) select the communication format in the serial mode register (scsmr). (3) write the value corresponding to the bit rate in the bit rate register (scbrr) unless an external clock is used. (4) wait at least one bit interval, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie, and mpie as necessary. setting te and re enables the txd0 and rxd0 pins to be used. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit). figure 17.7 sample sci initialization flowchart
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 515 of 1036 rej09b0254-0600 serial data transmission (asynchronous mode): figure 17.8 shows a sample flow chart for se rial data transmission. after enabling the sci transmission, transmit serial data following the procedure shown below: tdre = 1? write transmission data to sctdr and clear tdre bit in scssr to 0 all data transmitted? yes tend = 1? read tend bit in scssr break output? yes clear te bit scscr to 0 end transmission yes read tdre bit in scssr no no yes no no (1) (2) (3) start transmission set scpdr and scpcr (1) sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. (2) to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. (3) to output a break at the end of serial transmission: set the sc port data register (scpdr) and sc port control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). for scpcr and scpdr settings, see section 17.2.8, port sc control register (scpcr)/port sc data register (scpdr). figure 17.8 sample serial transmission flowchart
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 516 of 1036 rej09b0254-0600 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the scssr. when tdre is cleared to 0, the sci recognizes that the transmit data register (sctdr) contains new data, and loads this data from the sctdr into the transmit shift register (sctsr). 2. after loading the data from the sctdr into the sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the tran smit-data-empty interrupt enable bit (tie) is set to 1 in the scscr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd0 pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from th e sctdr into the sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in the scssr, outputs the stop bit, then continues output of 1 bits (marking). if the transmit-end in terrupt enable bit (teie) in the scscr is set to 1, a transmit-end interrupt (tei) is requested. figure 17.9 shows an example of sci transmit operation in the asynchronous mode.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 517 of 1036 rej09b0254-0600 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (marking) txi interrupt request generated tei interrupt request generated writes data to sctdr with the txi interrupt processing routine and clear tdre bit to 0 1 frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 txi interrupt request generated figure 17.9 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 518 of 1036 rej09b0254-0600 serial data reception (asynchronous mode): figure 17.10 shows a sample flow chart for serial data reception. after en abling the sci reception, receive serial data following the procedure shown below: start reception read orer, per, and fer bits in scssr all data received? end reception (1) no yes per, fer, orer = 1? rdrf = 1? yes yes clear the re bit in scscr to 0 no no read the rdrf bit in scssr error processing (3) (2) read reception data of scrdr and clear rdrf bit in scssr to 0 (1) receive error processing and break detection: if a receive error occurs, read the orer, per and fer bits of the scssr to identify the error. after executing the necessary error processing, clear orer, per and fer all to 0. receiving cannot resume if orer, per or fer remain set to 1. when a framing error occurs, the rxd0 pin can be read to detect the break state. (2) sci status check and receive- data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. (3) to continue receiving serial data: read the scrdr receive data and clear the rdrf flag in scssr to 0 before the stop bit of the current frame is received. figure 17.10 sample serial reception data flowchart (1)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 519 of 1036 rej09b0254-0600 error processing orer = 1? overrun error processing fer = 1? yes break? no framing error processing per = 1? yes parity error processing clear orer, per, and fer bits in scssr to 0 end no no no yes yes clear re bit in scscr to 0 figure 17.10 sample serial reception data flowchart (2)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 520 of 1036 rej09b0254-0600 in receiving, the sci operates as follows: 1. the sci monitors the communication line. when it detects a start bit (0), the sci synchronizes internally and starts receiving. 2. receive data is shifted into the s crsr in order from the lsb to the msb. 3. the parity bit and stop bit ar e received. after receiving these bits, the sci makes the following checks: a. parity check: the number of 1s in the recei ve data must match the even or odd parity setting of the o/ e bit in the scsmr. b. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check: rdrf must be 0 so that receive data can be loaded from the scrsr into the scrdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in the scrdr. if one of the checks fails (receive error), the sci operates as indicated in table 17.12. note: when a receive error flag is set, further recei ving is disabled. the rdrf bit is not set to 1. be sure to clear the error flags. 4. after setting rdrf to 1, if th e receive-data-full interrupt enable bit (rie) is set to 1 in the scscr, the sci requests a receive -data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data- full interrupt enab le bit (rie) in the scscr is also set to 1, the sci requests a receive-error interrupt (eri). table 17.12 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in scssr receive data not loaded from scrsr into scrdr framing error fer stop bit is 0 receive data loaded from scrsr into scrdr parity error per parity of receive data differs from even/odd parity setting in scsmr receive data loaded from scrsr into scrdr figure 17.11 shows an example of sci rece ive operation in the asynchronous mode.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 521 of 1036 rej09b0254-0600 rdrf fer eri interrupt request generated by framing error 1 frame reads data with the rxi interrupt processing routine and clears rdrf bit to 0 rxi interrupt request generated 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idling (marking) d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 17.11 example of sci operation in reception (example with 8-bit data, parity, one stop bit) 17.3.3 multiprocessor communication the multiprocessor communication function enables se veral processors to share a single serial communication line. the processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is ad dressed by a unique id. a serial communication cy cle consists of an id-sending cy cle that identifies the receiving processor, and a data-sending cycle. the multipro cessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the mu ltiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receivi ng processors compare the data with their ids. the receiving pr ocessor with a matching id con tinues to receive further incoming data. processors with ids not matching the recei ved data skip further incoming data until they
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 522 of 1036 rej09b0254-0600 again receive data with the multip rocessor bit set to 1. multiple processors can send and receive data in this way. figure 17.12 shows an example of communication among processors using the multiprocessor format. receiving station a (id = 01) (id = 02) (id = 03) (id = 04) receiving station b receiving station c serial communications circuit h'01 h'aa (mpb = 0) (mpb = 1) id transmit cycle = specifies receiving station serial data transmitting station receiving station d data transmit cycle = data transmission to receiving station specified by id mpb: multiprocessor bit figure 17.12 example of communica tion using multiprocessor format (transmission of data h'aa to receiving station a) communication formats four formats are available. parity-bit settings are ignored when the multiprocessor format is selected. for details see table 17.11. clock see the description in the asynchronous mode section.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 523 of 1036 rej09b0254-0600 transmitting and receiving data multiprocessor serial data transmission: figure 17.13 shows a sample flow chart for multip rocessor serial data transmission. after enabling the sci transmission, transmit multiprocessor serial data following the procedure shown below: tdre = 1? write transmission data to sctdr and set mpbt bit in scssr transmission ended? yes tend = 1? read tend bit in scssr break output? yes set scpdr and scpcr end transmission yes read tdre bit in scssr clear tdre bit to 0 no no yes no no (1) (2) (3) start transmission clear te bit scscr to 0 (1) sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in scssr. finally, clear tdre to 0. (2) to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. (3) to output a break at the end of serial transmission: set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). for scpcr and scpdr settings, see section 17.2.8, port sc control register (scpcr)/port sc data register (scpdr). figure 17.13 sample multiprocessor serial transmission flowchart
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 524 of 1036 rej09b0254-0600 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data, and loads this data from the sctdr into the transmit shift register (sctsr). 2. after loading the data from the sctdr into the sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transm it-data-empty interrupt enable bit (tie) in the scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd0 pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads data from the sctdr into the sctsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in the scssr to 1, outputs the stop bit, then continues output of 1 bits in the marking state. if the transmit-e nd interrupt enable bit (teie) in the scscr is set to 1, a transmit-en d interrupt (tei) is requested at this time. figure 17.14 shows sci transmissi on in the multiprocessor format.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 525 of 1036 rej09b0254-0600 tdre tend txi interrupt request generated txi interrupt request generated tei interrupt request generated writes data to tdr with the txi interrupt pro- cessing routine and clears tdre bit to 0 1 frame 01 1 1 0/1 0 1 multi- processor bit serial data start bit data stop bit start bit data stop bit idling (marking) d 0 d 1 d 7 d 0 d 1 d 7 0/1 multi- processor bit figure 17.14 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 526 of 1036 rej09b0254-0600 multiprocessor serial data reception: figure 17.15 shows a sample flow chart for mul tiprocessor serial data reception. after enabling the sci reception, receive mu ltiprocessor serial data followi ng the procedure shown below: rdrf = 1? fer = 1 or orer = 1? rdrf = 1? all data received? no end reception yes set mpie bit in scscr to 1 read rdrf bit in scssr clear re bit in scscr to 0 no no (1) (2) read orer and fer bits in scssr fer = 1 or orer = 1? read rdrf bit in scssr read receive data in scrdr is id the station?s id? yes read orer and fer bits in sscsr (3) no error processing yes yes (4) yes no start reception no yes read receive data in scrdr (1) id receive cycle: set the mpie bit in the serial control register (scscr) to 1. (2) sci status check and compare to id reception: read the serial status register (scssr), check that rdrf is set to 1, then read data from the receive data register (scrdr) and compare with the processor's own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. (3) sci status check and data receiving: read scssr, check that rdrf is set to 1, then read data from the receive data register (scrdr). (4) receive error processing and break detection: if a receive error occurs, read the orer and fer bits in scssr to identify the error. after executing the necessary error processing, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd0 pin can be read to detect the break state. figure 17.15 sample multiprocessor serial reception flowchart (1)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 527 of 1036 rej09b0254-0600 orer = 1? break? yes framing error processing yes error processing overrun error processing yes fer = 1? clear orer and fer bits in scssr to 0 end no no no clear re bit in scscr to 0 figure 17.15 sample multiprocessor serial reception flowchart (2)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 528 of 1036 rej09b0254-0600 figure 17.16 shows an example of sci rece ive operation using a multiprocessor format. rdrf mpie rdr value id1 rxi interrupt request (multiprocessor interrupt) generated, mpie = 0 reads rdr data with the rxi interrupt processing routine and clears rdrf bit to 0 (a) own id does not match data (b) own id matches data id is not station?s id, so mpie bit is set to 1 again no rxi interrupt, generated rdr state is maintained 01 1 1 10 1 stop bit mpb serial data start bit data (id1) data (data 1) start bit mpb stop bit idling (marking) d 0 d 1 d 7 d 0 d 1 d 7 0 rdrf mpie rdr value id1 id2 data2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idling (marking) d 0 d 1 d 7 d 0 d 1 d 7 0 rxi interrupt request (multiprocessor interrupt) generated, mpie = 0 reads rdr data with the rxi interrupt processing routine and clears rdrf bit to 0 id is that of station, so reception continues unchanged and data is received by the rxi interrupt processing routine mpie bit set to 1 again figure 17.16 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 529 of 1036 rej09b0254-0600 17.3.4 clock synchronous operation in the clock synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. the tran smitter and receiver are also d ouble buffered, so continuous transmitting or receiving is possibl e by reading or writing data while transmitting or receiving is in progress. figure 17.17 shows the general format in clock synchronous serial communication. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb synchroni- zation clock serial data don't care ** one unit of communication data (character or frame) note: * high except in continuous transmitting or receiving figure 17.17 data format in clock synchronous communication in clock synchronous se rial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. data are guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transm itted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remains in the state of the msb. in the clock synchronous mode, the sci transmits or receives data by synchronizing with the rising edge of th e serial clock.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 530 of 1036 rej09b0254-0600 communication format the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock an internal clock generated by the on-chip baud rate generator or an external clock input from the sck0 pin can be selected as the sci transmit/recei ve clock. the clock sour ce is selected by the c/ a bit in the serial mode register (scsmr) an d bits cke1 and cke0 in the serial control register (scscr). see table 17.10. when the sci operates on an internal clock, it outputs the clock signal at the sck0 pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high st ate. when only receiving, the sci receives in 2- character units, so a 16 pulse sy nchronization clock is output. to receive in 1-character units, select an external clock source. transmitting and receiving data sci initialization (clock synchronous mode) before transmitting and receiving data, the te and re bits in scscr should be cleared to 0, then the sci should be initialized as described in a sample flowchart in figure 17.18. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and the transmit shift register (sctsr) is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of scrdr. figure 17.18 is a sample flowchart for initializing the sci.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 531 of 1036 rej09b0254-0600 initialize clear te and re bits in scscr to 0 (1) has a 1-bit period elapsed? set te and re bits in scscr to 1 and set rie, tie, teie, and mpie bits set transmit/receive format in scsmr yes no set value in scbrr set rie, tie, teie, mpie, cke1, and cke0 bits in scscr (te and re are 0) end wait (2) (3) (4) (1) select the clock source in the serial control register (scscr). leave rie, tie, teie, mpie, te and re cleared to 0. (2) select the communication format in the serial mode register (scsmr). (3) write the value corresponding to the bit rate in the bit rate register (scbrr) unless an external clock is used. (4) wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scscr) to 1. also set rie, tie, teie and mpie. setting te and re allows use of the txd0 and rxd0 pins. figure 17.18 sample sci initialization flowchart
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 532 of 1036 rej09b0254-0600 serial data transmission (clock synchronous mode): figure 17.19 shows a sample flow chart for se rial data transmission. after enabling the sci transmission, transmit serial data following the procedure shown below: start transmission read tdre bit in scssr all data transmitted? yes no end transmission (1) (2) tdre = 1? write transmission data to sctdr and clear tdre bit in scssr to 0 yes no read tend bit in scssr tend = 1? yes no clear te bit in scscr to 0 (1) sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. (2) to continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0. figure 17.19 sample serial transmission flowchart
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 533 of 1036 rej09b0254-0600 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the scssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (sctdr) contains new data and loads this data from the sctdr into the transmit shift register (sctsr). 2. after loading the data from the sctdr into the sctsr, the sci sets the tdre bit to 1 and starts transmitting. if the transm it-data-empty interrupt enable bit (tie) in the scscr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output mode is selected, the sci outputs eight synchronous clock pu lses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data are output from the txd0 pin in order from the lsb (bit 0) to the msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from the sctdr into the sctsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in the scssr to 1, transmits the msb, then holds the transmit data pin (txd0) in the msb state. if th e transmit-end interrupt enable bit (teie) in the scscr is set to 1, a transmit-end inte rrupt (tei) is requested at this time. 4. after the end of serial transmission, th e sck0 pin is held in the high state. figure 17.20 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 synchronization clock serial data transfer direction bit 7 writes data to tdr with the txi interrupt processing routine and clears tdre bit to 0 1 frame tdre tend lsb msb txi interrupt request generated txi interrupt request generated tei interrupt request generated figure 17.20 sample sci transmission operation in clocked synchronous mode
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 534 of 1036 rej09b0254-0600 serial data reception (clo ck synchronous mode): figure 17.21 shows a sample flow chart for serial data reception. after enabling the sci transmission, transmit serial data following the procedure shown below: when switching from the asynchronous mode to the clock synchronous mode, make sure that orer, per, and fer are cleared to 0. if per or fe r is set to 1, the rdrf bit will not be set and both transmitting and receiving will be disabled. read orer bit in scssr all data received? end reception no yes orer = 1? rdrf = 1? yes clear re bit in scscr to 0 no no read rdrf bit in scssr (3) (2) yes error processing (1) read receive data in scrdr and clear rdrf bit in scssr to 0 start reception (1) receive error processing: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error processing, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. (2) sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. (3) to continue receiving serial data: read scrdr, and clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. figure 17.21 sample serial reception flowchart (1)
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 535 of 1036 rej09b0254-0600 error processing end orer = 1? no clear orer bit in scssr to 0 yes overrun error processing figure 17.21 sample serial reception flowchart (2) in receiving, the sci operates as follows: 1. the sci synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into the scrsr in or der from the lsb to the msb. after receiving the data, the sci checks that rdrf is 0 so that r eceive data can be loaded from the scrsr into the scrdr. if this check is passed, the sci sets rdrf to 1 and stores the received data in the scrdr. if the check is not passed (receive error), the sci operates as indicated in table 17.12. this state prevents further transmission or recep tion. while receiving, th e rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if th e receive-data-full interrupt enable bit (rie) is set to 1 in the scscr, the sci requests a receive-d ata-full interrupt (rxi). if th e orer bit is set to 1 and the receive-data-full interrupt enable bit (rie) in th e scscr is also set to 1, the sci requests a receive-error interrupt (eri). figure 17.22 shows an example of the sci receive operation.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 536 of 1036 rej09b0254-0600 bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 synchronization clock serial data transfer direction bit 7 reads data with the rxi interrupt processing routine and clears rdrf bit to 0 1 frame rxi interrupt request generated rxi interrupt request generated eri interrupt request generated by overrun error rdrf orer figure 17.22 example of sci operation in reception transmitting and receiving serial data simultaneously (clock synchronous mode) figure 17.23 shows a sample fl owchart for simultaneous serial transmit and receive operations. after enabling the sci transmissi on/reception, provide simultaneous serial transmit and receive operations following the procedure shown below:
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 537 of 1036 rej09b0254-0600 start transmission/reception read tdre bit in scssr all data transmitted/received? end transmission/reception (1) no yes tdre = 1? write transmission data to sctdr and clear tdre bit in scssr to 0 rdrf = 1? no yes yes no read orer bit in scssr error processing (2) orer = 1? no read rdrf bit in scssr (4) yes (3) read receive data of scrdr and clear rdrf bit in scssr to 0 clear te and re bits in scscr to 0 (1) sci status check and transmit data write: read the serial status register (scssr), check that the tdre bit is 1, then write transmit data in the transmit data register (sctdr) and clear tdre to 0. the txi interrupt can also be used to determine if the tdre bit has changed from 0 to 1. (2) receive error processing: if a receive error occurs, read the orer bit in scssr to identify the error. after executing the necessary error processing, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. (3) sci status check and receive data read: read the serial status register (scssr), check that rdrf is set to 1, then read receive data from the receive data register (scrdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. (4) to continue transmitting and receiving serial data: read the rdrf bit and scrdr, and clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. also read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in sctdr, then clear tdre to 0 before the msb (bit 7) of the current frame is transmitted. note: when switching transmit or receive operation to simultaneous serial transmit and receive operations, first clear the te bit and re bit to 0, and then set both these bits to 1 simultaneously. figure 17.23 sample flowchart of simultaneo us serial transmit and receive operations
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 538 of 1036 rej09b0254-0600 17.4 sci interrupt sources the sci has four interrupt sources in each chan nel: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transm it-data-empty (txi). table 17.13 lists the interrupt sources and indicates their priority. these interrupts can be en abled and disabled by the tie, rie, and teie bits in the serial control register (scscr). each in terrupt request is sent se parately to the interrupt controller. txi is requested when the tdre bit in the scssr is set to 1. rxi is requested when the rdrf bit in the scssr is set to 1. eri is requested when the orer, per, or fer bit in the scssr is set to 1. tei is requested when the tend bit in the scssr is set to 1. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation is complete. table 17.13 sci interrupt sources interrupt source description priority when reset is cleared eri receive error (orer, per, or fer) high rxi receive data full (rdrf) txi transmit data empty (tdre) tei transmit end (tend) low see section 4, exception handling, for informati on on the priority order and relationship to non- sci interrupts.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 539 of 1036 rej09b0254-0600 17.5 usage notes note the following points when using the sci. sctdr write and tdre flags: the tdre bit in the serial status register (scssr) is a status flag indicating loading of transmit data from the sctdr into the sctsr. the sci sets tdre to 1 when it transfers data from the sctdr to th e sctsr. data can be written to the sctdr regardless of the tdre bit state. if new data is written in the sctdr when tdre is 0, however, the old data stored in the sctdr will be lost beca use the data has not yet been transferred to the sctsr. before writing transmit data to the sctdr, be sure to check that tdre is set to 1. simultaneous multiple receive errors: table 17.14 indicates the state of the scssr status flags when multiple receive errors occur simulta neously. when an over run error occurs, the scrsr contents cannot be transferred to the scrdr, so receive data is lost. table 17.14 scssr status flags and transfer of receive data scssr status flags receive data transfer receive error status rdrf orer fer per scrsr scrdr overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x x: receive data is not transferred from scrsr to scrdr. o: receive data is transferred from scrsr to scrdr. break detection and processing: break signals can be detected by reading the rxd0 pin directly when a framing error (fer) is detected. in the break state, the input from the rxd0 pin consists of all 0s, so fer is set and the parity error flag (p er) may also be set. in the break state, the sci receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. sending a break signal: the txd0 pin i/o condition and level can be determined by means of the scp0dt bit of the port sc data register (scpdr) and bits scp0md0 and scp0md1 of the port sc control register (scpcr). these bits can be used to send breaks. to send a break during serial transmission, clear the scp0dt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd0 pin.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 540 of 1036 rej09b0254-0600 tend flag and te bit processing: the tend flag is set to 1 during transmission of the stop bit of the last data. consequently, if the te bit is cleared to 0 immediately after setting of the tend flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. therefore, the te bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the tend flag setting is confirmed. receive error flags and transmitter oper ation (clock synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, the sci will not st art transmitting even if tdre is set to 1. be sure to clear the receive erro r flags to 0 before starting to transmit. note that clearing re to 0 does not clea r the receive error flags. receive data sampling timing and reception margin in the asynchronous mode: in the asynchronous mode, the sci operates on a base clock of 16 times the transfer rate frequency. in receiving, the sci synchronizes in ternally with the falling edge of the start bit, which it samples on the base clock. receive data is latched on the rising edge of the eighth base clock pulse (figure 17.24). 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 basic clock receive data (rxd0) synchro- nization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 17.24 receive data sampling timing in asynchronous mode
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 541 of 1036 rej09b0254-0600 the reception margin in the asynchronous mode is given by formula 1. formula 1: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100% where: m = reception margin ( % ) n = ratio of clock frequency to bit rate (n = 16) d = clock duty cycle (d = 0?1.0) l = frame length (l = 9?12) f = absolute deviation of clock frequency assuming values of f = 0, d = 0.5 and n = 372 in formula (1), the reception margin is given by formula 2. formula 2: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % this is a theoretical value. a reasonable margin to allow in system designs is 20 to 30%. cautions for clock synchronous external clock mode: ? set te = re = 1 only when the external clock sck0 is 1. ? do not set te = re = 1 until at least four clocks after the external clock sck0 has changed from 0 to 1. ? when receiving, rdrf is 1 when re is set to zero 2.5 to 3.5 clocks after the rising edge of the sck0 input of the d7 bit in rxd0, but it cannot be copied to scrdr. caution for clock synchronous internal clock mode: when receiving, rdrf is 1 when re is set to zero 1.5 clocks after the rising edge of the sck0 output of the d7 bit in rxd0, but it cannot be copied to scrdr.
section 17 serial communication interface (sci) rev.6.00 mar. 27, 2009 page 542 of 1036 rej09b0254-0600
section 18 smart card interface rev.6.00 mar. 27, 2009 page 543 of 1036 rej09b0254-0600 section 18 smart card interface 18.1 overview as an additional serial communications interface function, a smart card (i ntegrated circuit card) interface (sci) that is compatible with the t = 0 data transfer protocol of iso/iec standard 7816- 3 (identification card) is supported. register settings are used to switch between the ordinary serial communication interface and the smart card interface. 18.1.1 features the smart card interface has the following features: ? asynchronous mode ? data length: eight bits ? parity bit generation and check ? receive mode error signal detection (parity error) ? transmit mode error signal detection and automatic re-transmission of data ? supports both direct convention and inverse convention ? bit rate can be selected using on-chip baud rate generator. ? three types of interrupts: transmit-data-emp ty, receive-data-full, and communication-error interrupts are requested independently.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 544 of 1036 rej09b0254-0600 18.1.2 block diagram figure 18.1 shows a block diagram of the smart card interface. rxd0 txd0 sck0 sci scbrr scscr scsmr sctdr sctsr scrdr scrsr scscmr scssr parity generation parity check clock external clock module data bus internal data bus p p /4 p /16 p /64 txi rxi eri bus interface baud rate generator transmit/ receive control scscmr: scrsr: scrdr: sctsr: sctdr: scsmr: scscr: scssr: scbrr: smart card mode register receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register legend: figure 18.1 smart card interface block diagram
section 18 smart card interface rev.6.00 mar. 27, 2009 page 545 of 1036 rej09b0254-0600 18.1.3 pin configuration table 18.1 summarizes the smart card interface pins. table 18.1 sci pins pin name abbreviation i/o function serial clock pin sck0 output clock output receive data pin rxd0 input receive data input transmit data pin txd0 ou tput transmit data output 18.1.4 register configuration table 18.2 summarizes the registers used by the smart card interface. the scsmr, scbrr, scscr, sctdr, and scrdr registers are the same as in the ordinary sci function. they are described in section 17, serial communication interface (sci). table 18.2 registers name abbreviation r/w initial value * 3 address access size serial mode register scsmr r/w h'00 h'fffffe80 8 bit rate register scbrr r/w h'ff h'fffffe82 8 serial control register scscr r/w h'00 h'fffffe84 8 transmit data register sctdr r/w h'ff h'fffffe86 8 serial status register scssr r/(w) * 1 h'84 h'fffffe88 8 receive data register scrdr r h'00 h'fffffe8a 8 smart card mode register scscmr r/w * 2 h'fffffe8c 8 notes: 1. only 0 can be written, to clear the flags. 2. bits 0, 2, and 3 are cleared. the value of the other bits is undefined. 3. initialized by a power-on or manual reset.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 546 of 1036 rej09b0254-0600 18.2 register descriptions this section describes the registers added for the smart card interface and the bits whose functions are changed. 18.2.1 smart card mode register (scscmr) the smart card mode register (scscmr) is an 8- bit read/write register that selects smart card interface functions. scscmr bits 0, 2, and 3 ar e initialized to h?00 by a reset and in standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? sdir sinv ? smif initial value: ? ? ? ? 0 0 ? 0 r/w: r r r r r/w r/w r r/w bits 7 to 4 and 1?reserved: these bits are always read as 0. the write value should always be 0. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3: sdir description 0 contents of sctdr are transferred as lsb first, receive data is stored in scrdr as lsb first. (initial value) 1 contents of sctdr are transferred as msb first, receive data is stored in scrdr as msb first. bit 2?smart card data inversion (sinv): specifies whether to invert the logic level of the data. this function is used in combination with b it 3 for transmitting and receiving with an inverse convention card. sinv does not affect the logic leve l of the parity bit. see section 18.3.4, register settings, for information on how parity is set. bit 2: sinv description 0 contents of sctdr are transferred un changed, receive data is stored in scrdr unchanged. (initial value) 1 contents of sctdr are inverted before tr ansfer, receive data is inverted before storage in scrdr.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 547 of 1036 rej09b0254-0600 bit 0?smart card interface mode select (smif): enables the smart car d interface function. bit 0: smif description 0 smart card interface function disabled (initial value) 1 smart card interface function enabled 18.2.2 serial status register (scssr) in the smart card interface mode, the function of scssr bit 4 is changed. the setting conditions for bit 2, the tend bit, are also changed. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer/ers per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear the flag. bits 7 to 5? these bits have the same function as in the ordinary sci. see section 17, serial communication interface (sci), for more information. bit 4?error signal status (ers): in the smart card interface mode, bit 4 indicates the state of the error signal returned from the receiving si de during transmission. the smart card interface cannot detect framing errors. bit 4: ers description 0 receiving ended normally with no error signal. (initial value) ers is cleared to 0 when the chip is reset or enters standby mode, or when software reads ers after it has been set to 1, then writes 0 in ers. 1 an error signal indicating a parity error was transmitted from the receiving side. ers is set to 1 if the error signal sampled is low. note: the ers flag maintains its state even when the te bit in scscr is cleared to 0.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 548 of 1036 rej09b0254-0600 bits 3 to 0? these bits have the same function as in the ordinary sci. see section 17, serial communication interface (sci), for more inform ation. the setting conditions for bit 2, the transmit end bit (tend), are changed as follows. bit 2: tend description 0 transmission is in progress. tend is cleared to 0 when software reads tdre after it has been set to 1, then writes 0 in tdre. 1 end of transmission. (initial value) tend is set to 1 when: ? the chip is reset or enters standby mode, ? the te bit in scscr is 0 and the fer/ers bit is also 0, ? the c/ a bit in scsmr is 0, and tdre = 1 and fer/ers = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted, or ? the c/ a bit in scsmr is 1, and tdre = 1 and fer/ers = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. note: etu: elementary time unit (time for transfer of 1 bit) 18.3 operation 18.3.1 overview the primary functions of the smart card interface are described below. 1. each frame consists of 8-bit data and 1 parity bit. 2. during transmission, the card l eaves a guard time of at least 2 etu (elementary time units: time for transfer of 1 bit) from th e end of the parity bit to the start of the next frame. 3. during reception, the card output s an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. during transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 549 of 1036 rej09b0254-0600 18.3.2 pin connections figure 18.2 shows the pin connection diagram for the smart card interface. during communication with an ic card, transmission an d reception are both carried out over the same data transfer line, so connect the txd0 and rxd0 pins on the chip. pull up the data transfer line to the power supply v cc side with a resistor. when using the clock generated by the smart car d interface on an ic ca rd, input the sck0 pin output to the ic card?s clk pin. this connection is not necessary when the internal clock is used on the ic card. use the chip?s port output as the reset signal. apart from these pins, the power and ground pin connections are usually also required. note: when the ic card is not connected and both re and te are set to 1, closed communication is possible and auto-diagnosis can be performed. lsi txd0 io clk rst rxd0 sck0 px (port) clock line data line reset line ic card connected device v cc figure 18.2 pin connection diagr am for the smart card interface 18.3.3 data format figure 18.3 shows the data format for the smart card interface. in this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. during transmission, error signals are sampled and data re-transmitted whenever an error signal is detected.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 550 of 1036 rej09b0254-0600 ds d0 d1 d2 d3 d4 d5 d6 d7 dp with no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp de with parity error transmitting station output receiving station output ds: d0 to d7: dp: de: start bit data bits parity bit error signal figure 18.3 data format for smart card interface the operating sequence is: 1. the data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. the transmitting side starts one frame of data transmission. the data fr ame starts with a start bit (ds, low level). the start bit is followed by ei ght data bits (d0 to d7) and a parity bit (dp). 3. on the smart card interface, th e data line returns to high impeda nce after this. the data line is pulled high with a pull-up resistor. 4. the receiving side checks parity . when the data is received normally with no parity errors, the receiving side then waits to receive the next data. when a parity error occurs, the receiving side outputs an error signal (d e, low level) and requests re-transfer of data. the receiving station returns the signal line to high impedance after outputting the error signal for a specified period. the signal line is pulled high with a pull-up resistor. 5. the transmitting side transmits the next frame of data unless it receives an error signal. if it does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 551 of 1036 rej09b0254-0600 18.3.4 register settings table 18.3 shows the bit map of th e registers that the smart card in terface uses. bits shown as 1 or 0 must be set to the indicated value. the settings for the other bits are described below. table 18.3 register settings fo r the smart card interface register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scsmr h'fffffe80 c/ a 0 1 o/ e 1 0 cks1 cks0 scbrr h'fffffe82 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scscr h'fffffe84 tie rie te re 0 0 cke1 cke0 sctdr h'fffffe86 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 scssr h'fffffe88 tdre rdrf orer fer/ ers per tend 0 0 scrdr h'fffffe8a rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scscmr h'fffffe8c ? ? ? ? sdir sinv ? smif note: dashes indicate unused bits. 1. setting the serial mode register (scsmr): the c/ a bit selects the set timing of the tend flag, and selects the clock output state with the comb ination of bits cke1 and cke0 in the serial control register (scscr). set the o/ e bit to 0 when the ic card uses the direct convention or to 1 when it uses the inverse convention. select the on-chip baud rate generator clock source with the cks1 and cks0 bits (see section 18.3.5, clock). 2. setting the bit rate register (scbrr): set the bit rate. see section 18.3.5, clock, to see how to calculate the set value. 3. setting the serial control register (scscr): the tie, rie, te and re bits function as they do for the ordinary sci0. see se ction 17, serial communicatio n interface (sci), for more information. the cke0 bit specifies the clock output. when no clock is output, set 0; when a clock is output, set 1. 4. setting the smart card mode register (scscmr): the sdir and sinv bits are both set to 0 for ic cards that use the direct convention and both to 1 when the inverse convention is used. the smif bit is set to 1 for the smart card interface. figure 18.4 shows sample waveforms for register settings of the two types of ic cards (direct convention and inverse convention) and their start characters. in the direct convention type, the logical 1 level is state z, the logical 0 level is state a, and communication is lsb first. the start character da ta is h'3b. the parity bit is even (from the smart card standards), and thus 1.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 552 of 1036 rej09b0254-0600 in the inverse convention type, the logical 1 level is state a, the logical 0 level is state z, and communication is msb first. the start character da ta is h'3f. the parity bit is even (from the smart card standards), and thus 0, which corresponds to state z. only data bits d7 to d0 are inverted by the sinv bit. to invert the parity bit, set the o/ e bit in scsmr to odd parity mode. this applies to both transmission and reception. ds d0 d1 d2 d3 d4 d5 d6 d7 dp a (z) z z a z z z a a z (z) state a. direct convention (sdir, sinv, and o/ e are all 0) ds d7 d6 d5 d4 d3 d2 d1 d0 dp a (z) z z a a a a a a z (z) state b. inverse convention (sdir, sinv, and o/ e are all 1) figure 18.4 waveform of start character 18.3.5 clock only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. the bit rate for the clock is set by the bit rate register (scbrr) and the cks1 and cks0 bits in the serial mode register (scsmr), and is calculated using the equation below. table 18.5 show s sample bit rates. if clock output is then selected by setting cke0 to 1, a clock with a frequency 372 times the bit rate is output from the sck0 pin. b = 10 6 1488 2 2n ? 1 (n + 1) p where: n = value set in scbrr (0 n 255) b = bit rate (bit/s) p = peripheral module operating frequency (mhz) n = 0 to 3 (table 18.4)
section 18 smart card interface rev.6.00 mar. 27, 2009 page 553 of 1036 rej09b0254-0600 table 18.4 relationship of n to cks1 and cks0 n cks1 cks0 0 0 0 1 0 1 2 1 0 3 1 1 table 18.5 examples of bit rate b (bit/s) for scbrr settings (n = 0) p (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 0 9600.0 13440.9 14400.0 174 73.1 19200.0 21505.4 24193.5 1 4800.0 6720.4 7200.0 873 6.6 9600.0 10752.7 12096.8 2 3200.0 4480.3 4800.0 582 4.4 6400.0 7168.5 8064.5 note: the bit rate is rounded to two decimal places. calculate the value to be set in the bit rate register (scbrr) from the operating frequency and the bit rate. n is an integer in the range 0 n 255, specifying a smallish error. n = 10 6 ? 1 1488 2 2n ? 1 b p table 18.6 examples of scbrr settings for bit rate b (bit/s) (n = 0) (mhz) (9600 bits/s) 7.1424 10.00 10.7136 13. 00 14.2848 16.00 18.00 n error n error n error n e rror n error n error n error 0 0.00 1 30.00 1 25.00 1 8. 99 1 0.00 1 12.01 2 15.99
section 18 smart card interface rev.6.00 mar. 27, 2009 page 554 of 1036 rej09b0254-0600 table 18.7 maximum bit rates for fre quencies (smart card interface mode) p (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 the bit rate error is found as follows: error (%) = ( 10 6 ? 1) 100 1488 2 2n ? 1 b (n + 1) p table 18.8 shows the relationship between transmit /receive clock register set values and output states on the smart card interface. table 18.8 register set values and sck0 pin register value sck0 pin setting smif c/ a cke1 cke0 output state 1 * 1 1 0 0 0 port determined by setting of port register scp1md1 and scp1md0 bits 1 0 0 1 sck0 (serial clock) output state 2 * 2 1 1 0 0 low output low output state 1 1 0 1 sck0 (serial clock) output state 3 * 2 1 1 1 0 high output high output state 1 1 1 1 sck0 (serial clock) output state notes: 1. the sck0 output state changes as soon as the cke0 bit is modified. the cke1 bit should be cleared to 0. 2. the clock duty remains constant despi te stopping and starting of the clock by modification of the cke0 bit.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 555 of 1036 rej09b0254-0600 18.3.6 data transmission and reception initialization: initialize the sci0 using the following procedure before sending or receiving data. initialization is also required fo r switching from transmit mode to receive mode or from receive mode to transmit mode. figure 18.5 shows a flow chart of the initialization process (example). 1. clear te and re in the serial control register (scscr) to 0. 2. clear error flags fer/ers, per, and orer to 0 in the serial status register (scssr). 3. set the c/ a bit, parity bit (o/ e bit), and baud rate generator select bits (cks1 and cks0 bits) in the serial mode register (scsmr). at this ti me also clear the chr and mp bits to 0 and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scscmr). when the smif bit is set to 1, the txd0 and rxd0 pins both switch from ports to sci0 pins and become high impedance. 5. set the value corresponding to the b it rate in the bit rate register (scbrr). 6. set the clock source select bits (cke1 and cke0 bits) in the serial co ntrol register (scscr). clear the tie, rie, te, re, mpie, and teie bits to 0. when the cke0 bit is set to 1, a clock is output from the sck0 pin. 7. after waiting at least 1 bit, set the tie, rie, te, and re bits in scscr. do not set the te and re bits simultaneously unless performing auto-diagnosis.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 556 of 1036 rej09b0254-0600 initialize clear te and re bits in scscr to 0 set value in scbrr clear scssr's fer/ers, per and orer flags to 0 wait set scscr's tie, rie, te, and re bits has a 1-bit interval elapsed? end (2) set scsmr's o/ e bit to parity, set cks1 and cks0 bits to the clock and set c/ a (3) set scscr's cke1 and cke0 bits to the clock and clear tie, rie, te, re, mpie, and teie bits to 0 (6) (5) (4) (1) (7) no yes set scsmr's smif, sdir, and sinv bits note: numbers refer to the preceding procedure. figure 18.5 initialization flowchart (example)
section 18 smart card interface rev.6.00 mar. 27, 2009 page 557 of 1036 rej09b0254-0600 serial data transmission: the processing procedures in the smart card mode differ from ordinary sci processing because data is retransmitted when an error signal is sampled during a data transmission. this results in the transmissi on processing flowchart shown in figure 18.6 (example). 1. initialize the smart card interface mode as described in initialization above. 2. check that the fer/ers bit in scssr is cleared to 0. 3. repeat steps 2 and 3 until the tend flag in scssr is set to 1. 4. write the transmit data into sctdr, clear th e tdre flag to 0 and start transmitting. the tend flag will be cleared to 0. 5. to transmit more data, return to step 2. 6. to end transmission, clear the te bit to 0. this processing can be interrupted. when the tie b it is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be request ed when the tend flag is set to 1 at the end of the transmission. when the rie bit is set to 1 and interrupt requests are enabled, a communication error interrupt (eri) will be requested when the ers flag is set to 1 when an error occurs in transmission. see interrupt operation below for more information.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 558 of 1036 rej09b0254-0600 start end transmission start transmission initialize write transmit data in sctdr and clear tdre flag in scssr to 0 (1) clear te bit in scscr to 0 (6) error processing (2) fer/ers = 0? tend = 1? yes yes yes yes no no all data transmitted? no tend = 1? no error processing fer/ers = 0? yes no (4) (5) (3) note: numbers refer to the preceding procedure. figure 18.6 transmission flowchart (example)
section 18 smart card interface rev.6.00 mar. 27, 2009 page 559 of 1036 rej09b0254-0600 serial data reception: the processing procedures in the sm art card mode are the same as in ordinary sci processing. the recep tion processing flowchart is show n in figure 18.7 (example). 1. initialize the smart card interface mode as descri bed above in initialization and in figure 18.5. 2. check that the orer and per fl ags in scssr are cleared to 0. if either flag is set, clear both to 0 after performing the appropri ate error processing procedures. 3. repeat steps 2 and 3 until the rdrf flag is set to 1. 4. read the receive data from scrdr. 5. to receive more data, clear the rdrf flag to 0 and return to step 2. 6. to end reception, clear the re bit to 0. this processing can be interrupted. when the rie b it is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) w ill be requested when the rdrf flag is set to 1 at the end of the reception. when an error occu rs during reception and either the orer or per flag is set to 1, a communication error interrupt (eri) will be requested. see interrupt operation below for more information. the received data will be transfer red to scrdr even when a parity error occurs during reception and per is set to 1, so this data can still be read.
section 18 smart card interface rev.6.00 mar. 27, 2009 page 560 of 1036 rej09b0254-0600 start end reception start reception initialize write receive data from scrdr and clear rdrf flag in scssr to 0 (1) clear re bit in scscr to 0 (6) error processing (2) orer = 0 or per = 0? rdrf = 1? yes yes yes no no all data received? no (4) (5) (3) note: numbers refer to the preceding procedure. figure 18.7 reception flowchart (example)
section 18 smart card interface rev.6.00 mar. 27, 2009 page 561 of 1036 rej09b0254-0600 switching modes: when switching from recei ve mode to transmit mode, check that the receive operation is completed before starting initializati on and setting re to 0 and te to 1. the rdrf, per, and orer flags can be used to check if reception is completed. when switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting te to 0 and re to 1. the tend flag can be used to check if transmission is completed. interrupt operation: in the smart card interface mode, ther e are three types of interrupts: transmit-data-empty (txi), comm unication error (eri) and receive-d ata-full (rxi). in this mode, the transmit-end interrupt (tei) cannot be requested. set the tend flag in scssr to 1 to request a tx i interrupt. set the rdrf flag in scssr to 1 to request an rxi interrupt. set the orer, per, or fer/ers flag in scssr to 1 to request an eri interrupt (table 18.9). table 18.9 smart card mode opera ting state and interrupt sources mode state flag mask bit interrupt source transmit mode normal tend tie txi error fer/ers rie eri receive mode normal rdrf rie rxi error per, orer rie eri 18.4 usage notes when the sci is used as a smart card interface, be sure that all criteria in sections 18.4.1, receive data timing and receive margin in asynchron ous mode and 18.4.2, retransmission (receive and transmit modes) are applied. 18.4.1 receive data timing and recei ve margin in asynchronous mode in asynchronous mode, the sci runs on a basic cl ock with a frequency of 372 times the transfer rate. during reception, the sci0 samples the falling of the start bit using the base clock to achieve internal synchronization. receive data is latched internally on the rising edge of the 186th basic clock cycle (figure 18.8).
section 18 smart card interface rev.6.00 mar. 27, 2009 page 562 of 1036 rej09b0254-0600 0 185 371 0 185 371 0 base clock receive data (rxd0) synchro- nization sampling timing data sampling timing 186 clock cycles 372 clock cycles start bit d0 d1 figure 18.8 receive data sampling timing in smart card mode the receive margin is found from the following equation: for smart card mode: m = (0.5 ? ) ? 1 2n d ? 0.5 n (l ? 0.5)f ? (1 + f) 100% where: m = receive margin (%) n = ratio of bit rate to clock (n = 372) d = clock duty (d = 0 to 1.0) l = frame length (l = 10) f = absolute value of clock frequency deviation using this equation, the receive margin when f = 0 and d = 0.5 is as follows: m = (0.5 ? 1/2 372) 100 % = 49.866 %
section 18 smart card interface rev.6.00 mar. 27, 2009 page 563 of 1036 rej09b0254-0600 18.4.2 retransmission (recei ve and transmit modes) retransmission by the sci in receive mode: figure 18.9 shows the retransmission operation in the sci receive mode. 1. when the received parity bit is checked and an error is found, the per bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an eri interrupt is requested. be sure to clear the per bit before the next parity bit is sampled. 2. the rdrf bit in scssr is not set in the frame that caused the error. 3. when the received parity bit is checked and no error is found, the per b it in scssr is not set. 4. when the received parity bit is checked and no error is found, reception is considered to have been completed normally and the rdrf bit in scssr is automatically set to 1. if the rie bit in scscr is enabled at this time, an rxi interrupt is requested. 5. when a normal frame is received, the pin main tains a three-state state when it transmits the error signal. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame rdrf per 2 1 4 5 3 retransmitted frame transfer frame n + 1 figure 18.9 retransmission in sci receive mode
section 18 smart card interface rev.6.00 mar. 27, 2009 page 564 of 1036 rej09b0254-0600 retransmission by the sci in transmit mode: figure 18.10 shows the retransmission operation in the sci transmit mode. 1. after transmission of one frame is completed, the fer/ers bit in scssr is set to 1 when a error signal is returned from the receiving side. if the rie b it in scscr is enabled at this time, an eri interrupt is requested. be sure to clea r the fer/ers bit before the next parity bit is sampled. 2. the tend bit in scssr is not set in the frame that received the error signal that indicated the error. 3. the fer/ers bit in scssr is not set when no error signal is returned from the receiving side. 4. when no error signal is returned from the receiving side, the tend bit in scssr is set to 1 when the transmission of the frame that includes the retransmission is considered completed. if the tie bit in scscr is enabled at this time, a txi interrupt will be requested. d0 ds d2 d1 d4 d3 d6 d5 dp de d7 d0 ds d2 d1 d4 d3 d6 d5 dp (de) d7 d0 ds d2 d1 d4 d3 nth transfer frame tend fer/ers transfer from sctdr to sctsr transfer from sctdr to sctsr transfer from sctdr to sctsr 1 2 4 3 retransmitted frame transfer frame n + 1 tdre figure 18.10 retransmission in sci transmit mode
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 565 of 1036 rej09b0254-0600 section 19 serial communi cation interface with fifo (scif) 19.1 overview this lsi has one-channel serial communication interface with fifo (scif) that supports asynchronous serial communication. it also has 16-stage fifo registers for both transfer and receive that enables this lsi efficien t high-speed conti nuous communication. 19.1.1 features ? asynchronous serial communication: ? serial data communications are performed by start-stop in character units. the sci can communicate with a universal as ynchronous receiver /transmitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous serial system. th ere are eight selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? receive error detection: pa rity and framing errors ? break detection: break is detected when the receive data next the generated framing error is the space 0 level and has the framing error. it is also detected by reading the rxd2 level directly from the port sc data regist er (scpdr) when a fr aming error occurs ? full duplex communication: the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use 16-stage fifo buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates ? internal transmit/receive clock source ? four types of interrupts: transmit-fifo-dat a-empty, break, receive-fifo-data-full, and receive-error interrupts are requested indepe ndently. the direct memory access controller (dmac) can be activated to execute a data tran sfer by a transmit-fifo-data-empty or receive- fifo-data-full interrupt. ? when the scif is not in use, it can be stopped by halting the clock supplied to it, saving power. ? on-chip modem control functions ( rts2 and cts2 )
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 566 of 1036 rej09b0254-0600 ? the quantity of data in the tr ansmit and receive fifo registers and the number of receive errors of the receive data in the r eceive fifo register can be known. ? the time-out error (dr) can be detected in receiving. 19.1.2 block diagram figure 19.1 shows a block diagram of the scif. rxd2 txd2 rts2 cts2 scif scbrr2 scssr2 scscr2 scftdr2 sctsr2 scfrdr2 (16stages) (16stages) scrsr2 scsmr2 scfdr2 scfcr2 scpcr2 scfdr2 parity generation parity check clock module data bus internal data bus p p /4 p /16 p /64 txi eri bri bri bus interface baud rate generator transmit/ receive control scrsr2: scfrdr2: sctsr2: scftdr2: scsmr2: scscr2: receive shift register 2 receive fifo data register 2 transmit shift register 2 transmit fifo data register 2 serial mode register 2 serial control register 2 scssr2: scbrr2: scfcr2: scfdr2: scpdr2: scpcr2: serial status register 2 bit rate register 2 fifo control register 2 fifo data count set register 2 port sc data register 2 port sc control register 2 legend: figure 19.1 scif block diagram
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 567 of 1036 rej09b0254-0600 figures 19.2 and 19.3 show scif i/o ports. bits 15, 14, 9, 8 of scpcr and bits 7 and 4 of scpdr control an input/output and data of the scif pins. see section 26.3.13, sc port control register (scpcr) for more details. internal data bus output enable scif serial transmission output q r scp4dt1 pdrw reset scpt[4]/txd2 c d pcrw: pdrw: scpcr write scpdr write r scp4md0 pcrw reset c q d r scp4md1 pcrw reset c q d legend: figure 19.2 scpt[4]/txd2 pin
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 568 of 1036 rej09b0254-0600 scif serial receive data pdrr * scpt[4]/rxd2 pdrr: scpdr read note: * when reading the rxd2 pin, set the re bit in scscr2 to 1. legend: internal data bus figure 19.3 scpt[4]/rxd2 pin 19.1.3 pin configuration the scif has the serial pins summarized in table 19.1. table 19.1 scif pins pin name abbreviation i/o function receive data pin rxd2 input receive data input transmit data pin txd2 ou tput transmit data output request to send pin rts2 output request to send clear to send pin cts2 input clear to send
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 569 of 1036 rej09b0254-0600 19.1.4 register configuration table 19.2 summarizes the scif internal registers. these registers specify the data format and bit rate, and control the transmitter and receiver sections. table 19.2 registers register name abbreviation r/w initial value address access size serial mode register 2 scsmr2 r/w h'00 h'04000150 (h'a4000150) * 2 8 bits bit rate register 2 scbrr2 r/w h'ff h'04000152 (h'a4000152) * 2 8 bits serial control register 2 scscr2 r/w h'00 h'04000154 (h'a4000154) * 2 8 bits transmit fifo data register 2 scftdr2 w ? h'04000156 (h'a4000156) * 2 8 bits serial status register 2 scssr2 r/(w) * 1 h'0060 h'04000158 (h'a4000158) * 2 16 bits receive fifo data register 2 scfrdr2 r undefined h'0400015a (h'a400015a) * 2 8 bits fifo control register 2 scfcr2 r/w h'00 h'0400015c (h'a400015c) * 2 8 bits fifo data count set register 2 scfdr2 r h'0000 h'0400015e (h'a400015e) * 2 16 bits notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to clear the flag. 2. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 570 of 1036 rej09b0254-0600 19.2 register descriptions 19.2.1 receive shift register 2 (scrsr2) the receive shift register 2 (scrsr2) receives serial data. data input at the rxd2 pin is loaded into the scrsr2 in the order r eceived, lsb (bit 0) first, conver ting the data to parallel form. when one byte has been received, it is automati cally transferred to the scfrdr2, which is a receive fifo data register 2. the cpu ca nnot read or write the scrsr2 directly. bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? 19.2.2 receive fifo data register 2 (scfrdr2) the 16-byte receive fifo data register 2 (scf rdr2) stores serial receive data. the scif completes the reception of one byte of serial data by moving th e received data from the receive shift register 2 (scrsr2) into the scfrdr2 for st orage. continuous receive is enabled until 16 bytes are stored. the cpu can read but not write the scfrdr2. wh en data is read without received data in the scfrdr2, the value is undefined. when the r eceived data in this register becomes full, the subsequent serial data is lost. bit: 7 6 5 4 3 2 1 0 r/w: r r r r r r r r
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 571 of 1036 rej09b0254-0600 19.2.3 transmit shift register 2 (sctsr2) the transmit shift register 2 (sctsr 2) transmits serial data. the sci loads transmit data from the transmit fifo data register 2 (scftdr2) into the sctsr2, then transmits the data serially from the txd2 pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from the scftdr2 into the sc tsr2 and starts transmitting again. the cpu cannot read or write the sctsr2 directly. bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? 19.2.4 transmit fifo data register 2 (scftdr2) the transmit fifo data register 2 (scftdr2) is a 16-byte 8-bit-leng th fifo register that stores data for serial transmission. when the scif detects that the transmit shift register (sctsr2) is empty, it moves transmit data written in the scftdr2 into the sctsr2 and starts serial transmission. continuous serial transmission is performed until the transmit data in the scftdr2 becomes empty. the cpu can alwa ys write to the scftdr2. when the transmit data in the scftdr2 is full (16 bytes), next data cannot be written. if attempted to write, the data is ignored. bit: 7 6 5 4 3 2 1 0 r/w: w w w w w w w w
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 572 of 1036 rej09b0254-0600 19.2.5 serial mode register 2 (scsmr2) the serial mode register 2 (scsmr2) is an ei ght-bit register that speci fies the scif serial communication format and selects the cloc k source for the baud rate generator. the cpu can always read and write the scsmr2. th e scsmr2 is initialized to h'00 by a reset or in standby and module standby modes. bit: 7 6 5 4 3 2 1 0 ? chr pe o/ e stop ? cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r r/w r/w bit 7?reserved: this bit always read 0. the write value should always be 0. bit 6?character length (chr): selects seven-bit or eight-bit data in the asynchronous mode. bit 6: chr description 0 eight-bit data. (initial value) 1 seven-bit data. * note: * when seven-bit data is selected, the msb (bit 7) of the transmit fifo data register 2 is not transmitted. bit 5?parity enable (pe): selects whether or not to add a parity bit to transmit data and to check the parity of receive data. bit 5: pe description 0 parity bit not added or checked. (initial value) 1 parity bit added and checked. when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. bit 4?parity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only when the parity enable bit (pe) is set to 1 to enable parity addition and check. the o/ e setting is ignored when parity addition and check is disabled.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 573 of 1036 rej09b0254-0600 bit 4: o/ e description 0 even parity. (initial value) if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted characte r and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 odd parity. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted characte r and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. bit 3?stop bit length (stop): selects one or two bits as the stop bit length. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the se cond stop bit is 0, it is treated as the start bit of the next incoming character. bit 3: stop description 0 one stop bit. (initial value) in transmitting, a single bit of 1 is added at the end of each transmitted character. 1 two stop bits. in transmitting, two bits of 1 are added at the end of each transmitted character. bit 2?reserved: this bit is always read as 0. the write value should always be 0. bits 1 and 0?clock select 1 and 0 (cks1 and cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available. p , p /4, p /16 and p /64. for further information on the clock source, bit rate register 2 settings, and baud rate, see section 19.2.8, bit rate register 2 (scbrr2). bit 1: cks1 bit 0: cks0 description 0 0 p clock (initial value) 1 p /4 clock 1 0 p /16 clock 1 p /64 clock note: p : peripheral clock
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 574 of 1036 rej09b0254-0600 19.2.6 serial control register 2 (scscr2) the serial control register 2 (scscr2) operates the sci transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. th e cpu can always read and write the scscr2. the scscr2 is initialized to h'00 by a reset or in standby and module standby modes. bit: 7 6 5 4 3 2 1 0 tie rie te re ? ? cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w bit 7?transmit interrupt enable (tie): enables or disables the transmit-fifo-data-empty interrupt (txi) requested when serial transmit data is transferred from tran smit fifo data register 2 (scftdr2) to transmit shift register 2 (sctsr 2), when the quantity of data in transmit fifo register 2 becomes less than the specified numbe r of transmission triggers, and when the tdfe flag in serial status register 2 (scssr2) is set to1. bit 7: tie description 0 transmit-fifo-data-empty interrupt request (txi) is disabled. * (initial value) 1 transmit-fifo-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by writing the greater quantity of transmit data than the specified number of tr ansmission triggers to scftdr2 and by clearing tdfe to 0 after reading 1 from tdfe, or can be cleared by clearing tie to 0. bit 6?receive interrupt enable (rie): enables or disables the receive-data-full (rxi) and receive-error (eri) interrupts requested when serial receive data is transferred from receive shift register 2 (scrsr2) to receive fifo data regist er 2 (scfrdr2), when th e quantity of data in receive fifo register 2 becomes mo re than the specified number of receive triggers, and when the rdrf flag in scssr2 is set to1. bit 6: rie description 0 receive-data-full interrupt (rxi), receiv e-error interrupt (eri), and receive break interrupt (bri) requests are disabled. * (initial value) 1 receive-data-full interrupt (rxi) and re ceive-error interrupt (eri) requests are enabled. note: * rxi and eri interrupt requests can be cleared by reading the dr, er, or rdf flag after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. at rdf, read 1 from the rdf flag and clear it to 0, after reading the received data from scfrdr2 until the quantity of received data becomes less than the specified number of the receive triggers.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 575 of 1036 rej09b0254-0600 bit 5?transmit enable (te): enables or disables the scif serial transmitter. bit 5: te description 0 transmitter disabled. (initial value) 1 transmitter enabled. * note: * serial transmission starts after writing of transmit data into the scftdr2. select the transmit format in the scsmr2 and scfcr2 and reset the scftdr2 before setting te to 1. bit 4?receive enable (re): enables or disables the scif serial receiver. bit 4: re description 0 receiver disabled. * 1 (initial value) 1 receiver enabled. * 2 notes: 1. clearing re to 0 does not affect t he receive flags (dr, er, brk, fer, and per). these flags retain their previous values. 2. serial reception starts when a start bit is detected. select the receive format in the scsmr2 before setting re to 1. bits 3 and 2?reserved: these bits are always read as 0. the write value should always be 0. bits 1 and 0?clock enable 1 and 0 (cke1 and cke0): these bits should always be set to 00.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 576 of 1036 rej09b0254-0600 19.2.7 serial status register 2 (scssr2) serial status register 2 (scssr2) is a 16-bit register. the upper 8 bits indicate the number of receive errors in the data of receive fifo data register 2, and the lower 8 bits indicate scif operating state. the cpu can always read and write the scssr2, but cannot write 1 in the status flags (er, tend, tdfe, brk, rdf, and dr). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 3 (fer) and 2 (p er) are read-only bits that cannot be written. the scssr2 is initialized to h'0060 by a reset or in standby and module standby modes. lower 8 bits: 7 6 5 4 3 2 1 0 er tend tdfe brk fer per rdf dr initial value: 0 1 1 0 0 0 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r r r/(w) * r/(w) * note: * the only value that can be wri tten is 0 to clear the flag. bit 7?receive error (er): indicates that a parity error ha s occurred when received data includes a framing error or a parity. bit 7: er description 0 receive is in progress, or receive is normally completed. * 1 (initial value) er is cleared to 0 when the chip is reset or enters standby mode, or when 0 is written after 1 is read from er. 1 a framing error or a parity error has occurred. er is set to 1 when the stop bit is 0 afte r checking whether or not the last stop bit of the received data is 1 at the end of one-data receive * 2 , or when the total number of 1's in the received data and in the parity bit does not match the even/odd parity specification specified by the o/ e bit of the scsmr2. notes: 1. clearing the re bit to 0 in scscr2 does not affect the er bit, which retains its previous value. even if a receive error occurs, the received data is transferred to scfrdr2 and the receive operation is conti nued. whether or not the data read from scfrdr2 includes a receive error can be detected by the fer and per bits of scssr2. 2. in the stop mode, only the first stop bit is checked; the second stop bit is not checked.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 577 of 1036 rej09b0254-0600 bit 6?transmit end (tend): indicates that when the last bit of a serial character was transmitted, the scftdr2 did not contain valid data, so transmission has ended. bit 6: tend description 0 transmission is in progress. tend is cleared to 0 when da ta is written in scftdr2. 1 end of transmission. (initial value) tend is set to 1 when the chip is reset or enters standby mode, te is cleared to 0 in the serial control register (scscr2), or when scftdr2 does not contain received data when the last bit of a one-byte serial character is transmitted. bit 5?transmit fifo data empty (tdfe): indicates that data is transferred from transmit fifo data register 2 (scftdr2) to transmit sh ift register (sctsr), the quantity of data in scftdr2 becomes less than the number of transmission triggers specified by the ttrg1 and ttrg0 bits in fifo control register 2 (scfcr2), and writing the transmit data to scftdr2 is enabled. bit 5: tdfe description 0 the quantity of transmit data written to scftdr2 is greater than the specified number of transmission triggers. (initial value) tdfe is cleared to 0 when data exceeding the specified transmission trigger number is written to scftdr2, and software reads 1 from tdfe and then writes 0 to tdfe. 1 the quantity of transmit data in scftdr2 is less than the specified number of transmission triggers. * tdfe is set to 1 at reset or at standby mode, or when the quantity of transmission data in scftdr2 becomes less than the specified number of transmission triggers as a result of transmission. note: * since scftdr2 is a 16-byte fifo register , the maximum quantity of data which can be written when tdfe is 1 is ?16 minus the spec ified number of transmission triggers.? if an attempt is made to write additional data, the data is ignored. the quantity of data in scftdr2 is indicated by the upper 8 bits of scftdr2.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 578 of 1036 rej09b0254-0600 bit 4?break detection (brk): indicates that a break signal is detected in received data. bit 4: brk description 0 no break signal is being received. (initial value) brk is cleared to 0 when the chip is reset or enters standby mode, or software reads brk after it has been set to 1, then writes 0 in brk. 1 the break signal is received. * brk is set to 1 when data including a framing error is received and a framing error occurs with space 0 in the subsequent received data. note: * when a break is detected, transfer of the re ceived data (h'00) to scfrdr2 stops after detection. when the break ends and the rece ive signal becomes mark 1, the transfer of the received data resumes. the received data of a frame in which a break signal is detected is transferred to scfrdr2. after th is, however, no received data is transferred until a break ends with the received signal be ing mark 1 and the next data is received. bit 3?framing error (fer): indicates a framing error in the data read from the receive fifo data register 2 (scfrdr2). bit 3: fer description 0 no receive framing error occurred in t he data read from scfrdr2. (initial value) fer is cleared to 0 when the chip is power-on reset or enters standby mode, or when no framing error is present in the data read from scfrdr2. 1 a receive framing error occurred in the data read from scfrdr2. fer is set to 1 when a framing error is present in the data read from scfrdr2. bit 2?parity error (per): indicates a parity error in the data read from the receive fifo data register 2 (scfrdr2). bit 2: per description 0 no receive parity error occurred in the data read from scfrdr2. (initial value) per is cleared to 0 when the chip is power-on reset or enters standby mode, or when no parity error is present in the data read from scfrdr2. 1 a receive parity error occurred in the data read from scfrdr2. per is set to 1 when a parity error is present in the data read from scfrdr2.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 579 of 1036 rej09b0254-0600 bit 1?receive fifo data full (rdf): indicates that received data is transferred to the receive fifo data register 2 (scfrdr2), the quantity of data in scfrdr2 becomes more than the number of receive triggers specified by the rtrg1 and rtrg0 bits in fifo control register 2 (scfcr2). bit 1: rdf description 0 the quantity of transmit data written to scfrdr2 is less than the specified number of receive triggers. (initial value) rdf is cleared to 0 at power-on reset or in standby mode, or when scfrdr2 is read until the quantity of receive data in scfrdr2 is less than the specified receive trigger number, and software reads 1 from rdf and then writes 0 to rdf. 1 the quantity of receive data in scfrdr2 is more than the specified number of receive triggers. rdf is set to 1 when the quantity of receive data which is greater than the specified number of receive triggers is stored in scfrdr2. * note: * since scftdr2 is a 16-byte fifo register , the maximum quantity of data which can be read when rdf is 1 is the specified number of receive triggers. if attempted to read after all data in the scfrdr2 have been read, the data is undefined. the quantity of receive data in scfrdr2 is indicated by the lower 8 bits of scftdr2. bit 0?receive data ready (dr): indicates that the receive fi fo data register 2 (scfrdr2) stores the data which is less than the specified num ber of receive triggers, and that next data is not yet received after 15 etu has elap sed from the last stop bit. bit 0: dr description 0 receive is in progress, or no rece ived data remains in scfrdr2 after completing receive normally. (initial value) dr is cleared to 0 when the chip is power-on reset or enters standby mode, or software reads dr after it has been set to 1, then writes 0 in dr. 1 next receive data is not received. dr is set to 1 when scfrdr2 stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit. * note: * this is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (e tu: element time unit)
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 580 of 1036 rej09b0254-0600 upper 8 bits: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 15 to 12?number of parity errors 3 to 0 (per3 to per0): indicates the quantity of data including a parity error in the recei ved data stored in the receive fifo data register 2 (scfrdr2). the value indicated by the bits 15 to 12 represen ts the number of parity errors in scfrdr2. bits 11 to 8?number of framing errors 3 to 0 (fer3 to fer0): indicates the quantity of data including a framing error in the recei ved data stored in scfrdr2. the value indicated by bits 11 to 8 represents the number of framing errors in scfrdr2. 19.2.8 bit rate register 2 (scbrr2) the bit rate register 2 (scbrr2) is an eight-bit regi ster that, together with the baud rate generator clock source selected by the cks1 and cks0 b its in the serial mode register 2 (scsmr2), determines the serial tr ansmit/receive bit rate. the cpu can always read and write the scbrr2. the scbrr2 is initialized to h'ff by a reset or in module standby or standby mode. each channel has independent baud rate generator control, so different values can be set in two channels. bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the scbrr2 setting is calculated as follows: asynchronous mode: n = p 64 2 2n?1 b 10 6 ? 1 b: bit rate (bit/s) n: scbrr2 setting for baud rate generator (0 n 255) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 19.3.)
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 581 of 1036 rej09b0254-0600 table 19.3 scsmr2 settings scsmr2 settings n clock source cks1 cks0 0 p 0 0 1 p /4 0 1 2 p /16 1 0 3 p /64 1 1 note: find the bit rate erro r by the following formula: p 10 6 ? 1 100 (n+1) 64 2 2n ? 1 b error (%) = table 19.4 lists examples of scbrr2 settings. table 19.4 bit rates and scbrr2 settings p (mhz) 2 2.097152 2.4576 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 150 1 103 0.16 1 108 0.21 1 127 0.00 300 0 207 0.16 0 217 0.21 0 255 0.00 600 0 103 0.16 0 108 0.21 0 127 0.00 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 2400 0 25 0.16 0 26 1.14 0 31 0.00 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 19200 0 2 8.51 0 2 13.78 0 3 0.00 31250 0 1 0.00 0 1 4.86 0 1 22.88 38400 0 1 ?18.62 0 0 ?14.67 0 1 0.00
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 582 of 1036 rej09b0254-0600 p (mhz) 3 3.6864 4 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 212 0.03 2 64 0.70 2 70 0.03 150 1 155 0.16 1 191 0.00 1 207 0.16 300 1 77 0.16 1 95 0.00 1 103 0.16 600 0 155 0.16 0 191 0.00 0 207 0.16 1200 0 77 0.16 0 95 0.00 0 103 0.16 2400 0 38 0.16 0 47 0.00 0 51 0.16 4800 0 19 ?2.34 0 23 0.00 0 25 0.16 9600 0 9 ?2.34 0 11 0.00 0 12 0.16 19200 0 4 ?2.34 0 5 0.00 0 6 ?6.99 31250 0 2 0.00 0 3 ?7.84 0 3 0.00 38400 ? ? ? 0 2 0.00 0 2 8.51 p (mhz) 4.9152 5 6 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 86 0.31 2 88 ?0.25 2 106 ?0.44 150 1 255 0.00 2 64 0.16 2 77 0.16 300 1 127 0.00 1 129 0.16 1 155 0.16 600 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 31 0.00 0 32 ?1.36 0 38 0.16 9600 0 15 0.00 0 15 1.73 0 19 ?2.34 19200 0 7 0.00 0 7 1.73 0 9 ?2.34 31250 0 4 ?1.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 ?2.34
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 583 of 1036 rej09b0254-0600 p (mhz) 6.144 7.3728 8 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 79 0.00 2 95 0.00 2 103 0.16 300 1 159 0.00 1 191 0.00 1 207 0.16 600 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 0.00 0 5 0.00 0 6 ?6.99 p (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 174 ?0.26 2 177 ?0.25 1 212 0.03 2 217 0.08 150 1 127 0.00 2 129 0.16 1 155 0.16 2 159 0.00 300 0 255 0.00 2 64 0.16 1 77 0.16 2 79 0.00 600 0 127 0.00 1 129 0.16 0 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 0 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 38 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 19 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 9 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 4 0.16 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 2 0.00 0 11 2.40 38400 0 1 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 584 of 1036 rej09b0254-0600 p (mhz) 14.7456 16 19.6608 20 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 ?0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 2 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 1 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 0 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 31250 0 14 ?1.70 0 15 0.00 0 19 ?1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 115200 0 3 0.00 0 3 8.51 0 4 6.67 0 4 8.51 500000 0 0 ?7.84 0 0 0.00 0 0 22.9 0 0 25.0 p (mhz) 24 24.576 28.7 30 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 106 ?0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 155 0.16 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 155 0.16 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 155 0.16 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 38 0.16 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 23 0.00 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 ?2.34 0 19 0.00 0 22 1.55 0 23 1.73 115200 0 6 ?6.99 0 6 ?4.76 0 7 ?2.68 0 7 1.73 500000 0 1 ?25.0 0 1 ?23.2 0 1 ?10.3 0 1 ?6.25
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 585 of 1036 rej09b0254-0600 table 19.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. table 19.5 maximum bit rates for variou s frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 586 of 1036 rej09b0254-0600 19.2.9 fifo control register 2 (scfcr2) bit: 7 6 5 4 3 2 1 0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the fifo control register 2 (scf cr2) resets the number of data in the transmit and receive fifo register 2, sets the number of trigger data, and c ontains the permit bit for the loop back test. the scfcr2 is always read and written by the cpu. it is initialized to h'00 by the reset, the module standby function, or in the standby mode. bits 7 and 6?trigger of the number of receive fifo data (rtrg1 and rtrg0): set the number of receive data which sets the receive data full (rdf) flag in the se rial status register 2 (scssr2). these bits set the rdf flag when the number of receive data stored in the receive fifo register 2 (scfrdr2) is in creased more than the number of setting triggers listed below. bit 7: rtrg1 bit 6: rtrg0 number of received triggers 0 0 1 (initial value) 1 4 1 0 8 1 14 bits 5 and 4?trigger of the number of transmit fifo data (ttrg1 and ttrg0): set the number of remaining transmit data which sets the transmit fifo data regist er empty (tdfe) flag in the serial status register 2 (scssr2). thes e bits set the tdfe flag when the number of transmit data in the transmit fifo data register 2 (scftdr2) is decreased less than the number of setting triggers listed below. bit 5: ttrg1 bit 4: ttrg0 number of transmitted triggers 0 0 8 (8) * 1 4 (12) 1 0 2 (14) 1 1 (15) note: * initial value. values in brackets mean t he number of empty scftdr2 when a flag occurs.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 587 of 1036 rej09b0254-0600 bit 3?modem control enable (mce): enables the modem control signals cts2 and rts2 . bit 3: mce description 0 disables the modem signal * (initial value) 1 enables the modem signal note: * the cts2 is fixed to active 0 regardless of the input value, and the rts2 is also fixed to 0. bit 2?transmit fifo data register reset (tfrst): disables the transmit data in the transmit fifo data register 2 and resets the data to the empty state. bit 2: tfrst description 0 disables reset operation * (initial value) 1 enables reset operation note: * reset is operated in resets or the standby mode. bit 1?receive fifo data register reset (rfrst): disables the receive data in the receive fifo data register 2 and resets the data to the empty state. bit 1: rfrst description 0 disables reset operation * (initial value) 1 enables reset operation note: * reset is operated in resets or the standby mode. bit 0?loop back test (loop): internally connects the transm it output pin (txd2) and receive input pin (rxd2) and enables the loop back test. bit 0: loop description 0 disables the loop back test (initial value) 1 enables the loop back test
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 588 of 1036 rej09b0254-0600 19.2.10 fifo data count set register 2 (scfdr2) the scfdr2 is a 16-bit register which indicates the number of data stored in the transmit fifo data register 2 (scftdr2) and the receive fifo data register 2 (scfrdr2). it indicates the number of transmit data in the scftdr2 with the upper eight bits, and the number of receive data in the scfrdr2 with the lower eight bits. the scfdr2 is always read from the cpu. upper 8 bits: 15 14 13 12 11 10 9 8 ? ? ? t4 t3 t2 t1 t0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the scfdr2 indicates the number of non-transmitted data stored in the scftdr2. the h'00 means no transmit data, and the h'10 means that the full of transmit data are stored in the scftdr2. lower 8 bits: 7 6 5 4 3 2 1 0 ? ? ? r4 r3 r2 r1 r0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the scfdr2 indicates the number of receive data stored in the scfrdr2. the h'00 means no receive data, and the h'10 means that the full of receive data are stored in the scfrdr2.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 589 of 1036 rej09b0254-0600 19.3 operation 19.3.1 overview for serial communication, the scif has an asynchronous mode in which characters are synchronized individually. refer to section 17.3.2, operation in asynchronous mode. the scif has the 16-byte fifo buffer for both transmit and receive, reduces an overhead of the cpu, and enables continuous high-speed communication. moreover, it has the rts2 and cts2 signals as the modem control signals. the tr ansmission format is selected in the serial mode register 2 (scsmr2), as listed in table 19.6. the clock source of scif is determined by the combination of cke1 and cke0 bits in the serial control register 2 (scscr2) as shown in table 19.7. ? data length is selectable from seven or eight bits. ? parity and multiprocessor bits are selectable. so is the stop bit length (one or two bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing erro rs (fer), parity errors (per), receive fifo data full, receive data ready, and breaks. ? in transmitting, it is possible to detect transmit fifo data empty. ? the number of stored data fo r both the transmit and receive fifo registers is displayed. ? scif clock source ? the scif operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency 16 times the bit rate. table 19.6 scsmr2 settings and scif transmit/receive scsmr2 settings scif transmit/receive mode bit 6 chr bit 5 pe bit 3 stop data length parity bit stop bit length 0 1 bit 0 1 not set 2 bits 0 1 bit 0 1 1 8-bit set 2 bits 0 1 bit 0 1 not set 2 bits 0 1 bit asynchronous 1 1 1 7-bit set 2 bits
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 590 of 1036 rej09b0254-0600 table 19.7 settings for scsm r2 and scscr2 and selectio n of clock source of scif scscr2 settings scif transmit/receive clock mode bit 1 cke1 bit 0 cke0 clock source functions of sck2 pins 0 scif does not use sck2 pins. 0 1 internal inhibited 0 asynchronous 1 1 external inhibited 19.3.2 serial operation transmit/receive formats: table 19.8 lists eight communicati on formats that can be selected. the format is selected by settings in the serial mode register (scsmr2). table 19.8 serial transmit/receive formats scsmr2 bits serial transmit/receive format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop notes: start: start bit stop: stop bit p: parity bit
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 591 of 1036 rej09b0254-0600 transmitting and receiving data (scif initialization): before transmitting or receiving, clear the te and re bits to 0 in the serial control re gister 2 (scscr2), then initialize the scif as follows. when changing the communication format, always cl ear the te and re bits to 0 before following the procedure given below. clearing te to 0 initia lizes the transmit shift register 2 (sctsr2). clearing te and re to 0, however, does not initialize the serial status register 2 (scssr2), transmit fifo data register 2 (scftdr2), or r eceive fifo data register 2 (scfrdr2), which retain their previous contents. clear te to 0 after all transmit da ta are transmitted and the tend flag in the scssr2 is set. the transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared to 0 in transmitting. set the tfrst bit in the scfcr2 to 1 and reset the scftdr2 before te is set again to start transmission. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. scif operation becomes unreliable if the clock is stopped.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 592 of 1036 rej09b0254-0600 figure 19.4 is a sample flowchart for initializing the scif. the procedure for initializing the scif is: initialization (1) set the clock selection in scscr2. be sure to clear bits rie tie, te, and re to 0. when clock output is selected, it is output immediately after scscr2 settings are made. (2) set the data transfer format in scsmr2. (3) write a value corresponding to the bit rate into the bit rate register 2 (scbrr2). (not necessary if an external clock is used.) (4) wait at least one bit interval, then set the te bit or re bit in scsr2 to 1. also set the rie and tie bits. setting the te and re bits enables the txd2 and rxd2 pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. clear te and re bits in scscr2 to 0 set tfrst and rfrst bits in scfcr2 to 1 (1) (2) (3) (4) 1-bit interval elapsed? set rtrg1-0, ttrg1-0, and mce in scfcr2 clear tfrst and rfrst bits to 0 set te and re bits in scscr2 to 1,and set rie, and tie bits set data transfer format in scsmr2 yes no set value in scbrr2 set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) end wait figure 19.4 sample scif initialization flowchart
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 593 of 1036 rej09b0254-0600 ? serial data transmission figure 19.5 shows a sample serial transmission fl owchart. after scif transmission is enabled, use the following procedure to perform serial data transmission. start transmission read tdfe bit in scssr2 tend= 1? read tend bit in scssr2 clear te bit in scscr2 to 0 set scpdr2 and scpcr2 yes no tdfe= 1? no all data transmitted? no yes yes break output? yes no write transmit data (16 - transmit trigger set number) to scftdr2, read 1 from tdfe bit and tend flag in scssr2, then clear to 0 end of transmission (1) scif status check and transmit data write: read serial status register 2 (scssr2) and check that the tdfe flag is set to 1, then write transmit data to the transmit fifo data register 2 (scftdr2), read 1 from the tdfe and tend flags, then clear these flags to 0. the number of transmit data bytes that can be written is 16 - (transmit trigger set number). (2) serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr2, and then clear the tdfe flag to 0. (3) break output at the end of serial transmission: to output a break in serial transmission, set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register 2 (scscr2). for information on scpdr2 and scpcr2, see section 17.2.8. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of the fifo data count set register 2 (scfdr2). (1) (2) (3) figure 19.5 sample serial transmission flowchart
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 594 of 1036 rej09b0254-0600 in serial transmission, the scif operates as described below. 1. when data is written into the transmit fifo da ta register 2 (scftdr2), the scif transfers the data from scftdr2 to the transmit shift regi ster 2 (sctsr2) and starts transmitting. confirm that the tdfe flag in the serial status register 2 (scssr2) is set to 1 before writing transmit data to scftdr2. the number of da ta bytes that can be written is (16 ? transmit trigger setting). 2. when data is transferred from scftdr2 to sctsr2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr2. when the number of transmit data bytes in scftdr2 falls below the transmit trigger number set in the fifo control register 2 (scfcr2), the tdfe flag is set. if the tie bit in the serial control register (scsr2) is set to 1 at this time, a tr ansmit-fifo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd2 pin in the following order. a. start bit: one-bit 0 is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one- or two-bit 1s (stop bits) are output. e. mark state: 1 is output continuously until th e start bit that starts the next transmission is sent. 3. the scif checks the scftdr2 transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr2 to sctsr2, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scssr2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. figure 19.6 shows an example of the operation for transmission.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 595 of 1036 rej09b0254-0600 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle state (mark state) txi interrupt request data written to scftdr2 and tdfe flag read as 1 then cleared to 0 by txi interrupt handler one frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 txi interrupt request figure 19.6 example of transmit operation (example with 8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and rest arted in accordance with the cts2 input value. when cts2 is set to 1, if transmission is in progress, the line goes to the mark state after transmi ssion of one frame. when cts2 is set to 0, the next transmit data is output starting from the start bit. figure 19.7 shows an example of the operation when modem control is used. 0 0/1 0 cts2 parity bit serial data txd2 start bit stop bit start bit d 0 d 1 d 7 d 0 d 1 d 7 0/1 rise this point before a stop bit figure 19.7 example of op eration using modem control ( cts2 )
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 596 of 1036 rej09b0254-0600 ? serial data reception figures 19.8 and 19.9 show sample serial receptio n flowcharts. after scif reception is enabled, use the following procedure to perform serial data reception. start reception read dr, er, brk flags in scssr2 all data received? end reception no yes brk v er v dr = 1? rdf = 1? yes yes clear re bit in scscr2 to 0 no no read rdf flag in scssr2 error processing read receive data in scfrdr2, and clear rdf flag in scssr2 to 0 (1) receive error handling and break detection: read the dr, er, and brk flags in scssr2 to identify any error, perform the appropriate error handling, then clear the dr, er, and brk flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd2 pin. (2) scif status check and receive data read : read the serial status register 2 (scssr2) and check that rdf = 1, then read the receive data in the receive fifo data register 2 (scfrdr2), read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can be identified by an rxi interrupt. (3) serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr2, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr2 can be ascertained by reading the lower bits of scfdr2. (1) (2) (3) figure 19.8 sample seri al reception flowchart (1)
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 597 of 1036 rej09b0254-0600 error processing end brk= 1? dr= 1? er = 1? yes yes clear dr, er, brk flags in scssr2 to 0 no no no receive error processing break processing read receive data in scfrdr2 1. whether a framing error or parity error has occurred in the receive data read from scfrdr2 can be ascertained from the fer and per bits in scssr2. 2. when a break signal is received, receive data is not transferred to scfrdr2 while the brk flag is set. however, note that the last data in scfrdr2 is h'00 and the break data in which a framing error occurred is stored. figure 19.9 sample seri al reception flowchart (2)
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 598 of 1036 rej09b0254-0600 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr2 in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the stop bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the r eceive shift register 2 (scrsr2) to scfrdr2. c. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr2. note: reception becomes in possible after a receive error occurred. 4. if the rie bit in scscr2 is set to 1 when th e rdf or dr flag changes to 1, a receive-fifo- data-full interrupt (rxi) request is generated. if the rie bit in scscr2 is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit in scscr2 is set to 1 when the brk flag changes to 1, a break reception interrupt (bri) request is generated. figure 19.10 shows an example of the operation for reception.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 599 of 1036 rej09b0254-0600 rdf fer eri interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle state (mark state) d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 19.10 example of scif receive operation (example with 8-bit data, parity, one stop bit) 5. when modem control is enabled, the rts2 signal is output when scfrdr2 is empty. when rts2 is 0, reception is possible. when rts2 is 1, this indicates that scfrdr2 is full and reception is not possible. figure 19.11 shows an example of the operation when modem control is used. 0 0/1 0 1 rts2 parity bit serial data rxd2 start bit start d 0 d 1 d 2 d 7 figure 19.11 example of op eration using modem control ( rts2 )
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 600 of 1036 rej09b0254-0600 19.4 scif interrupts the scif has four interrupt sources: transmit -fifo-data-empty (txi), receive-error (eri), receive-data-full (rxi), and break (bri). table 19.9 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie and rie bits in scscr2. a separate interrupt request is sent to the interrupt controller for each of these interrupt sources. when the tdfe flag in the serial status register 2 (scssr2) is set to 1, a txi interrupt request is generated. the dmac can be activated and data transfer performed when this interrupt is generated. the tdfe flag is cleared when data exceeding the transmit trigger number is written to transmit fifo data register 2 (scftdr2) by the dmac, 1 is read from tdfe, and then 0 is written to tdfe. when the rdf flag in scssr2 is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed when the rd f flag in scssr is set to 1. the rdf flag is cleared when receive data is r ead from receive fifo data regi ster 2 (scfrdr2) by the dmac until the quantity of receive data in scfrdr2 is less than the receive trigger number, 1 is read from rdf, and then 0 is written to rdf. when the er flag in scssr2 is set to 1, an eri interrupt request is generated. when the brk flag in scssr2 is set to 1, a bri interrupt request is generated. the txi interrupt indicates that transmit data can be written, and the rxi interrupt indicates that there is receive data in scfrdr2. table 19.9 scif interrupt sources interrupt source description dmac activation priority on reset release eri interrupt initiated by receive error flag (er) impossible high rxi interrupt initiated by receive data fifo full flag (rdf) or data ready flag (dr) possible (rdf only) bri interrupt initiated by br eak flag (brk) impossible txi interrupt initiated by transmit fifo data empty flag (tdfe) possible low see section 4, exception processing, for prioritie s and the relationship with non-scif interrupts.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 601 of 1036 rej09b0254-0600 19.5 usage notes note the following when using the scif. 1. scftdr2 writing and the tdfe flag: the tdfe flag in the serial status register 2 (scssr2) is set when the number of transmit data byte s written in the transmit fifo data register 2 (scftdr2) has fallen below the transmit trigge r number set by bits ttrg1 and ttrg0 in the fifo control register 2 (scfcr2). after tdfe is set, transmit data up to the number of empty bytes in scftdr2 can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr2 is less than or equal to the transmit trigger number, the tdfe flag will be set to 1 ag ain after being cleared to 0. the tdfe flag should therefore be cleared to 0 after a number of data bytes exceeding the transmit trigger number has been written to scftdr2. the number of transmit data bytes in scftdr2 can be found from the upper 8 bits of the fifo data count set register 2 (scfdr2). 2. scfrdr2 reading and the rdf flag: the rdf flag in the serial status register 2 (scssr2) is set when the number of receive data bytes in the receive fifo data register 2 (scfrdr2) has become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register 2 (scfcr2). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr2, allowing efficient co ntinuous reception. however, if the number of data bytes in scfrdr2 exceeds the trigger number, the rdf flag will be set to 1 again after being cleared to 0. the rdf flag should therefore be cleared to 0 when 1 has been written to rdf after all receive data has been read. the number of receive data bytes in scfrdr2 ca n be found from the lower 8 bits of the fifo data count set register 2 (scfdr2). 3. break detection and processing: break signals can be detected by reading the rxd2 pin directly when a framing error (fer) is detected. in the break state the input from the rxd2 pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. note that, although transfer of receive data to scfrdr2 is halted in the break state, the scif receiver continues to operate, so if the brk flag is cleared to 0 it will be set to 1 again. 4. sending a break signal: the i/o condition and level of the txd2 pin are determined by the scp4dt bit in the port sc data register 2 (scpdr2) and bits scp4md0 and scp4md1 in the port sc control register 2 (scpcr2). this feature can be used to send a break signal. to send a break signal during serial transmission, clear the cp4dt bit to 0 (designating low level), then set the scp4md0 and scp4md1 bits to 1 and 0, respectively, and finally clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd2 pin.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 602 of 1036 rej09b0254-0600 5. tend flag and te bit processing: the tend flag is set to 1 during transmission of the stop bit of the last data. consequently, if the te b it is cleared to 0 immediately after setting of the tend flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. therefore, the te bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits ar e used) after setting of the tend flag setting is confirmed. 6. receive data sampling timing and receive margin: the scif operates on a base clock with a frequency of 16 times the transfer rate. in recep tion, the scif synchroni zes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 19.12. 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 base clock receive data (rxd2) synchro- nization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 19.12 receive data sampling timing in asynchronous mode the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). equation 1: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5) f ? (1 + f) 100% ........................ (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 603 of 1036 rej09b0254-0600 from equation (1), if f = 0 and d = 0.5, the r eceive margin is 46.875%, as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % ............................................................. ......................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%.
section 19 serial communication interface with fifo (scif) rev.6.00 mar. 27, 2009 page 604 of 1036 rej09b0254-0600
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 605 of 1036 rej09b0254-0600 section 20 serial io (siof) 20.1 overview siof is a clock-synchronized se rial i/o module that can be di rectly connected to the audio codec. 20.1.1 features feature of siof are listed below. ? serial transmitting ? 32 bit 16 step sized fifo fo r send or receive communication ? 8 bit/16 bit/recording or playback function for 16 bit stereo sound ? both big endian and little endian are supported in data transmission and reception ? variable sampling rate up to 48 khz ? synchronization corresponds to frame sync pulse and switching right/left channels ? support codec control function through data line ? support linear/audio a-law and -law codec chip ? support both master and receive communication mode ? serial clock ? external clock or peripheral clock (p ) may be used as clock source. ? interrupt it is possible to require independe ntly the following 4 interruptions. ? transmit interrupt ? receive interrupt ? error interrupt ? control interrupt ? dma transfer ? supports transmit/receive opera tions using dma transfer in response to a transmit/receive transfer request
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 606 of 1036 rej09b0254-0600 20.1.2 block diagram figure 20.1 shows siof block diagram. control register 16 32 tx_fifo 32 bits 16 stages bus i/f peripheral clock (p ) rxd_sio txd_sio sck_sio siofsync 32 32 32 peripheral bus rx_fifo 32 bits 16 stages s/p rx control data 32 32 timing control eri cci rxi txi siomclk baud rate generator p/s tx control data 1/n mclk siof figure 20.1 siof block diagram
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 607 of 1036 rej09b0254-0600 20.1.3 terminal table 20.1 shows pin list of siof. table 20.1 siof pin list name symbol i/o function clock input pin siomclk i master clock input communication clock pin sck_sio i/o serial clock (common for transmitting/ receiving) frame sync pin siofsync i/o frame sy nchronized signal (common for transmitting/receiving) transmit data pin txd_sio o transmit data receive data pin rxd_sio i receive data 20.1.4 register configuration table 20.2 lists the inte rnal registers of siof. table 20.2 siof register configuration name symbol r/w initial value address access size serial mode register simdr r/w h'0000 h'040000c0 (h'a40000c0) * 16 clock select register siscr r/w h'0000 h'040000c2 (h'a40000c2) * 16 transmit data assign register sitdar r/w h'0000 h'040000c4 (h'a40000c4) * 16 receive data assign register sirdar r/w h'0000 h'040000c6 (h'a40000c6) * 16 control data assign register sicda r r/w h'0000 h'040000c8 (h'a40000c8) * 16 serial control register sictr r/w h'0000 h'040000cc (h'a40000cc) * 16 fifo control register sifctr r/w h'1000 h'040000d0 (h'a40000d0) * 16 status register sistr r/w h'0000 h'040000d4 (h'a40000d4) * 16 interruption enabling register siier r/w h'0000 h'040000d6 (h'a40000d6) * 16 transmit data register sitdr w h'0000 h'040000e0 (h'a40000e0) * 32 receive data register sirdr r h'0000 h'040000e4 (h'a40000e4) * 32 transmit control register sitcr r/w h'0000 h'040000e8 (h'a40000e8) * 32 receive control register sircr r h'0000 h'040000ec (h'a40000ec) * 32 note: * use the address surrounded by parenthesis when the address translation process by mmu is not applied. refer to section 20.3.5, control data interface fo r more details of the control data.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 608 of 1036 rej09b0254-0600 20.2 register description 20.2.1 mode register (simdr) this register sets the operating mode of siof. this register is initialized by the power on reset or manual reset. bit: 15 14 13 12 11 10 9 8 trmd1 trmd0 ? redg fl3 fl2 fl1 fl0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r * r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 txdiz lsbf rcim ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r * r * r * r * r * note: * 0 must be written into these bits. the operation of this lsi is unpredictable when setting the value other than 0. bits 13 and 4 to 0?reserved bits 15 and 14?transmit mode setting (trmd1 and trmd0) bit 15: trmd1 bit 14: trmd0 description 0 0 slave mode 1 (initial value) 1 slave mode 2 1 0 master mode 1 1 master mode 2 note: refer to section 20.3.3, transmit data format for more details of the functions of each mode. bit 12?receive with sa mpling edge (redg): txd_sio is output at the opposite edge from the sampling time of rxd_sio. (see figure 20.4)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 609 of 1036 rej09b0254-0600 bit 12: redg description 0 sample rxd_sio by falling edge of sck_sio (initial value) 1 sample rxd_sio by rising edge of sck_sio note: this mode is effective in master mode 1 or master mode 2. bits 11 to 8?frame length (fl3 to fl0) bit 11: fl3 bit 10: fl2 bit 9: fl1 bit 8: fl0 description 0 0 0/1 * 0/1 * slot size is 8 bit, frame length is 8 bit (initial value) 1 0 0 slot size is 8 bit, frame length is 16 bit 1 slot size is 8 bit, frame length is 32 bit 1 0 slot size is 8 bit, frame length is 64 bit 1 slot size is 8 bit, frame length is 128 bit 1 0 0/1 * 0/1 * slot size is 16 bit, frame length is 16 bit 1 0 0 slot size is 16 bit, frame length is 32 bit 1 slot size is 16 bit, frame length is 64 bit 1 0 slot size is 16 bit, frame length is 128 bit 1 slot size is 16 bit, frame length is 256 bit notes: 1. when 8 bit slot size is chosen, contro l data is not able to be transmitted or received. 2. when lsb first is chosen, control data is not able to be transmitted or received. * same setting in both 1 and 0. (don?t care) bit 7?hi-z output control under ineffective case for transmission (txdiz): ineffective case is the case of transmit data or command are not assigned or transmit operation is disabled. bit 7: txdiz description 0 1 output ineffective transmission (initial value) 1 hi-z output ineffective transmission bit 6?lsb first transmission and reception (lsbf): selects msb first or lsb first for the transmission or reception frame. bit 6: lsbf description 0 msb first (initial value) 1 lsb first
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 610 of 1036 rej09b0254-0600 bit 5?transmit or receive contro l command interrupt mode (rcim) bit 5: rcim description 0 set rcrdy bit of sistr register wh en the contents of sircr register is changed. (initial value) 1 set rcrdy bit of sistr register wh en every control commands are received and set to sircr register 20.2.2 clock select register (siscr) this register sets the operate of baud rate genera tor. to set up this register, trmd bit of simdr register must be set 10 or 11. this register is initialized in po wer on reset or software reset. bit: 15 14 13 12 11 10 9 8 mssel msimm ? brps4 brps3 brps2 brps1 brps0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r * r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? brdv2 brdv1 brdv0 initial value: 0 0 0 0 0 0 0 0 r/w: r * r * r * r * r * r/w r/w r/w note: * 0 must be written into this bit. the operation of this lsi is unpredictable when setting the value other than 0. bit 15?master clock source choice (mssel): master clock means the clock that is input to the baud rate generator. bit 15: mssel description 0 use external clock source siomclk input signal as master clock (initial value) 1 use peripheral clock (p ) as master clock
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 611 of 1036 rej09b0254-0600 bit 14?master clock select (msimm) bit 14: msimm description 0 use baud rate generator output clock as clock source (initial value) 1 use master clock as clock source bits 13 and 7 to 3?reserved bits 12 to 8?setting of prescaler (brps4 to brps0): the dividing ratio of master clock (brps) is set within the range of 00001 (1/1 time s), 00010 (1/2 times), to 11111 (1/31 times) and 00000 (1/32 times: initial value). bits 2 to 0?setting of dividing ratio (brdv2 to brdv0): set the dividing ratio of frequency of output stage (brdv). finally, baud rate is decided by the value of brps * brdv (maximum 1/1024). bit 2: brdv2 bit 1: brdv1 bit 0: brdv0 description 0 0 0 1/2 times of prescaler output (initial value) 1 1/4 times of prescaler output 1 0 1/8 times of prescaler output 1 1/16 times of prescaler output 1 0 0 1/32 times of prescaler output settings other than the above (reserved)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 612 of 1036 rej09b0254-0600 20.2.3 transmit data assign register (sitdar) this register specifies the data a ssignment of transmit data in each transmit frame. this register is initialized in power on reset or software reset. bit: 15 14 13 12 11 10 9 8 tdle ? ? ? tdla3 tdla2 tdla1 tdla0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 tdre tlrep ? ? tdra3 tdra2 tdra1 tdra0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r/w r/w r/w r/w bits 14 to 12, 5, and 4?reserved bit 15?transmit data for left channel enable (tdle) bit 15: tdle description 0 disable data transmitting of left channel data (initial value) 1 enable data transmitting of left channel data bits 11 to 8?transmit data for left channel assignment (tdla3 to tdla0): the slot assignment of transmit data for left channel in transmit frame is specified from 0000(0: initial value) to 1110(14) by this register. the transmit da ta for left channel is set in bits sitdl 15 to sitdr register. note: the operation of this lsi is unpredicta ble when setting 1111 in bits tdla3 to tdla0. bit 7?transmit data for right channel enable (tdre) bit 7: tdre description 0 disable data transmitting of right channel data (initial value) 1 enable data transmitting of right channel data
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 613 of 1036 rej09b0254-0600 bit 6?transmit left channel data repeatedly (tlrep): setting of this bit is effective when tdre bit is 1. when 1 is set to this bit, setting of bits 15 to 0 in sitdr register is ignored. bit 6: tlrep description 0 the data in sitdr bit of sitdr register is transmitted as right channel data. (initial value) 1 the data in sitdl bit of sitdl register is transmitted as right channel data. bits 3 to 0?transmit data for right channel slot assignment (tdra3 to tdra0): the slot assignment of transmit data for right channel in transmit frame is specified from 0000(0: initial value) to 1110(14) by this register. the transmit data for right channel is set in sitdr bits 15 to 0 in sitdr register. note: the operation of this lsi is unpredictable when setting 1111 in bits tdra3 to tdra0. 20.2.4 receive data assign register (sirdar) this register specifies the data assignment of received data in each received frame. this register is initialized at power on reset or software reset. bit: 15 14 13 12 11 10 9 8 rdle ? ? ? rdla3 rdla2 rdla1 rdla0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 rdre ? ? ? rdra3 rdra2 rdra1 rdra0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r/w r/w r/w r/w bits 14 to 12, and 6 to 4?reserved bit 15?receive data for le ft channel enable (rdle) bit 15: rdle description 0 disable receiving of left channel data (initial value) 1 enable receiving of left channel data
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 614 of 1036 rej09b0254-0600 bits 11 to 8?receive data for left ch annel slot assignment (rdla3 to rdla0): the slot assignment of received data for left channel in received frame is specified from 0000(0: initial value) to 1110(14) by this register. the receive data for left channel is stored in bits 15 to 0 in sirdl of sirdr register. note: the operation of this lsi is unpredicta ble when setting 1111 in bits rdla3 to rdla0. bit 7?receive data for righ t channel enable (rdre) bit 7: rdre description 0 disable receiving of right channel data (initial value) 1 enable receiving of right channel data bits 3 to 0?receive data for right ch annel slot assignmen t (rdra3 to rdra0): the slot assignment of received data for right channel in received frame is specified from 0000(0: initial value) to 1110(14) by this register. the receive data for right channel is stor ed in bits 15 to 0 in sirdr of sirdr register. note: the operation of this lsi is unpredictable when setting 1111 in bits rdra3 to rdra0. 20.2.5 control command assign register (sicdar) this register specifies the pos ition of control command in each frame . the setting to this register is enabled when 1*** is set to bits fl3 to fl0 of simdr register. this register is initialized at power on reset or software reset. bit: 15 14 13 12 11 10 9 8 cd0e ? ? ? cd0a3 r/w2 r/w1 r/w0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 cd1e ? ? ? cd1a3 cd1a2 cd1a1 cd1a0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r/w r/w r/w r/w bits 14 to 12, and 6 to 4?reserved
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 615 of 1036 rej09b0254-0600 bit 15?control command data channel 0 enable (cd0e) bit 15: cd0e description 0 disable transmitting or receiving of control command of channel 0. (initial value) 1 enable transmitting or receiving of control command of channel 0. bits 11 to 8?control command data assignment for channel 0 (cd0a3 to cd0a0): the slot assignment for control channel 0 in tran smit and receive frames is specified from 0000(0: initial value) to 1110( 14) by this register. the receive data for control channel 0 is set in bits sitc05 to sitc00 of sircr register. the receive data for control channel 0 is stored in bits sirc015 to sirc00 in sircr register. note: the operation of this lsi is unpredicta ble when setting 1111 in bits cd0a3 to cd0a0. bit 7?control command data channel 1 enable (cd1e) bit 7: cd1e description 0 disable transmitting or receiving of control command of channel 1. (initial value) 1 enable transmitting or receiving of control command of channel 1. bits 3 to 0?control command data assignment for channel 1 (cd1a3 to cd1a0): the slot assignment for control channel 1 in transmit and receive frames is specified from 0000(0: initial value) to 1110(14) by this register. the receive data for control channel 1 is set in bits sirc115 to sirc10 of sircr register. note: the operation of this lsi is unpredicta ble when setting 1111 in bits cd1a3 to cd1a0.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 616 of 1036 rej09b0254-0600 20.2.6 serial control register (sictr) this register sets the operating states of siof. this register is initialized at po wer on reset or software reset. bit: 15 14 13 12 11 10 9 8 scke fse ? ? ? ? txe rxe initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? txrst rxrst initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r w w bits 13 to 10, and 7 to 2?reserved bit 15?serial clock output enable (scke): this bit is effective in master mode. when 1 is set to this bit, siof initializes baud rata generato r, then starts, operation, and outputs the clock that is generated by baud rate generator to sck_sio. bit 15: scke description 0 disable output of sck_sio (outputs 0) (initial value) 1 enable output of sck_sio bit 14?frame synchronize signal output enable (fse): this bit is effective at master mode. when 1 is set to this bit, siof initializes the frame counter, then starts operation. bit 14: fse description 0 disable output of siofsync (outputs 0) (initial value) 1 enable output of siofsync
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 617 of 1036 rej09b0254-0600 bit 9?transmit enable (txe): setting of this bit becomes effec tive when next frame starts (at the rising edge of frame synchron ize signal)and data are stored in transmit fifo. after the setting ?1? to this bit becomes effective, siof submit th e transmit request accordi ng to the tfwm bit of sifctr register. when data is sets to transmit fifo, transmit da ta is transfer from txd_sio. this bit is initialized at transmit reset. bit 9: txe description 0 disable to transmit data from tx d_sio (outputs 1) (initial value) 1 enable to transmit data from txd_sio bit 8?receive enable (rxe): setting of this bit is effective when next frame starts (at the rising edge of frame synchronizing signal). after the se tting ?1? to this bit becomes effective, siof begins to receive the data from rxd_sio. when data is sets to the receive fifo, siof submits the request to transfer acco rding to rfwm bit of sifctr register . this bit is initialized at receive reset. bit 8: rxe description 0 disable to receive data from rxd_sio (initial value) 1 enable to receive data from rxd_sio bit 1?transmitting operation reset (txrst): setting to this bit becomes effective immediately. after the setting 1 to this bit beco mes effective, siof change transmit data from txd_sio to 1 and initializes the following registers. 1. sitdr register 2. transmit fifo write pointer and read pointer 3. tcrdy, tfemp, and tdreq bits of sistr register 4. txe bit siof is cleared automatically when this bit complete s the reset, so 0 is always read from this bit. bit 1: txrst description 0 transmitting operation is not reset (initial value) 1 transmitting operation is reset
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 618 of 1036 rej09b0254-0600 bit 0?receiving operation reset (rxrst): setting to this bit becomes effective immediately. after the setting 1 to this bit becomes effective, siof initializes the following registers and stop receiving from rxd_sio. 1. sirdr register 2. receiving fifo write pointer and read pointer 3. rcrdy, rfful, and rdreq bits of sistr register 4. rxe bit siof is cleared automatically when this bit complete s the reset, so 0 is always read from this bit. bit 0: rxrst description 0 receiving operation is not reset (initial value) 1 receiving operation is reset 20.2.7 fifo control register (sifctr) this register set trigger point and show current available area of transm it and receive fifo. this register is initialized at power on reset or software reset. bit: 15 14 13 12 11 10 9 8 tfwm2 tfwm1 tfwm0 tfua4 tfua3 tfua2 tfua1 tfua0 initial value: 0 0 0 1 0 0 0 0 r/w: r/w r/w r/w r r r r r bit: 7 6 5 4 3 2 1 0 rfwm2 rfwm1 rfwm0 rfua4 rfua3 rfua2 rfua1 rfua0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r r r r r
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 619 of 1036 rej09b0254-0600 bits 15 to 13?transmit fifo water mark (tfwm2 to tfwm0): the transfer request of the transmit fifo is controlled by td req bit of sistr register. fifo depth is always 16 steps, nevertheless the setting to these bits. bit 15: tfwm2 bit 14: tfwm1 bit 13: tfwm0 description 0 0 0 the transfer request is submitted when the size of empty area in transmit fifo is 16 steps (initial value) 1 0 the transfer request is submitted when the size of empty area in transmit fifo is larger than 12 steps 1 the transfer request is submitted when the size of empty area in transmit fifo is larger than 8 steps 1 0 the transfer request is submitted when the size of empty area in transmit fifo is larger than 4 steps 1 the transfer request is submitted when the size of empty area in transmit fifo is larger than 1 step bits 7 to 5?receive fifo wa ter mark (rfwm2 to rfwm0): the transfer request of the receive fifo is controlled by td req bit of sistr register. fifo depth is always 16 steps, nevertheless the setting to these bits. bit 7: rfwm2 bit 6: rfwm1 bit 5: rfwm0 description 0 0 0 the transfer request is submitted when the size of empty area of receive fifo is larger than 1 step (initial value) 1 0 the transfer request is submitted when the size of empty area of receive fifo is larger than 4 steps 1 the transfer request is submitted when the size of empty area of receive fifo is larger than 8 steps 1 0 the transfer request is submitted when the size of empty area of receive fifo is larger than 12 steps 1 the transfer request is submitted when the size of empty area of receive fifo is at 16 steps bits 12 to 8?transmit fifo usable area (tfua4 to tfua0): tfua shows usable number of words for cpu or dmac to transfer from 00000 to 10000 (initial value). bits 4 to 0?receive fifo usab le area (rfua4 to rfua0): rfua shows usable number of words for cpu or dmac to transfer from 00000 (initial value) to 10000.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 620 of 1036 rej09b0254-0600 20.2.8 status register (sistr) this register shows states of siof. each bit of th is register becomes interrupt source when 1 is set to corresponding register of siier register. this register is initialized at po wer on reset or software reset. bit: 15 14 13 12 11 10 9 8 ? tcrdy tfemp tdreq ? rcrdy rfful rdreq initial value: 0 0 0 0 0 0 0 0 r/w: r * r * r * r * r * r * r * r * bit: 7 6 5 4 3 2 1 0 ? ? ? fserr tfovr tfudr rfudr rfovr initial value: 0 0 0 0 0 0 0 0 r/w: r * r * r * r/w r/w r/w r/w r/w note: * 0 should be written into these bits. ot herwise the operation is unpredictable. bits 15, 11, and 7 to 5?reserved bit 14?transmit control data ready (tcrdy): this bit displays condition of sitcr register. siof clears when any value is written to sitcr register. this bit becomes effective when 1 is written to txe bit of si ctr register. siof issues control interrupt if interrupt issuing is allowed for this bit. once any data are written to si ctr register with 0 of tcrdy bit, new data is overwritten to original data and orig inal data of txd_sio will be lost. note: when using this bit, refer to note 2 in section 20.4, notes on use. bit 14: tcrdy description 0 disable writing into sitcr register (initial value) 1 enable writing into sitcr register bit 13?transmit fifo empty (tfemp): this bit is showing condition, siof clear by writing to sitdr register. this bit become s effective when 1 is written to the txe bit of sictr register. siof issues control interrupt if inte rrupt issuing is allowed by this bit.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 621 of 1036 rej09b0254-0600 bit 13: tfemp description 0 transmit fifo is not empty (initial value) 1 transmit fifo is empty bit 12?transmit data transfer request (tdreq): the transmit data transfer request is issued when empty area of transmit fifo exceed the setting of tfwm bit of sifctr register. this bit is effective when 1 is written to txe b it of sictr register. this bit shows condition of transmit fifo. siof clears this b it if empty area of transmit fifo is smaller than the set value of tfwm bit of simdr register. siof issues a transmit interrupt if the interrupt issuing is allowed for this bit. bit 12: tdreq description 0 no transmit request exists. (initial value) 1 transmit request exists. bit 10?receive control data ready (rcrdy): this bit shows condition of sircr register. siof clears siof register wh en sircr register is read. new received data will be overwritten to sircr regist er if valid data is received and written to sircr register while this bit shows 1. this bit is effective when 1 is written to rxe bit of sictr register. siof issues a control interrupt if the interrupt issuing is allowed to bit. bit 10: rcrdy description 0 effective data is not stored in sircr register (initial value) 1 effective data is stored in sircr register bit 9?receive fifo full (rfful): this bit shows condition of receive fifo. siof clears when sirdr register is read. this bit is effectiv e when 1 is written to rxe bit of sictr register. siof issues a control interrupt when the interrupt issuing is allowed. bit 9: rfful description 0 receive fifo is not full (initial value) 1 receive fifo is full bit 8?receive data transfer request (rdreq): the receive data transfer request is issued when effective received data in receive fifo ex ceed the setting of rfwm bit of simdr register. this bit is effective when 1 is written to rxe b it of sictr register. this bit shows condition of receive fifo. siof clears this bit if effective received data ar ea in fifo is smaller than the set
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 622 of 1036 rej09b0254-0600 value of rfwm bit of simdr regist er. siof issues a receive interr upt if the interrupt issuing is allowed for this bit. bit 8: rdreq description 0 effective data in receive fifo does not exceed setting of rfwm bit of simdr register (initial value) 1 effective data in receive fifo exceeds setting of rfwm bit of simdr register bit 4?frame synchronization error (fserr): frame synchronization error shows that next frame synchronize timing has come before data or control command are transferred. when frame synchronization error has occurred , siof transmits or receives data to the slots that are enable to transmit or receive data. this bit becomes effective when 1 is written to tx e bit or rxe bit of sictr register. this bit is cleared when 1 is written to this bit. siof issues the transmit in terrupt when the interrupt issuing is allowed to this bit. bit 4: fserr description 0 frame synchronization error does not occur (initial value) 1 frame synchronization error occurs bit 3?transmit fifo over run (tfovr): transmit fifo overrun sh ows that data are written to sitdr register when transmit fifo is full. written data is ig nored when transmit fifo over run happens. this bit is effective when 1 is written to txe bit of sictr register. this bit is cleared when 1 is written to this bit. siof issues the transmit interr upt when the interrupt issuing is allowed to this bit. bit 3: tfovr description 0 transmit fifo over run does not occur (initial value) 1 transmit fifo over run occurs bit 2?transmit fifo under run (tfudr): transmit fifo under run shows that the load by data transfer from fifo has occurr ed when transmit fifo is empty. siof repeats to send the data that was sent before when this under run has occurred.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 623 of 1036 rej09b0254-0600 this bit is effective when 1 is written to rxe bit of sictr register. this bit is cleared when 1 is written to this bit. siof issues the transmit interr upt when the interrupt issuing is allowed to this bit. bit 2: tfudr description 0 transmit fifo under run does not occur (initial value) 1 transmit fifo under run occurs bit 1?receive fifo under run (rfudr): receive fifo under run shows that sirdr register is read when receive fifo is empty. the data that has been read out from sirdr is not guaranteed when this under run has occurred. this bit is effective when 1 is written to rxe bit of sictr register. this bit is cleared when 1 is written to this bit. siof issues the transmit interr upt when the interrupt issuing is allowed to this bit. bit 1: rfudr description 0 receive fifo under run does not occur (initial value) 1 receive fifo under run occurs bit 0?receive fifo over run (rfovr): receive fifo over shows write action has occurred to receive fifo by siof, when receive fifo is full. the receive d data disappears when receive fifo overrun occurs. this bit is effective when 1 is written to txe bit or rxe bit of sictr register. this bit is cleared when 1 is written to this bit. siof issues the transmit interrupt when the interrupt issuing is allowed to this bit. bit 0: rfovr description 0 transmit over run does not generate (initial value) 1 transmit over run generate
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 624 of 1036 rej09b0254-0600 20.2.9 interrupt enable register (siier) this register allows siof interr upt resources to issue interrupt to cpu. when 1 is written to each bit, corresponding interrupt is issued by siof. this register is initialized at power on reset, or software reset. bit: 15 14 13 12 11 10 9 8 ? tcrdye tfempe tdreqe ? rcrdye rffule rdreqe initial value: 0 0 0 0 0 0 0 0 r/w: r * r/w r/w r/w r * r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? fserre tfovre tfudre rfudre rfovre initial value: 0 0 0 0 0 0 0 0 r/w: r * r * r * r/w r/w r/w r/w r/w note: * 0 should be written into these bits. otherwise the operation is unpredictable. bits 15, 11, and 7 to 5?reserved bit 14?transmit control data ready enable (tcrdye) bit 14: tcrdye description 0 disable interrupt of transmit control data ready (initial value) 1 enable interrupt of transmit c ontrol data ready (control interrupt) bit 13?transmit fifo empty enable (tfempe) bit 13: tfempe description 0 disable interrupt of transmit fifo empty (initial value) 1 enable interrupt of transmit fifo empty (control interrupt) bit 12?transmit data transfer request enable (tdreqe) bit 12: tdreqe description 0 disable interrupt of transmit data transfer request enable (initial value) 1 enable interrupt of transmit data transfer request enable (transmit interrupt)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 625 of 1036 rej09b0254-0600 bit10?receive control data ready enable (rcrdye) bit10: rcrdye description 0 disable interrupt of receive control data ready (initial value) 1 enable interrupt of receive control data ready (control interrupt) bit 9?receive fifo full enable (rffule) bit 9: rffule description 0 disable interrupt of receive fifo full (initial value) 1 enable interrupt of receive fifo full (control interrupt) bit 8?receive data transfer request enable (rdreqe) bit 8: rdreqe description 0 disable interrupt of receive data transfer request (initial value) 1 enable interrupt of receive data transfer request (receive interrupt) bit 4?frame synchronization error enable (fserre) bit 4: fserre description 0 disable interrupt of frame synchronization error (initial value) 1 enable interrupt of frame synchronized error (error interrupt) bit 3?transmit fifo ov er run enable (tfovre) bit 3: tfovre description 0 disable interrupt of transmit fifo over run (initial value) 1 enable interrupt of transmit fifo over run (error interrupt) bit 2?transmit fifo under run enable (tfudre) bit 2: tfudre description 0 disable interrupt of transmit fifo under run (initial value) 1 enable interrupt of transmit fifo under run (error interrupt)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 626 of 1036 rej09b0254-0600 bit 1?receive fifo unde r run enable (rfudre) bit 1: rfudre description 0 disable interrupt of receive fifo under run 1 enable interrupt of receive fifo under run (error interrupt) bit 0?receive fifo over run enable (rfovre) bit 0: rfovre description 0 disable interrupt of receive fifo over run 1 enable interrupt of receive fifo over run (error interrupt) 20.2.10 transmit data register (sitdr) this register sets transmit data to siof. the data that has been set to this register is stored in transmit fifo. this register is initialized at powe r on reset, software re set, or transmit reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sitdl 15 sitdl 14 sitdl 13 sitdl 12 sitdl 11 sitdl 10 sitdl 9 sitdl 8 sitdl 7 sitdl 6 sitdl 5 sitdl 4 sitdl 3 sitdl 2 sitdl 1 sitdl 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: w w w w w w w w w w w w w w w w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sitdr 15 sitdr 14 sitdr 13 sitdr 12 sitdr 11 sitdr 10 sitdr 9 sitdr 8 sitdr 7 sitdr 6 sitdr 5 sitdr 4 sitdr 3 sitdr 2 sitdr 1 sitdr 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: w w w w w w w w w w w w w w w w bits 31 to 16?transmit data for left channel (sitdl15 to sitdl0): these bits set data transmitted from txd_sio as left channel data . the position for left channel side data are assigned as tdla bit of sitda register. this bit becomes effective when 1 is set to tdle bit of sitdar register. bits 15 to 0?transmit data for right channel (sitdr15 to sitdr0): these bits set data transmitted from txd_sio as right channel data . the position for left channel side data are assigned as tdra bit of sitda register. this bit becomes effective when 1 is set to tdre bit of sitdar register, and 0 is set to tlrep bit of sitdar register.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 627 of 1036 rej09b0254-0600 20.2.11 receive data register (sirdr) this register reads receive data of siof. the data fr om receive fifo is stored in this register. this register is initialized at power on reset, software reset, or transmit reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sirdl 15 sirdl 14 sirdl 13 sirdl 12 sirdl 11 sirdl 10 sirdl 9 sirdl 8 sirdl 7 sirdl 6 sirdl 5 sirdl 4 sirdl 3 sirdl 2 sirdl 1 sirdl 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirdr 15 sirdr 14 sirdr 13 sirdr 12 sirdr 11 sirdr 10 sirdr 9 sirdr 8 sirdr 7 sirdr 6 sirdr 5 sirdr 4 sirdr 3 sirdr 2 sirdr 1 sirdr 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bits 31 to 16?receive data for le ft channel (sirdl15 to sirdl0): these bits stores received data from rxd_sio as left channel data . the position of left channel side data are assumed as the position what defined by rdla bit of sirdar register. these bits are effective when 1 is wr itten to rdle bit of sirdar register. bits 15 to 0?receive data for ri ght channel (sirdr 15 to sirdr0): these bits stores received data from rxd_sio as right channel da ta. the position of left channel side data are assumed as the position what defined by rdra bit of sirdar register. these bits are effective when 1 is wr itten to rdre bit of sirdar register.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 628 of 1036 rej09b0254-0600 20.2.12 transmit control data register (sitcr) this register sets the transmit control data for siof . setting to this register is effective when 1*** is set to fl bit of simdr register. this register is initialized at power on reset, software reset, or transmit reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sitc0 15 sitc0 14 sitc0 13 sitc0 12 sitc0 11 sitc0 10 sitc0 9 sitc0 8 sitc0 7 sitc0 6 sitc0 5 sitc0 4 sitc0 3 sitc0 2 sitc0 1 sitc0 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sitc1 15 sitc1 14 sitc1 13 sitc1 12 sitc1 11 sitc1 10 sitc1 9 sitc1 8 sitc1 7 sitc1 6 sitc1 5 sitc1 4 sitc1 3 sitc1 2 sitc1 1 sitc1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 16?transmit control data for channel 0 (sitc015 to sitc00): these bits stores data to be transfer as transmit control channel 0 data from txd_sio. the position of control data for channel 0 is determined by the setting of cd0a bit of sicdar register. this bit is effective when 1 is set to cd0e bit of sicdar register. bits 15 to 0?siof transmit control data for channel 1 (sitc115 to sitc10): these bits stores data to be transfer as transmit control channel 1 command from txd_sio. the position of control data for channel 1 is determined by the setting of cd1a bit of sicdar register. this bit is effective when 1 is set to cd1e bit of sicdar register.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 629 of 1036 rej09b0254-0600 20.2.13 receive control data register (sircr) this register stores the received control data for siof. setting to this register is effective when 1*** is set to fl bit of simdr register. this re gister is initialized at po wer on reset, software reset, or receive reset. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sirc0 15 sirc0 14 sirc0 13 sirc0 12 sirc0 11 sirc0 10 sirc0 9 sirc0 8 sirc0 7 sirc0 6 sirc0 5 sirc0 4 sirc0 3 sirc0 2 sirc0 1 sirc0 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirc1 15 sirc1 14 sirc1 13 sirc1 12 sirc1 11 sirc1 10 sirc1 9 sirc1 8 sirc1 7 sirc1 6 sirc1 5 sirc1 4 sirc1 3 sirc1 2 sirc1 1 sirc1 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 16?receive data for channel 0 (sirc015 to sirc00): received data from rxd_sio as control channel 0 data is stored to these bits. the position of control channel 0 data is determined by the setting of cd0a bit of sicdar register. this bit is effective when 1 is set to cd0e bit of sicdar register. bits 15 to 0?receive data for channel 1 (sirc115 to sirc10): received data from rxd_sio as control channel 1 data is stored to these bits. the position of control channel 1 data is determined by the setting of cd1a bit of sicdar register. this bit is effective when 1 is set to cd1e bit of sicdar register.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 630 of 1036 rej09b0254-0600 20.3 operation 20.3.1 serial clock (1) master/slave there are two modes as serial clock listed as below. ? slave mode: sck_sio and siofsync is input. ? master mode: sck_sio and siofsync is output. (2) baud rate generator (brg) at the siof master mode, serial clock is generated using the baud rate generator (brg). the baud rate can be selected from 1/2 to 1/1024. figure 20.2 shows the serial clock supply system. from 1/2 to 1/1024 mclk master oe brg siomclk peripheral clock (p ) sck_sio e timing control figure 20.2 serial clock supply system table 20.3 shows examples about serial clock frequency. table 20.3 examples of siof clock frequency sampling rate frame length 8 khz 44.1 khz 48 khz 32 bits 256 khz 1.4112 mhz 1.536 mhz 64 bits 512 khz 2.8224 mhz 3.072 mhz 128 bits 1.024 mhz 5.6448 mhz 6.144 mhz 256 bits 2.048 mhz 11.2896 mhz 12.288 mhz note: in master mode, sck_sio c ontinues to be output regardless of whether there is any data.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 631 of 1036 rej09b0254-0600 20.3.2 serial timing (1) siofsync siofsync is the frame sync signal, and supports the two modes shown below. ? the pulse with 1 bit width which shows the first of the sync pulse frame. ? the pulse with 1/2 frame width, which shows left channel in l/r stereo data as high and right channel as low. figure 20.3 shows synchronized timing as siof sync. figure 20.3(a) s hows the case for master mode 1, slave mode 1, and slave mode 2. figure 20.3(b) shows the case for master mode 2. (a) at the synch pulse 1 frame first bit data (msb) 1 frame 1/2 frame length no delay 1 bit delay 1/2 frame length (b) at the l/r sck_sio siofsync txd_sio rxd_sio sck_sio siofsync txd_sio rxd_sio lch. first bit data (msb) rch. first bit data (msb) figure 20.3 siof serial data synchronized timing
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 632 of 1036 rej09b0254-0600 (2) transmit or receive timing timing to sck_sio for transmitt ing txd_sio or receiving rxd_ sio can be chosen from the following two cases. timing for tran smitting or receiving is set in to redg bit in simdr register. in slave mode 1 or slave mode 2, only the sample at falling is valid. ? sample at falling ? sample at rising figure 20.4 shows the timing for transmitting or receiving. (a) falling sampling receive timing transmit timing sck_sio siofsync txd_sio rxd_sio (b) rising sampling receive timing transmit timing sck_sio siofsync txd_sio rxd_sio figure 20.4 siof transmit or receive timing 20.3.3 transmit data format siof transmit two kind of data shown below. ? transmit or receive data: transmit data of 8 bit/16 bit/16 bit stereo ? control data: 16 bit length (interf ace by using the de dicated register) (1) transmit mode siof has four modes as transmit mode shown in table 20.4. transmit mode is set to bits trmd1 to trmd0 in simdr register. table 20.4 serial transmit mode transmit mode siofsync bit delay control data slave mode 1 sync pulse 1 bit slot position slave mode 2 sync pulse 1 bit secondary fs master mode 1 sync pulse 1 bit slot position master mode 2 l/r nothing no support
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 633 of 1036 rej09b0254-0600 (2) frame length frame length of siof transmitting is set by bits fl3 bit to fl0 in simdr register. table 20.5 shows relations between value and frame length. table 20.5 frame length fl3, fl2, fl1, fl0 slot length bit/frame support transmit data 00 - - 8 8 8 bit monaural 0100 8 16 8 bit monaural 0101 8 32 8 bit monaural 0110 8 64 8 bit monaural 0111 8 128 8 bit monaural 10 - - 16 16 16 bit monaural/stereo 1100 16 32 16 bit monaural/stereo 1101 16 64 16 bit monaural/stereo 1110 16 128 16 bit monaural/stereo 1111 16 256 16 bit monaural/stereo (3) slot position siof can set the position of transmit data, receive data, and control data (common in transmit/receive) in 1 frame indepe ndently by slot number. the followi ng register are used for this setting. ? transmit data: sitdar register ? receive data: sirdar register ? control data: sicdar register control data is effective when the slot length is 16 bit. the control data for transmission and reception is always assigned to the same slot.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 634 of 1036 rej09b0254-0600 20.3.4 register assign ment for transfer data (1) transmit or receive data writing into/reading out of tr ansmit/receive data is done for the following registers. ? writing transmit data: sitdr register (32 bit access) ? reading receive data: sird r register (32 bit access) figure 20.5 shows bit alignmen t of transmit or receive data and sitdr and sirdr registers. (a) at the 16 bit stereo 31 24 23 16 15 8 7 0 lch. data rch. data (b) at the 16 bit monaural 31 24 23 16 15 8 7 0 data (d) at the 16 bit stereo (right and left same sound) 31 24 23 16 15 8 7 0 data (c) at the 8 bit monaural 31 24 23 16 15 8 7 0 data figure 20.5 transmit or receive data bit alignment note: in figure 20.5, only data portions that are shown by the oblique lines are transmitted or received as effective data. thus, the areas without the oblique lines ar e not the object to transmit or receive.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 635 of 1036 rej09b0254-0600 monaural or stereo of transmit data is set with tdle bit and tdre bit of siltdar register. to choose monaural or stereo for receive, rdle bit an d rdre bit of sirdar register must be set. the same sound for right and left in transmit da ta is set with tlrep bit of sitdar register. table 20.6 shows establishment of sound mode for transmit data, table 20.7 shows establishment of sound mode for receive data, use only the left channel in case of monaural 8 bits transfer. table 20.6 transmit data sound mode bit mode tdle tdre tlrep monaural 1 0 * stereo 1 1 0 same sound for right and left 1 1 1 * : don?t care table 20.7 receive data sound mode bit mode rdle rdre monaural 1 0 stereo 1 1 note: same mode for right and le ft don?t exist in receive data.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 636 of 1036 rej09b0254-0600 (2) control data control data is read out/written into the following registers. ? writing transmit control data: si tcr register (32 bit access) ? reading receive control data: sircr register (32 bit access) figure 20.6 shows bit a lignments of transmit or receive data and sitcr and sircr registers. (b) at the control data 2ch. 31 24 23 16 15 8 7 0 (a) at the control data 1ch. 31 24 23 16 15 8 7 0 control data ch. 0 control data ch. 0 control data ch. 1 figure 20.6 contro l data bit alignment the channel number of control data is set w ith cd0e bit cd1e bit of sicdar register. table 20.8 establishment of ch. number for control data. use channel 0 when using only data one channel as control data. table 20.8 control data channel number establishment bit ch. number cd0e cd1e 1 1 0 2 1 1
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 637 of 1036 rej09b0254-0600 20.3.5 control data interface control data outputs the control command to codec and receive the state of codec. siof support the following two operations as an interface operation of control data. ? control by the slot positions ? control by secondary fs control data is effective when selecting 16 bit as data length and msb first receive mode. (1) control by slot positions (master mode 1) this is the method that dedicates the slot passion of control data in a frame to transmit or receive the control data. figure 20.7 shows a sample of control data interface timing by slot position. note: when using this method, peripheral clock (p ) should be used as the master clock (master clock select (mssel) = 1). 1 frame setting: trmd = 00 or 10, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0001, fl = (frame length 128 bits), tdre = 1, tdra3 to tdra0 = 0010, rdre = 1, rdra3 to rdra0 = 0010, cd1e = 1, cd1a3 to cd1a0 = 0011 sck_sio siofsync txd_sio rxd_sio lch. data control ch.0 rch. data control ch.1 ? slot no.0 slot no.1 slot no.2 slot no.3 figure 20.7 control data interface (slot position)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 638 of 1036 rej09b0254-0600 (2) control by secondary fs this is the method that codec, which outputs siofsync as a sync. pulse (fs), transmit or receive the control data by outputting the second ary fs used for transmit or receive for only control data after the period of 1/2 frame, which is different from the original fs output position. order of the control data interface as secondary fs are listed below. ? normal data are sent as lsb=0 (compulsory is 0 by siof) ? transmit data of lsb=1 at transmitting the control data (for 1 by siof reading to sitcr register) ? codec transmits secondary fs ? siof synchronizes secondary fs and transmit or receive (storing into sircr register) the control data (setting data in sitcr register) figure 20.8 shows timing of contro l data interface by secondary fs. 1 frame 1/2 frame setting: lsb = "1? " (secondary fs request) trmd = 01, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0000, fl = 1100 (frame length 28 bits) tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio 1/2 frame lch.data control ch.0 slot no.0 slot no.0 normal fs normal fs secondary fs figure 20.8 control data interface (secondary fs)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 639 of 1036 rej09b0254-0600 20.3.6 fifo (1) outline features of siof transmit or r eceive fifo are listed as below. ? capacity of 32 bits 16 stages for each of transmission and reception ? pointer is updated by a read/write cycle for all of the access sizes of cpu and dmac (it is impossible to separate on e stage access to multiple times) ? access cycle number is always 2 cycles (p bus cycle) for all of the access sizes. (2) transmit request transmit request of fifo is displayed in the following two bits of sistr register. ? transmit request: tdreq (transmit interrupt factor) ? receive request: rdreq (receive interrupt factor) it is possible to set independently the condition for each of submitting transmit request of transmit or receive fifo. condition of transmit request are set to bits tfwm2 to tfwm0 in sifctr register and transfer request of receive fifo are set to bits rfwm2 to rfwm0. table 20.9 shows transmit request submit condition, and table 20.10 shows receive request submit condition. table 20.9 transmit request submit condition tfwm2 to tfwm0 request stage number transmit request submit used area 000 1 16 stages empty area small 100 4 over 12 stages empty area 101 8 over 8 stages empty area 110 12 over 4 stages empty area 111 16 over 1 stage empty area large
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 640 of 1036 rej09b0254-0600 table 20.10 receive reque st submit condition rfwm2 to rfwm0 request stage number receive request submit used area 000 1 over 1 stage effective area small 100 4 over 4 stages effective area 101 8 over 8 stages effective area 110 12 over 12 stages effective area 111 16 16 stages effective area large when the data area or empty area exceed the above stage number, fifo ca pacity always can be used 16 stages. therefore, over flow or under flow error are submitted wh en the data area, or empty area excesses 16 stages. even if fifo is not empty or full, the transm it request is cancelled when the above conditions become not to be satisfied. (3) showing of stage number the state of using transmit or receive fifo is displayed in the following registers. ? transmit fifo: shows stage number of empty area to bits tfua4 to tfua0 in sifctr register ? receive fifo: shows stage number of effectiv e data to bits rfua4 to rfua0 of sifctr register the above contents show the number of data which cpu or dmac can transfer.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 641 of 1036 rej09b0254-0600 20.3.7 procedures for transmit or receive (1) transmitting in master figure 20.9 shows an example of setting and operation of transmitting in master. no. time chart setting content of siof siof operation 1 2 3 4 5 6 7 8 9 start end y y n n tdreq = 1? finish to transmit? settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register "1" is set to scke bit of sictr register sck_sio begin to transmit "1" is set to fse bit of sictr register "1" is set to txe bit of sictr register setting of sitdr register synchronized to siofsync, content of sitdr is setn from txd_sio "0" is set to txe bit of sictr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request set the beggin to operation of baud rate generator set the transmit enable set the begin to transmit of frame synchronized signal set the transmit data set to transmit disable finish to transmit transmit frame synchronized signal submit the transmit request transmit transmit serial clock figure 20.9 example of transmit operation in master
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 642 of 1036 rej09b0254-0600 (2) receiving in master figure 20.10 shows an example of receiving and operation in master. no. time chart setting content of siof siof operation 1 2 3 4 5 6 7 8 9 start end y y n n rdreq = 1? finish to transmit? settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register "1" is set to scke bit of sictr register sck_sio begin to transmit ?1? is set to fse bit of sictr register "1" is set to rxe bit of sictr register synchronized to siofsync receive data from rxd_sio is stored to sirdr setting of sirdr register "0" is set to rxe bit of sictr register setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request set the beggin to operation of baud rate generator set the begin to transmit of frame synchronized signal set the transmit enable reading of receive data set to transmit disable transmit serial clock transmit frame synchronized signal receive request is submitted by limit of reveive fifo receive finish to receive figure 20.10 example of receive operation in master
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 643 of 1036 rej09b0254-0600 (3) transmitting in slave figure 20.11 shows an example of transmitting and operation in slave. no. time chart setting content of siof siof operation 1 2 3 4 5 6 start end y y n n tdreq = 1? finish to transmit? setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register "1" is set to txe bit of sictr register setting of sitdr register synchronized to siofsync send content of sitdr from txd_sio "0" is set to txe bit of sictr register set transmit enable set the transmit data set to transit disable disable to transmit when frame synchronized transmit submit the transmit request transmit finish to transmit figure 20.11 example of transmit operation in slave
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 644 of 1036 rej09b0254-0600 (4) receiving in slave figure 20.12 shows an example of receiving and operation in slave. no. time chart setting content of siof siof operation 1 2 3 4 5 6 start end y y n n rdreq = 1? finish to transmit? setting of operation mode, serial clock, slot position of transmit or receive data, slot position of control data and limit of fifo request settting of simdr register, siscr register, sitdar register, sirdar register, sicdar register, sifctr register "1" is set to txe bit of sictr register synchronized to siofsync store receive data from rxd_sio to sirdr reading of sirdr register "0" is set to rxe bit of sictr register set the receive enable reading of receive data set to receive disable receiving enable when frame synchronized signal receive receive request is submitted by receive fifo limit receive finish to receive figure 20.12 example of receive operation in slave
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 645 of 1036 rej09b0254-0600 (5) transmit or receive reset siof can reset independently the transmit and recei ve portions by setting 1 in the following bits. ? transmit reset: (txrst bit of sictr register) ? receive reset: (rxrst bit of sictr register) table 20.11 shows the initialized contents by transmit or receive reset. table 20.11 transmit or receive reset reset type initialized register or bits transmit reset sitdr register transmit fifo write pointer transmit fifo read pointer tcrdy, tfemp, and tdreq bits in sistr register txe bit in sictr register receive reset sirdr register receive fif0 write pointer receive fif0 read pointer rcrdy, rfful, and rdreq bits in sistr register rxe bit in sictr register (6) module stop siof stops transmit or receive operation with holding the contents of all registers at module stop. issue the transmit or receive reset, when the transmit or receive oper ation is not executed directly after the module stop.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 646 of 1036 rej09b0254-0600 20.3.8 interrupt siof has the following four types of interrupt. these types are reflected to irr4 register in interrupt controller (intc). ? transmit interrupt (txi) ? receive interrupt (rxi) ? control interrupt (cci) ? error interrupt (eri) (1) interrupt factor each interrupt is submitted by its multiple factors. each factor is shown in siof register as siof states. table 20.12 shows siof interrupt factors. table 20.12 siof interrupt factors no. type bit function explanation of interrupt 1 transmit (txi) tdreq transmit fifo send request data of over setting is stared to transmit fifo 2 receive (rxi) rdreq receive fifo send request data of over setting is stared to receive fifo 3 tcrdy transmit control data ready enable writing into transmit control data register 4 rcrdy receive control data ready valid data is stored in receive control data register 5 tfemp transmit fifo empty transmit fifo is empty 6 control (cci) rfful receive fifo full receive fifo is full 7 tfudf transmit fifo under flow the serial data send timing comes when transmit fifo is empty 8 tfovf transmit fifo over flow write to transit fifo when transmit fifo is full 9 rfovf receive fifo over flow receive serial data when receive fifo is full 10 rfudf receive fifo under flow read receive fifo when receive fifo is empty 11 error (eri) fserr f3 error serial signal is received before setting bit number (at slave)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 647 of 1036 rej09b0254-0600 it depends on setting of siier register whether or not an interrupt corresponding to each interrupt factor is submitted or not depend. siof submits each interrupt when interrupt f actor that 1 is set to corresponding bit of siier register is set to 1. (2) transmit/receive interrupt flag transmit or receive interrupt requests intc or dmac to accept the interruption through the interrupt flag, which is generated from the valu e of tdreq bit and rdreq bit in sistr register. table 20.13 shows the setting conditions for the transmit or receive interrupt flag. table 20.13 setting conditions for the transmit or receive interrupt flag setting conditions resetting conditions transmit interrupt flag tdreq in sistr register = 1 ? tdreq in sistr register = 0 ? acknowledge from dmac receive interrupt flag rdreq in sistr register = 1 ? rdreq in sistr register = 0 ? acknowledge from dmac (3) operations in case of error siof executes the following op erations for the errors which are shown in sistr as status. ? transmit fifo under run (tfudr): the data th at was transmitted direc tly before is sent again. ? transmit fifo over run (tfovr): the contents of transmit fifo is protected, the written data that became to over flow is ignored. ? receive fifo over run (r fovr): data that became to over flow is disposed and vanished. ? receive fifo under run (r fudr): data that is read as final data is output on bus. (indefinite in specification) ? fs error (fserr): internal counter is reset according to the sync. signal that b ecame to error.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 648 of 1036 rej09b0254-0600 20.3.9 transmit or receive timing figures 20.13 to 20.19 show examples of serial transmit or receive of siof. (1) a case of 8 bits monaural (no.1) sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot no. 0, frame length is 8 bits. 1 frame 1 bit delay setting: trmd = 00 or 10, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0000, fl = 0000 (frame length 16 bits), tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio lch. data slot no.0 figure 20.13 transmit or recei ve timing (8 bits monaural?1) (2) a case of 8 bits monaural (no.2) sync pulse method, falling edge sampling, transmit da ta and receive data are assigned to slot no.0, frame length is 16 bits. 1 frame setting: trmd = 00 or 10, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 0, cd0a3 to cd0a0 = 0000, fl = 0100 (frame length 16 bits), tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio slot no.0 slot no.1 lch. data 1 bit delay figure 20.14 transmit or recei ve timing (8 bits monaural?2)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 649 of 1036 rej09b0254-0600 (3) a case of 16 bits monaural (no.1) sync pulse method, falling edge sampling, transmit data and receive data are assigned to slot no. 0, frame length is 64 bits. 1 frame setting: trmd = 00 or 10, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 0, cd0a3 to cd0a0 = 0000, fl=1101 (frame length 64 bits) tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio lch. data slot no.0 slot no.1 slot no.2 slot no.3 1 bit delay figure 20.15 transmit or receive timing (16 bits monaural?1) (4) a case of 16 bits stereo (no.1) l/r method, rising edge sampling and lch. data are assigned to slot no. 0, rch.data is assigned to slot no. 1, and frame length is 32 bits. 1 frame setting: trmd = 11, redg = 1, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0= 0000, cd0e = 0, cd0a3 to cd0a0 = 0000, fl = 1100 (flame length 32 bits), tdre = 1, tdra3 to tdra0 = 0001, rdre = 1, rdra3 to rdra0 = 0001, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio slot no.0 no delay lch. data slot no.1 rch. data figure 20.16 transmit or receive timing (16 bits stereo?1)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 650 of 1036 rej09b0254-0600 (5) a case of 16 bits stereo (no.2) l/r method, rising edge sampling and lch.transmit data are assigned to slot no. 0, lch. receive data are assigned to slot no.1, lch. receive data are assigned to slot no. 2, rch. receive data is assigned to slot no. 3, and frame length is 64 bits. 1 frame setting: trmd = 11, redg = 1, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0001, cd0e = 0, cd0a3 to cd0a0 = 0000, fl = 1101 (frame length 64 bits), tdre = 1, tdra3 to tdra0 = 0010, rdre = 1, rdra3 to rdra0 = 0011, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio slot no.0 no delay slot no.1 slot no.2 slot no.3 lch. data rch. data rxd_sio lch. data rch. data figure 20.17 transmit or receive timing (16 bits stereo?2) (6) a case of 16 bits stereo (no. 3) sync pulse method, falling edge sampling and lch. da ta are assigned to slot no. 0, rch. data is assigned to slot no. 2, control ch. data 0 is assigned to slot no. 1, control ch. data 0 is assigned to slot no. 3, and frame length is 128 bits. 1 frame setting: trmd = 00 or 10, redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0001, fl = 1110 (frame length 128 bits), tdre = 1, tdra3 to tdra0 = 0010, rdre = 1, rdra3 to rdra0 = 0010, cd1e = 1, cd1a3 to cd1a0 = 0011 sck_sio siofsync txd_sio rxd_sio 1 bit delay lch. data control ch. 0 rch. data control ch. 1 slot no.0 slot no. 1 slot no. 2 slot no. 3 slot no. 4 slot no. 5 slot no. 6 slot no. 7 figure 20.18 transmit or receive timing (16 bits stereo?3)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 651 of 1036 rej09b0254-0600 (7) a case of bits monaural (no. 2) sync pulse method, falling edge sampling and seconda ry fs are requested, lch. data is assigned to slot no. 0, control ch. data 0 are assigned to slot no. 0, and frame length is 128 bits. 1 frame sck_sio (a) when the control ch. is not transferred (b) when the control ch. is transferred siofsync txd_sio rxd_sio 1 bit delay lch. data slot no. 0 slot no. 1 slot no. 2 slot no. 3 slot no. 4 slot no. 5 slot no. 6 slot no. 7 lsb = ?0? (secondary fs request) 1 frame 1/2 frame setting: lsb = ?1? (secondary fs request) trmd = 01 redg = 0, tdle = 1, tdla3 to tdla0 = 0000, rdle = 1, rdla3 to rdla0 = 0000, cd0e = 1, cd0a3 to cd0a0 = 0000, fl = 1110 (frame length 128 bits), tdre = 0, tdra3 to tdra0 = 0000, rdre = 0, rdra3 to rdra0 = 0000, cd1e = 0, cd1a3 to cd1a0 = 0000 sck_sio siofsync txd_sio rxd_sio 1/2 frame normal fs normal fs secondary fs lch. data control ch.0 slot no.0 slot no.1 slot no.2 slot no.3 slot no.0 slot no.1 slot no.2 slot no.3 1 bit delay figure 20.19 transmit or recei ve timing (16 bits monaural?2)
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 652 of 1036 rej09b0254-0600 20.4 usage notes note the following when using the siof. for details on using versions previous to the SH7727b please refer to 20.4.1, notes on using the siof with versions previous to the sh 7727b, in addition to the notes below. 1. using the transmit function in sleep mode if transmission is enabled when data has alread y been written to the transmit fifo, one or two of the initial data bytes may be lost. therefore, data should not be written to the transmit fifo before enabling transmission. 2. using control data transmi ssion/reception consecutively on cont rol data interface (secondary fs position) the tcrdy value may become 1 before transmit control data is sent, and if the next control data is written to the control data register at this point, the control data waiting to be sent will be overwritten and erased. at this time, also, the control sequence is di srupted and the siof switches around the primary fs and secondary fs, with the result that transm ission/reception of data and control data can no longer be performed normally. the control data register should therefore be written to after transmit control data has been sent. example: reference rcrdy, and write to the cont rol data register when rcrdy is 1. after transmit control data has been written, it is essential to read the receive control register (sircr) and clear rcrdy. 3. dma transfer do not use 16-byte dma transfer. (see section 14.3.4, dma transfer types.) 4. access from the cpu when performing access from the cpu, do not access the si of's transmit/receive fifo consecutively, but instead insert an access to somewhere else between siof transmit/receive fifo accesses. 5. transmit/receive fifo underflow if the transmit/receive fifo underflows during a transmit/receive operation, control of the siof's transmit/receive fifo may fail and data may be lost. to prevent this, either set a watermark so that underflow does not occur, or execute a transmit reset (txrst) or receive reset (rxrst) wh en an empty interrupt is generated.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 653 of 1036 rej09b0254-0600 6. transmit/receive reset execution when using the siof again after a transmit/ receive operation ends, or after erroneous operation occurs, first execute a transmit reset (txrst) or receive reset (rxrst). 7. using the control data interface (slot position) loss of transmit or control data may occur if transmit and control data are mixed within a single frame during a transmit operation in any of the following modes: (1) master mode with an external clock (siomclk) used as the master clock (2) slave mode therefore, the control data interface (slot po sition) should be used under the following conditions: (1) master mode (2) master clock: peripheral clock (pclk) 8. serial io (siof) reception operation during serial io (siof) operation, if reception is performed with a slot length of 8 bits and lsb first, unwanted data is added at the start of the reception data, fifo storage is delayed one byte at a time, and the final portion of the data remains in the shift register. to prevent this, use one of the three methods described below. (1) perform reception using a slot length of 8 bi ts and lsb first, and read and discard the unwanted data. read and discard the unwanted data at the st art of the reception data. then, input a dummy fs after the final portion of data so that the real final portion of data is stored in the fifo. this will ensure that reception operates correctly when a slot length of 8 bits and lsb first is used. (2) perform reception using a slot length of 8 bits and msb first, then use software processing to convert the data to lsb-first format. data reception operates correctly when a slot length of 8 bits and msb first is used. after receiving the data in msb-first format, use so ftware processing to convert the data read from the fifo from msb-first to lsb-first format. the result can then be used as 8-bit slot length lsb-first data. (3) perform reception using a slot length of 16 bi ts and lsb first, and read only the required data. data reception operates correctly when a slot le ngth of 16 bits and lsb first is used. then one of the following two methods can be used to obtain data that can be used as 8-bit slot length lsb-first data. (a) make settings on the transmitting side so that only the upper 8 bits are used for actual data. then, after the 16-bit data is receive d by the SH7727, extract the upper 8 bits and use it as 8-bit slot length lsb-first data.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 654 of 1036 rej09b0254-0600 (b) transmit two 8-bit units of data at once. then, after the 16-bit data is received by the SH7727, separate the upper and lower 8-bit portions and treat them as two 8-bit units of data. they can then be used as 8-bit slot length lsb-first data. 20.4.1 notes on using the siof with versions previous to the SH7727b notes when using siof, the following phenomenon may occur. (1) during siof transmit with dma transferring, siof may suddenly stop internal dma transfer request, then underflow error ocurs and transmit operation stops. (2) during siof transmit and transmit fifo empt y, underflow or overflow, some data transmit may fail, depending on the timing relationship between transmit fifo write in and read out. (3) during siof receive operation with dma inte rnal peripheral module request mode, some data receive may fail, due to unexpect ed overflow errors caused on the manner that only one data transfer request exceeding watermark of receive fifo. (4) during receive operation, some receive data may fail when a write occurs at reading from receive fifo. (5) during siof receive operation and receive fi fo empty, underflow or overflow, some data receive may fail, depending on the timing relati onship between receive fifo write in and read out. in this case, the statuses of full, underflow, and overflow may not be reflected to flags. countermeasures countermeasures to deal w ith software using siof. (1) notes (1) and (2) with referring to transmit fifo transfer reques t interrupt (siftxi) caused by under watermark of transmit fifo, write the exactly same number of data with that of transmit fifo empty slots with dma auto request. at that time, make sure to set the watermark va lue so as not to occur transmit fifo empty nor underflow when transmit operation. example: when 12 empty slots are set to transmit fifo, write 12 data to transmit fifo with dma auto request by transmit fi fo transfer inte rrupt (siftxi). (2) notes (3), (4), and (5) with referring to receive fifo transfer requ est interrupt (sifrxi) caused by over watermark of receive fifo, read the (va lid number ? 2) of data from receive fifo with dma auto request. read operation shall be done before next receive data write.
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 655 of 1036 rej09b0254-0600 at that time, make sure to set the watermark va lue so as not to receive fifo full nor overflow when receive operation. example: when 12 empty slots are set to receive fifo, read 12 data from receive fifo with dma auto request by receive fifo transfer interrupt (sifrxi). etc. (1) not to use dma 16 bytes transfer. (s ee section 14.3.4, dma transfer types.) (2) recommend dma auto request for siof access. when from cpu, not to use continuous access. (3) when newly use siof after transmit/receive operation, proceed transfer operation after transmit reset (txrst) or receive reset (rxrst).
section 20 serial io (siof) rev.6.00 mar. 27, 2009 page 656 of 1036 rej09b0254-0600
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 657 of 1036 rej09b0254-0600 section 21 analog fr ont end interface (afeif) 21.1 overview this lsi has an afe interface that supports soft waremodem. this afe interface can efficiently execute the modem processing, because it includes 128 stages of fifo for each of transmission and reception. this af e interface also includes the interf ace to data access arrangement (daa) such as dial pulse generator circuit and ringing de tection. therefore, it is possible to establish a modem system with a minimum of hardware. 21.1.1 features ? serial interface with fifo ? clock synchronized serial interface ? transmit/receive fifo size is 16 bits (maximum) 128 words ? transmit/receive interrupt thre shold size is programmable ? dial pulse generator circuit is included ? ringing detection (calling signal) function is included
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 658 of 1036 rej09b0254-0600 21.1.2 block diagram figure 21.1 shows a block diagram of afeif. bus i/f 16 16 16 16 16 32 pp-bus ringing detector dial pulse generator control registers tx_fifo 16 bit 128 word afe control word afe status word hc control p/s s/p afe_rxin afe_hc1 afe_txout afe_sclk afe_fs afe_rlycnt afe_rdet rx_fifo 16 bit 128 word 16 16 16 figure 21.1 block di agram of afe interface
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 659 of 1036 rej09b0254-0600 21.1.3 pin configuration table 21.1 shows the pins for afe interface. table 21.1 pins for afe interface pin no. name i/o function 121 afe_rdet i ringing signal input 114 afe_rlycnt o on-hook control signal 116 afe_sclk i shift clock 118 afe_fs i frame synchronization signal 119 afe_rxin i serial receive data 113 afe_hc1 o afe hardware control signal 120 afe_txout o serial transmit data 21.1.4 register configuration table 21.2 shows registers fo r afeif. byte access registers to these is inhibited. table 21.2 afeif registers register name abbre- viation r/w initial value address access size afeif control register 1 actr1 r/w h'0000 h'04000180 16 afeif control register 2 actr2 r/w h'0000 h'04000182 16 afeif status register 1 ast r1 r/w h'0f0a h'04000184 16 afeif status register 2 astr2 r/w h'0300 h'04000186 16 make ratio count register mrcr r/w h'0000 h'04000188 16 minimum pose count register mpcr r/w h'0000 h'0400018a 16 dial number queue dpnq r/w h'0000 h'0400018c 16 ringing pulse counter rcnt r h'0000 h'0400018e 16 afe control data register acdr r/w h'0000 h'04000190 16 afe status data register asdr r h'0000 h'04000192 16 transmit data fifo port tdfp w undetermined h'04000194 32 (16) receive data fifo port rdfp r undetermined h'04000198 32 (16)
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 660 of 1036 rej09b0254-0600 21.2 register description 21.2.1 afeif control register 1 and 2 (actr1, actr2) actr is the control register for afeif and is composed of actr1 and actr2. actr1 is mainly used for fifo control commands. actr2 is used for afe control commands and daa control commands. (1) afeif control register 1 (actr1) bit: 15 14 13 12 11 10 9 8 hc ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r r r r r bit: 7 6 5 4 3 2 1 0 dlb ? ? ffsz2 ffsz1 ffsz0 te re initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r r/w r/w r/w r/w r/w bits 14 to 8, 6, and 5?reserved bit 15?afe hardware control bit (hc): this bit controls afe. afe_hc1 signal is made to high directly often the next serial transmit data tr ansfer, when this bit is written to 1. then acdr data (afe control word) is transferred by founding the second afe.fs. afeif module automatically makes afe_hc1 signal to low and hc bit to 0, directly after transferring the afe control word. see section 21.3 .2, afe interface for more deta il about afe control sequences. bit 7?fifo digital loop back (dlb) bit 7: dlb description 0 normal operation (initial value) 1 digital loop back between tx fifo and rx fifo is performed. in this time the transmit data is output to afe_txout, too.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 661 of 1036 rej09b0254-0600 bits 4 to 2?fifo interrupt size set 2 to 0 (ffsz2 to ffsz0): specifies the size of fifo. fifo size to generate interrupt (tfe, rff, the, and rhf) is assigned as follows: description bit 4: ffsz2 bit 3: ffsz1 bit 2: ffsz0 fifo size tfe/rff the/rhf 0 0 0 128 128 empty/full 64 empty/full (initial value) 1 64 64 empty/full 32 empty/full 1 0 32 32 empty/full 16 empty/full 1 16 16 empty/full 8 empty/full 1 0 0 8 8 empty/full 4 empty/full 1 4 4 empty/full 2 empty/full 1 0 2 2 empty/full 1 empty/full 1 96 96 empty/full 48 empty/full bit 1?tx enable (te) bit 1: te description 0 transmit operation is disabled. the read pointer of fifo is stacked to the first address. write pointer is reset when 0 is written to this bit. tfem and them bits in astr1 is set to 1 at that time. (initial value) 1 transmit operation is enabled. bit 0?rx enable (re) bit 0: re description 0 receive operation is disabled. the write/read pointer is fixed to the first address. rffm and rhfm bits in astr1 is set to 1 at that time. 1 receive operation is enabled
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 662 of 1036 rej09b0254-0600 (2) afeif control register 2 (actr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? dpst pps rcen ? rlyc initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r/w r/w r r/w bits 15 to 5, and 1?reserved bit 4?dial pulse start (dpst): start bit of dial pulse. dial num ber within the dpnq register is output to afe_rlycnt as specified by pps, m rcr and mpcr. after all dial number is output , dpe interrupt is generated to modify the dpst bit to 0. see section 21.3.3, daa interface for more detail about dial pulse output sequence. take care that afe_rlycnt must be ?h? to enable dial pulse generating circuit bit 3?dial pulse duration set (pps) bit 3: pps description 0 10pps (initial value) 1 20pps bit 2?ringing counter enable (rcen) bit 2: rcen description 0 stop ringing counter (initial value) 1 start ringing counter note: see section 21.3.3, daa interfac e for more detail ab out how to count.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 663 of 1036 rej09b0254-0600 bit 0?relay control (rlyc): the signal controls hook relay. bit 0: rlyc description 0 on hook state. afe_rlycnt goes low level. (initial value) 1 off hook state. afe_rlycnt goes high level. 21.2.2 make ratio count register (mrcr) mrcr is the counter that specifies make ratio of dial pulse. make interval is specified with afe_fs as base clock of 9,600 hz. pulse signal is not output when an invalid data (a data that is greater than 1e0h in case of pps = 1 (20 pps), or a data that is greater than 3c0h in case of pps = 0 (10 pps)) was input. bit: 15 14 13 12 11 10 9 to 0 ? ? ? ? ? ? mrcr initial value: 0 0 0 0 0 0 0 r/w: r r r r r r r/w 21.2.3 minimum pause count register (mpcr) mpcr is a counter that sets the dial number interv al of the dial pulse. the interval is specified with afe_fs as base clock of 9600 hz. bit: 15 to 0 mpcr initial value: 0 r/w: r/w
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 664 of 1036 rej09b0254-0600 21.2.4 afeif status register 1 and 2 (astr1, astr2) astr is the control register for afeif, and composed of astr1 and astr2. astr1 is mainly used for transmit/receive fifo interrupt contro l commands. astr2 is used for daa interrupt control commands. see section 21.3.1, interrupt timing for more detail about interrupt handling. (1) afeif status register 1 (astr1) bit: 15 14 13 12 11 10 9 8 ? ? ? ? tfem rffm them rhfm initial value: 0 0 0 0 1 1 1 1 r/w: r/w r r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? tfe rff the rhf initial value: 0 0 0 0 1 0 1 0 r/w: r r r r r r r r astr1 is composed by interrupt status flags (4 bits) relating transmit/receive fifo and mask flags (4 bits) for transmit/receive fifo interrupt signal. status fl ag displays full/empty interrupt status of transmit/receive fifo and half size interrupt status for fifo. fifo empty (tfe) and fifo half size interrupt(the) shows ?1? as initia l value, because transmit fifo is empty after power on reset. these interrupt flags are to be cl eared with the data write / read action to fifo from cpu. each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in interrupt status flag. every mask bits are automatically set when te or re bit are modified to 1. tfem and them are 1 when te = 0. rffm and rh fm are ?1? when re = ?0?. each mask bit are reset as 1. bits 15 to 12 and 7 to 4?reserved bit 11?tx fifo empty interrupt mask (tfem) bit 11: tfem description 0 tfe interrupt enable (initial value) 1 tfe interrupt masked
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 665 of 1036 rej09b0254-0600 bit 10?rx fifo full interrupt mask (rffm) bit 10: rffm description 0 rff interrupt enable (initial value) 1 rff interrupt masked bit 9?threshold of tx fifo empty interrupt mask (them) bit 9: them description 0 the interrupt enable (initial value) 1 the interrupt masked bit 8?threshold of rx fifo full interrupt mask (rhfm) bit 8: rhfm description 0 rhf interrupt enable (initial value) 1 rhf interrupt masked bit 3?tx fifo empty interrupt (tfe) bit 3: tfe description 0 normal state (initial value) 1 tfifo empty interrupt set condition: 1. reset 2. no effective data in area of fifo 3. te bit (actr1) is set to 0 (tfem is automatically masked in case 3.) clear condition: 1. data are written into fifo
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 666 of 1036 rej09b0254-0600 bit 2?rx fifo full interrupt (rff) bit 2: rff description 0 no interrupt (initial value) 1 rx fifo full interrupt set condition: 1. specified size with ffsz(actr1) of r eceive data is accumulated into fifo. clear condition: 1. reset 2. number of data in fifo becomes smaller than the size that is indicated with ffsz (actr1). 3. re bit (actr1) is set to 0. bit 1?tx fifo half size empty (the) bit 1: the description 0 normal state (initial value) 1 tx fifo half size interrupt set condition: 1. reset 2. number of valid data in fifo becomes smaller than the half of the size that is indicated with ffsz. 3. te bit (actr1) is set to 0 (them is automatically masked in case 3.) clear condition: 1. number of valid data in fifo becomes greater than the half of the size that is indicated by ffsz.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 667 of 1036 rej09b0254-0600 bit 0?rx fifo half size full (rhf) bit 0: rhf description 0 normal state (initial value) 1 rx fifo half size interrupt set condition: 1. the half of specified size with ffsz (actr1 ) of receive data is accumulated into fifo. clear condition: 1. reset 2. number of data in fifo becomes smaller than the half of the size that is indicated by ffsz (actr1). 3. re bit (actr1) is set to 0 (2) afeif status register 2 (astr2) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? dpem rdetm initial value: 0 0 0 0 0 0 1 1 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? dpe rdet initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w astr2 is the register that is composed of interrupt status flag (2 bits) relating daa control and mask flag (2 bits) of interrupt signals for daa control. status flags shows statuses of ringing detect interrupt, end of dial pulse output interrup t. interrupt flags are cleared by 0 write after read action of this register. each interrupt signal ar e able to be masked by each interrupt masks. bit 9?dial pulse end interrupt mask (dpem) bit 9: dpem description 0 interrupt enable (initial value) 1 interrupt mask
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 668 of 1036 rej09b0254-0600 bit 8?ringing detect mask (rdetm) bit 8: rdetm description 0 ringing interrupt enable (initial value) 1 ringing interrupt mask bit 1?dial pulse end (dpe) bit 1: dpe description 0 normal state (initial value) 1 dial pulse end interrupt set condition: 1. output of all of dial pulse sequences completed or end command 0h detected 2. illegal end (unspecified dial number and dpst set when rlyc bit (actr2) is low level) clear condition: 1. reset 2. interrupt status 1 is read and then 0 is written to this bit. bit 0?ringing detect (rdet) bit 0: rdet description 0 normal state (initial value) 1 ringing waveform detect set condition: 1. ringing waveform is input to afe_rdet pin (latched at rising edge) clear condition: 1. reset 2. interrupt status 1 is read and then 0 is written to this bit.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 669 of 1036 rej09b0254-0600 21.2.5 dial pulse number queue (dpnq) this is the dial pulse number queue up to 4 digits which has 4-bits registers. this queue generates dial pulse according to the following table in the order of dial pulse number. a dial-pulse-end interrupt is sent out after dn3 is output or if 0h or a value other than the corresponding data is detected. bit: 15 to 12 11 to 8 7 to 4 3 to 0 dn0 dn1 dn2 dn3 initial value: 0000 0000 0000 0000 r/w: r/w r/w r/w r/w table 21.3 telephone number and data tel no. corresponding data 0 ah 1 1h 2 2h 3 3h 4 4h 5 5h 6 6h 7 7h 8 8h 9 9h pause fh end 0h
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 670 of 1036 rej09b0254-0600 21.2.6 ringing pulse counter (rcnt) the result of counting 1 cycle of ringing wave form with afe_fs is shown here. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcnt initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r bits 15 to 0?ringing counter value (rcntv): the result of counting 1 cycle of input ringing wave form with afe_fs (output of afe). s ee section 21.3.3, daa in terface for more detail about the ringing detect sequence. 21.2.7 afe control data register (acdr) acdr is the register to store the afe control word . after 1 is written to hc bit (actr1), data is transferred to afe at the timing of 3rd fs. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acdr initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 21.2.8 afe status data register (asdr) asdr is the register to store the afe status word . after 1 is written to hc bit (actr2), data is transferred to asdr from afe at the timing of 3rd fs. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 asdr initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 671 of 1036 rej09b0254-0600 21.2.9 transmit data fifo port (tdfp) tdfp is the write only port for transmit fifo. transmit fifo has 128 stages (maximum), and can generate interrupt of the data empty as well as of the threshold size speci fied by ffsz (actr1). directly after the reset and when te (actr1) bit is 0, the pointer of fifo is set to the first address and data becomes empty. the interrupt w ill occur when the te bit (actr1) is written to 1 at that state. in normal case, te bit should be changed after writing data into transmit fifo. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdfp initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: w w w w w w w w w w w w w w w w 21.2.10 receive data fifo port (rdfp) rdfp is the read only register for receive fifo . receive fifo has 128 stages (maximum), and can generate interrupt of the data full as well as of the threshold size speci fied by ffsz (actr1). directly after the reset and when re bit (actr1) is 0, the pointer of fifo is fixed at the first address and data from rdfp becomes undetermined. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdfp initial value: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r/w: r r r r r r r r r r r r r r r r 21.3 operation 21.3.1 interrupt timing afe interface module generates 3 types of interrupt: fifo data transfer, ri nging detect, and dial pulse transmit end. the timing of each interruption is described below. (1) fifo interrupt timing figure 21.2 shows interrupt timing of data tran sfer fifo. transmit fifo generates the tfe and the interrupts after the last data is transfer re d shift register. receive fifo generates the rff and rhf interrupt after the last data or specified word is transferred from shift register to fifo.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 672 of 1036 rej09b0254-0600 afe_fs data 1 data 2 half ? 1 half first first + 1 half ? 1 half afe_tx out tfe/tte a fe_fs afe_rx in rff/rtf figure 21.2 fifo interrupt timing (2) ringing interrupt timing as the figure 21.3 shows, the ringing signal from the line is transformed to rectangular wave and then input to afeif. the interrupt is generated at the rising edge of input wave in afeif module. ringing wave input wave int. occur figure 21.3 ringing interrupt occurrence timing (3) dial pulse interrupt timing dial pulse interrupt is generated in the dial pulse transmit sequence when afeif reads 0h (end) data from dpnq register or all of 4 digits are output. refer to section 21.3.3, daa interface about dial pulse sequence.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 673 of 1036 rej09b0254-0600 (4) interrupt generator circuit interrupt is generated as is shown in figure 21.4. that is, afeifi signal is generated by performing or operation on the four signals from astr1 in fifo interrupt control and the two signals from astr2 in daa interrupt control, and then sent out to intc as one interrupt signal. a str1 (fifo cont.) afeifi int. mask int. factor a str2 (daa cont.) int. mask int. factor 2 4 2 4 2 4 figure 21.4 interrupt generator 21.3.2 afe interface (1) serial data tr ansfer specification the specification for serial data transfer is base on that of stlc7550, which is an afe manufactured by st microelectronics. stlc7550 has a self-oscillation mode, and flame synchronous signal afe_fs used for serial transfer and serial bit clock afe_sclk are supplied by afe. figure 21.5 shows th e serial transfer interface. af ter outputting the valid data, afe_txout holds the value of lsb. a fe_fs msb lsb a fe_sclk a fe_txout a fe_rxin sampling period figure 21.5 afe serial interface
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 674 of 1036 rej09b0254-0600 (2) hc control sequence afeif module supports hardware control stlc7550 that is an afe manufactured by st microelectronics. figure 21.6 shows the afe control sequence. data word data word control word data word write 1 to hc bit of actr1 write "1" to hc bit of actr1 fs for data fs for data fs for data fs for data fs for data afe mode change hc1 goes to 0 hc1 goes to 1 fs for control word data data data data data data sampling period 1/2 sampling period mode change (3) (5) (4) (2) (1) afe_fs afe_txout afe_hc1 afe i/f stlc7550 hc0: kept to 1 1. if the cpu write " 1 " to the hc bit of actr1, the aefif drives afe_hc1 to " h " right after transmit next data. 2. afe fetches the hc1's status of " h " at rising edgge of next afe_fs. 3. afe output the fs at the next 1/2 sampling period and then afeif transfer the afe control word. 4. afeif keeps afe_hc1 to " h " for 2nd fs and return to " l " after transmit the control word. 5. afe fetches the afe_hc1's status of " l " and changes the mode of itself. figure 21.6 afe control sequence
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 675 of 1036 rej09b0254-0600 21.3.3 daa interface figure 21.7 shows the blocks diagram of daa circuit. ringing detect and dial pulse sending sequence are described below. afe_rlycnt afe_rdet afe (stlc7550) afeif tip ring hyblid circuit dc holding circuit hook relay ringing detector figure 21.7 daa block diagram (1) ringing detect sequence after the first ringing interrupt occurs, countin g starts with writing 1 into rcen bit of ctr2. afe must be operating before counting, because periodic counter counts afe_fs from falling edge to next falling edge. the value of rcntv register is effective only af ter 2nd interrupt generation, because the value of rcntv register is transferred from counter with a trigger of ending of 1st period cycle. rcntv will be 258h (600 in deci mal) if ringing cycle is 16hz and counted by 9600hz which is default value of afe_fs. figure 21.8 shows detecting sequence of ringing.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 676 of 1036 rej09b0254-0600 count up rcntv set rcntv set rcntv set rcntv set 1. first int occur. rcen (actr2) turns on. 2. from 2nd int, read the rcntv. 3. after acknowledge the ringing, rcen (actr) turns off and goes to off hook operation. figure 21.8 ringing detect sequence (2) dial pulse sending sequence a dial pulse is generated according to the conditions that are specified in actr2, and is sent out to afe_rlycnt. as the basic clock for generating the dial pulse is afe_fs that is input from afe, it is necessary to make afe in operating state. an example of control sequence for dial pulse sending is shown below. note that this sequence cannot be operated when rlyc bit (actr2) is low. [conditions] make ratio: 33% pulse interval: 20 pps minimum pause: 600 ms dial number: 0,1234567 (?,? means pause) [control sequence] 1. set pps (actr2) ?1?, mkr ?9eh1?, mnrpcnt ?1680h? 2. set dpnq ?af12h?. 3. set rlyc ?h?. (off hook) 4. detect dial tone or wait specific period. (controlled by software)
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 677 of 1036 rej09b0254-0600 5. write ?1? to dpst (actr2). (start sending dial pulse) 6. after 4 digit of dial pulses are sent, inte rrupt is generated. (dpst is reset to ?0?) 7. set dpnq1 ?3456h?. 8. write ?1? to dpst (actr2). 9. after 4 digit of dial pulses are sent, inte rrupt is generated. (dpst is reset to ?0?) 10. set dpnq2 ?70xxh?. 11. write ?1? to dpst (actr2). 12. after 1 digit of dial pulse is sent, interrupt is generated. (dpst is reset to ?0?, finish sending) 21.3.4 wake up ringing interrupt system wake up function by the ringing signal from telephone line is realized by inputting afe_rdet signal, that is an input signal for ringing, to pint pin.
section 21 analog front end interface (afeif) rev.6.00 mar. 27, 2009 page 678 of 1036 rej09b0254-0600
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 679 of 1036 rej09b0254-0600 section 22 usb pi n multiplex controller 22.1 feature the usb multiplex controller controls the data path to usb transceiver from usb host controller port 1 or usb function controller. both usb host port 1 and usb function contro ller are connected to usb transceiver 1 via multiplexer that is controlled by expfc regi ster. the usb host controller port 2 and usb transceiver 2 are connected one-to-one. usb tr ansceiver 1 can be connected to usb host controller or usb function controller, while usb transceiver 2 can only be connected to the usb host controller. because these ports and transceive rs are controlled individually, usb transceiver 2 can be connected to either the usb host controller or the usb function controller regardless its status. the signals to usb transceiver are us ed as external pins usb1d _**** which are multiplexed with pins 113 to 122.
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 680 of 1036 rej09b0254-0600 22.1.1 block diagram figure 22.1 shows the connections between the on-chip usb host controller of the SH7727, the usb function controller, and the on-chip 2-port usb transceiver. usb host usb function pwr_en usb2_pwr_en usb2_ovr_current usb2_p usb2_m usb1_pwr_en usb1_ovr_current / usbf_vbus usb1d_ **** usb1_p usb1_m pwr_en vbus pwr_en/ control pin multiplexer usb host/function transceiver signals multiplexer ovr_current / vbus multiplexer ovr_current ovr_current transceiver usb digital signal transceiver control port 1 port 2 usb transceiver 2 usb transceiver 1 power power transceiver transceiver port 1 power transceiver select select figure 22.1 block diagra m of usb pin multiplexer
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 681 of 1036 rej09b0254-0600 22.1.2 pin configuration usb pin multiplexer controller has pins that are shown in tables 22.1, 22.2, and 22.3. table 22.1 pin configuration (digital transceiver signal) name symbol i/o description rcv pin usb1d_rcv input input pin for re ceive data from differential receiver dpls pin usb1d_dpls input input pin for d + signal from receiver dmns pin usb1d_dmns input input pin for d ? signal from receiver txdpls pin usb1d_txdpls output d + transmit output pin txenl pin usb1d_txenl output driver output enable pin suspend pin usb1d_suspend output tran sceiver suspend state output pin speed pin usb1d_speed output transceiver speed control pin txse0 pin usb1d_txse0 output se0 state output pin note: the pins shown in table 22.1 are used for connecting an external usb transceiver, and cannot be used when the on-chip usb transceiver is connected. table 22.2 pin configuration (analog transceiver signal) name symbol i/o description 1p pin usb1_p i/o d+ port1 transceiver pin 1m pin usb1_m i/o d? port1 transceiver pin 2p pin usb2_p i/o d+ port2 transceiver pin 2m pin usb2_m i/o d? port2 transceiver pin note: the pins shown in table 22.2 can be used as two-port usb host controller pins or as one- port usb host controller pins and one-port usb function controller pins. leave these pins open or pull them down when not used.
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 682 of 1036 rej09b0254-0600 table 22.3 pin configurat ion (power control signal) name symbol i/o description power enable pin 1 usb1_pwr_en output usb port 1 power enable control power enable pin 2 usb2_pwr_en output usb port 2 power enable control one current pin 1/ vbus pin usb1_ovr_current / usbf_vbus input usb port 1 over-current detect/ usb cable connection monitor pin over current pin 2 usb2_ovr_current input usb port2 over-current detect note: the pins shown in table 22.3 can be used for power control of usb. pins for port 1 have the functions that are multiplexed functions of usb controller and usb function controller. 22.1.3 register configuration table 22.4 shows the registers for usb pin multiplexer controller. table 22.4 register configuration name abbreviation r/w initial value address access size extra pin function controller expfc r/w h'0000 h'a4000234 16
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 683 of 1036 rej09b0254-0600 22.2 register description 22.2.1 extra pin function controller (expfc) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? usb_ trans usb_sel initial value: 0 0 0 0 0 0 0 0 r/w: r r r/w * r/w * r/w * r/w * w w note: * 0 must be set in reading or writing. bits 15 to 2?reserved: write 0 to these bits. when 1 is written to this bits, the operation is unpredictable. bit 1?usb port 1 transceiver (usb_trans) bit 1 function 0 usb transceiver is enabled (initial value) 1 usb digital signals output is enabled bit 0?usb port 1 signal source selection (usb_sel) bit 0 function (signal source selection) 0 usb host is used (initial value) 1 usb function is used note: usb port 2 is for dedicated use by the usb host controller.
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 684 of 1036 rej09b0254-0600 22.3 examples of external circuit 22.3.1 example of the conne ction between usb function controller and transceiver figures 22.2 to 22.5 show example connections of usb function controller and transceiver. figures 22.2 and 22.3 show connections when using the built-in usb transceiver. figures 22.4 and 22.5 show connections when not using the built-in usb transceiver. when using the usb function controller, the signals must be input to the cable connection monitor pin ujbf_vbus. the usbf_vbus pin is multiplexed with the usb1_ovr_current pin, and writing 1 to bit 0 of the expfc register selects the usbf_vbus pin functions. according to the status of the usbf_vbus pin, the usb function controller recognizes whether the cable is connected/disconnected. also, pin d+ must be pulled up in order to notify the usb host/hub that the connection is established. the sample circuits in figures 22.2 to 22.5 use the usb1_pwr_en pin for pull-up control. SH7727 usb function usb connector ic allowing voltage application when system power is off usb1_pwr_en usbf_vbus usb1_p usb1_m vbus ic1 ic allowing voltage application when system power is off ic2 d + d ? gnd usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k 27 27 figure 22.2 example 1 of transceiver connection for usb function controller (on-chip transceiver is used)
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 685 of 1036 rej09b0254-0600 SH7727 usb function usb connector usb1_pwr_en usbf_vbus vbus d + d ? gnd usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k usb1_p usb1_m ic allowing voltage application when system power is off ic allowing voltage application when system power is off 27 27 ic1 ic2 figure 22.3 example 2 of transceiver connection for usb function controller (on-chip transceiver is used)
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 686 of 1036 rej09b0254-0600 SH7727 usb function usb connector usb1_pwr_en usbf_vbus vbus d + d ? gnd pdiusbp11a etc. speed d + d ? oe vpo vmo/fseo rcv vp vm suspend usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k ic1 ic allowing voltage application when system power is off ic2 ic allowing voltage application when system power is off figure 22.4 example 3 of transceiver connection for usb function controller (on-chip transceiver is not used)
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 687 of 1036 rej09b0254-0600 SH7727 usb function usb connector usb1_pwr_en usbf_vbus vbus d + d ? gnd pdiusbp11a etc. speed d + d ? oe vpo vmo/fseo rcv vp vm suspend usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k ic1 ic2 ic allowing voltage application when system power is off ic allowing voltage application when system power is off figure 22.5 example 4 of transceiver connection for usb function controller (on-chip transceiver is not used)
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 688 of 1036 rej09b0254-0600 d+ pull-up control control d+ pull-up by using usb1_pwr_en pin in the system when the connection?notification (d+ pull-up) to usb host or hub is wished to be inhibited (i.e., during high-priority processing or initialization processing). the d+ pull-up control signal and usbf_vbus pin input signal should be controlled by using the usb1_pwr_en pin and the usb cable vbus (and ci rcuit) as is shown in examples of figures 22.2 and 22.4 d+ pull-up is inhibited when the usb1_pwr_en pin is high in examples of figures 22.2 to 22.5. (the initial setting of the us b1_pwr_en pin is high.) pull-up d+ after confirming that usbf_vbus pi n became high, when th e pull-up control is performed directly by usb1_pwr_en pin as is shown in examples of figures 22.3 and 22.5. d+ pull-up is inhibited when the usb1_pwr_en pin is low in examples of figures 22.3 and 22.5. use an ic such that allows voltage applica tion when system power is off (for example, hd74lv1g126a) for the pull-up control ic (ic2 in figures 22.2 to 22.5). (the udc core in the SH7727 holds the powered state when usbf_vbus pin is low, regardless of the d + /d ? state.) detection of usb cable connection/disconnection as usb function controller in the SH7727 manages the state by hardware, usb_vbus signal is necessary to recognize connection or disconnec tion of the usb cable. the power supply signal (vbus) in the usb cable is used for usbf_vbus. however, if the cable is connected to the usb host or hub when the power of usb function controller (SH7727?installed system) is off, a voltage of 5 v will be applied from the usb host or hub. therefore, use an ic such that allows voltage ap plication when system power is off (for example, hd74lv1g08a) for the ic1 in figures 22.2 to 22.5.
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 689 of 1036 rej09b0254-0600 22.3.2 example of the co nnection between usb host controller and transceiver figures 22.6 and 22.7 show example connections of the usb host controller and transceiver. figure 22.6 shows an example connection using the built-in transceiver 1. by using the usb2_ovr_current , usb2_pwr_en, usb2_p, and usb2_m pins in an external circuit similar to that in figure 22.6, you can also use built-in usb transceiver 2. figure 22.7 shows an example connection when not using the built-in usb transceiver. when using the usb host controller, a separate lsi must be used for usb power bus control (equivalent to the usb power control lsis in figures 22.6 and 22.7). make sure the lsi ha s the power supply capacity to satisfy the usb standard, and select one that has an overcurrent protection function. configure the system so that the input to the usb1_ovr_current pin is low on detection of an overcurrent. SH7727 usb host usb connector usb1_pwr_en usb1_ovr_current gnd d + d ? usb power control lsi 15k 15k usb1_p usb1_m 5v 27 27 figure 22.6 example 1 of transceive r connection for usb host controller (on-chip transceiver is used)
section 22 usb pin multiplex controller rev.6.00 mar. 27, 2009 page 690 of 1036 rej09b0254-0600 SH7727 usb host usb connector usb1_pwr_en usb1_ovr_current gn d d + d ? pdiusbp11a etc. speed usb power control lsi d + d ? 15k 15k oe vpo vmo/fseo rcv vp vm suspend usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 5v figure 22.7 example 2 of transceive r connection for usb host controller (on-chip transceiver is not used) 22.3.3 usage notes about the usb transceiver usb transceiver is included in the SH7727. it is al so possible to connect an external transceiver according to the setting in expfc re gister (see figures 22.4, 22.5, an d 22.7). in this case, ask the manufacturer of the transceiver about the reco mmended circuit that is used between the usb transceiver and usb connectors. about the examples of external circuit these examples of transceiver connection in this chapter are for reference only, therefore proper operation is not guaranteed with these circuit examples. if system countermeasures are required for external surges and esd nois e, use a protective diode, etc.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 691 of 1036 rej09b0254-0600 section 23 usb function controller 23.1 features ? incorporates udc (usb device controller) conforming to usb1.1 automatic processing of usb protocol automatic processing of usb standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) ? transfer speed: full-speed ? endpoint configuration endpoint name abbreviation transfer type maximum packet size fifo buffer capacity dma transfer endpoint 0 ep0s setup 8 8 ? ep0i control-in 8 8 ? ep0o control-out 8 8 ? endpoint 1 ep1 bulk-out 64 128 possible endpoint 2 ep2 bulk-in 64 128 possible endpoint 3 ep3 interrupt 8 8 ? configuration 1 ? interface 0 ? alternate setting 0 end point 1 end point 2 end point 3 ? interrupt requests: generates various interrupt signals necessary for usb transmission/reception ? clock: selection by means of excpg for details, see section 11, extend cloc k pulse generator for usb (excpg). ? power-down mode power consumption can be reduced by stopping internal clock when udc cable is disconnected automatic transition to/recovery from suspend state ? can be connected to a philips pdiusbp11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand) ? this usb function controller is a self-power device. it cannot operate by power supplied from the usb cable.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 692 of 1036 rej09b0254-0600 23.2 block diagram status and control registers internal peripheral bus udc: usb device controller fifo (288 bytes) interrupt requests dma transfer requests clock (48 mhz) udc usb function module to transceive r figure 23.1 block diagram of ubc 23.3 pin configuration table 23.1 pin configuration and functions pin name i/o function usbf_vbus input usb cable connection monitor pin usb1_pwr_en output usb1 power control pin can be connected to a philips pdiusbp11 series tr ansceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand). see section 22, usb pin multiplex controller, for connection to the usb transceiver.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 693 of 1036 rej09b0254-0600 23.4 register configuration table 23.2 usb function module registers name abbreviation r/w initial value address access size usbep0i data register usbepdr0i w ? h'04000242 (h'a4000242) * 8 usbep0o data register usbepdr0o r ? h'04000243 (h'a4000243) * 8 usbep0s data register usbepdr0s r ? h'04000247 (h'a400247) * 8 usbep1 data register usbepdr1 r ? h'0400024e (h'a400024e) * 8 usbep2 data register usbepdr2 w ? h'04000249 (h'a4000249) * 8 usbep3 data register usbepdr3 w ? h'04000252 (h'a4000252) * 8 interrupt flag register 0 usbifr0 r/w h'10 h'04000240 (h'a4000240) * 8 interrupt flag register 1 usbifr1 r/w h'00 h'04000241 (h'a4000241) * 8 trigger register usbtrg w ? h'04000244 (h'a4000244) * 8 fifo clear register usbfclr w ? h'04000245 (h'a4000245) * 8 usbep0o receive data size register usbepsz0o r h' 00 h'04000246 (h'a4000246) * 8 data status register usbdasts r h'00 h'04000248 (h'a4000248) * 8 endpoint stall register usbepstl r/w h'00 h'0400024b (h'a400024b) * 8 interrupt enable register 0 usbier0 r/w h'00 h'0400024c (h'a400024c) * 8 interrupt enable register 1 usbier1 r/w h'00 h'0400024d (h'a400024d) * 8 usbep1 receive data size register usbepsz1 r h'00 h'0400024f (h'a400024f) * 8 usbdma setting register usbdma r/w h'00 h'04000251 (h'a4000251) * 8
section 23 usb function controller rev.6.00 mar. 27, 2009 page 694 of 1036 rej09b0254-0600 name abbreviation r/w initial value address access size interrupt select register 0 usbisr0 r/w h'00 h'0400024a (h'a400024a) * 8 interrupt select register 1 usbisr1 r/w h'07 h'04000250 (h'a4000250) * 8 note: * if the mmu does not convert addresses, use addresses in parentheses. 23.5 register descriptions 23.5.1 usbep0i data register (usbepdr0i) usbepdr0i is an 8-byte fifo buffer for endpoint 0, holding one packet of transmit data for control-in. transmit data is fixed by writing one pa cket of data and setting bit 0 in the usb trigger register. when an ack handshake is returned from the host after the data has been transmitted, ep0i ts in usb interrupt flag register 0 is set. this fifo buffer can be initialized by means of ep0i clr in the usbfifo clear register. 23.5.2 usbep0o data register (usbepdr0o) usbepdr0o is an 8-byte receive fifo buffer for endpoint 0. usbepdr0o holds endpoint 0 receive data other than setup commands. when da ta is received norma lly, ep0o ts in usb interrupt flag register 0 is set, and the number of receive bytes is indicated in the ep0o receive data size register. after the data has been read, setting ep0o rdfn in the usb trigger register enables the next packet to be received. this fi fo buffer can be initialized by means of ep0o clr in the usbfifo clear register. 23.5.3 usbep0s data register (usbepdr0s) usbepdr0s is an 8-byte fifo buffer specifically for endpoint 0 setup command reception. usbepdr0s receives only setup commands requirin g processing on the application side. when command data is received normally, setup ts in usb interrupt flag register 0 is set. as a setup command must be received without fail, if data is left in this buffer, it will be overwritten with new data. if reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly terminated, and the read data is invalid.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 695 of 1036 rej09b0254-0600 23.5.4 usbep1 data register (usbepdr1) usbepdr1 is a 128-byte receive fifo buffer for endpoint 1. usbepdr1 has a dual-fifo configuration, and has a capacity of twice the ma ximum packet size. when one packet of data is received normally from the host, ep1 full in usb in terrupt flag register 0 is set. the number of receive bytes is indicated in the usbep1 receive data size register. after the data has been read, the buffer that was read is enabled to receive ag ain by writing 1 to ep1 rd fn in the usb trigger register. the receive data in this fifo buffer can be transferred by dma (see section 23.5.19, usbdma setting register (usbdmar)). this fifo buffer can be initialized by means of ep1 clr in the usbfifo clear register. 23.5.5 usbep2 data register (usbepdr2) usbepdr2 is a 128-byte transmit fifo buffer for endpoint 2. usbepdr2 has a dual-buffer configuration, and has a capacity of twice the ma ximum packet size. when transmit data is written to this fifo buffer and ep2 pkte in the usb trigger register is set, one packet of transmit data is fixed, and the dual-fifo buffer is switched over. transmit data for this fifo buffer can be transferred by dma (see section 23.5.19, usbd ma setting register (usbdmar)). this fifo buffer can be initialized by means of ep 2 clr in the usbfifo clear register. 23.5.6 usbep3 data register (usbepdr3) usbepdr3 is an 8-byte transmit fifo buffer for endpoint 3, holding one packet of transmit data in endpoint 3 interrupt transfer. transmit data is fixed by writing one packet of data and setting ep3 pkte in the usb trigger register. when an ack handshake is received from the host after one packet of data has been transmitted normally, ep3 ts in the usb interrupt flag register 1 is set. this fifo buffer ca n be initialized by means of ep3 clr in the usb fifo clear register. 23.5.7 usb interrupt flag register 0 (usbifr0) together with usb interrupt flag register 1, usbifr0 indicates interrupt status information required by the application. when an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with usb interrupt enable register 0. clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. however, ep1 full and ep2 empty are status bits, and cannot be cleared.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 696 of 1036 rej09b0254-0600 bit: 7 6 5 4 3 2 1 0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts initial value: 0 0 0 1 0 0 0 0 r/w: r/w r r/w r r/w r/w r/w r/w bit 7?bus reset (brst): set to 1 when the bus reset signal is detected on the usb bus. bit 6?ep1 fifo full (ep1 full): this bit is set when endpoint 1 receives one packet of data normally from the host, and holds a value of 1 as lo ng as there is valid data in the fifo buffer. ep1 full is a status bit, and cannot be cleared. bit 5?ep2 transfer request (ep2 tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 2 is received from the host. a nack handshake is returned to the host until data is written to the fi fo buffer and packet transmission is enabled. bit 4?ep2 fifo empty (ep2 empty): this bit is set when at least one of the dual endpoint 2 transmit fifo buffers is ready for transmit data to be written. ep2 empty is a status bit, and cannot be cleared. bit 3?setup command receive complete (setup ts): this bit is set to 1 when endpoint 0 receives normally a setup command requiring decodi ng on the application side, and returns an ack handshake to the host. bit 2?ep0o receive complete (ep0o ts): this bit is set to 1 when endpoint 0 receives data from the host normally, stores the data in the fifo buffer, and returns an ack handshake to the host. bit 1?ep0i transfer request (ep0i tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 0 is received from the host. a nack handshake is returned to the host until data is written to the fi fo buffer and packet transmission is enabled. bit 0?ep0i transmit complete (ep0i ts): this bit is set when data is transmitted to the host from endpoint 0 and an ack handshake is returned.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 697 of 1036 rej09b0254-0600 23.5.8 usb interrupt flag register 1 (usbifr1) together with usb interrupt flag register 0, usbifr1 indicates interrupt status information required by the application. when an interrupt source occurs, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with usb interrupt enable register 1. clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. bit: 7 6 5 4 3 2 1 0 ? ? ? ? vbusmn ep3 tr ep3 ts vbusf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 7 to 4?reserved: these bits are always read as 0. the write value should always be 0. bit 3?usb connect status (vbusmn): this bit is a status bit for monitoring the state of the usbf_vbus pin. it reflects the state of the usbf_vbus pin. bit 2?ep3 transfer request (ep3 tr): this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 3 is received from the host. a nack handshake is returned to the host until data is written to the fi fo buffer and packet transmission is enabled. bit 1?ep3 transmit complete (ep3 ts): this bit is set when data is transmitted to the host from endpoint 3 and an ack handshake is returned. bit 0?usb bus connect (vbusf): this bit is set to 1 when connecting to or disconnecting from the usb bus. the usbf_vbus pin is used to detect connection/disconnection. the usbf_vbus pin must be connected, as it is needed inside the module.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 698 of 1036 rej09b0254-0600 23.5.9 usb trigger register (usbtrg) usbtrg generates one-shot triggers to contro l the transmit/receive sequence for each endpoint. bit: 7 6 5 4 3 2 1 0 ? ep3 pkte ep1 rdfn ep2 pkte ? ep0s rdfn ep0o rdfn ep0i pkte r/w: w w w w w w w w bit 7?reserved bit 6?ep3 packet enable (ep3 pkte): after one packet of data has been written to the endpoint 3 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit. bit 5?ep1 read complete (ep1 rdfn): write 1 to this bit after one packet of data has been read from the endpoint 1 fifo buffer. the endpoint 1 receive fifo buffer has a dual-fifo configuration. writing 1 to this bit initializes the fifo that was read, enabling the next packet to be received. bit 4?endpoint 2 packet enable (ep2 pkte): after one packet of data has been written to the endpoint 2 fifo buffer, the transmit data is fixed by writing 1 to this bit. bit 3?reserved bit 2?ep0s read complete (ep0s rdfn): write 1 to this bit after ep0s command fifo data has been read. writing 1 to this bit enables tran smission/reception of data in the following data stage. a nack handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit. bit 1?ep0o read complete (ep0o rdfn): writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit fifo buff er initializes the fifo buffer, enabling the next packet to be received. bit 0?ep0i packet enable (ep0i pkte): after one packet of data has been written to the endpoint 0 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 699 of 1036 rej09b0254-0600 23.5.10 usbfifo clear register (usbfclr) usbfclr is provided to initialize the fifo buffers for each endpoint. writing 1 to a bit clears all the data in the corresponding fifo buffer. the co rresponding interrupt flag is not cleared. do not clear a fifo buffer duri ng transmission/reception. bit: 7 6 5 4 3 2 1 0 ? ep3 clr ep1 clr ep2 clr ? ? ep0o clr ep0i clr r/w: w w w w w w w w bit 7?reserved bit 6?ep3 clear (ep3 clr): when 1 is written to this bit, th e endpoint 3 transmit fifo buffer is initialized. bit 5?ep1 clear (ep1 clr): when 1 is written to this bit, bo th fifos in the endpoint 1 receive fifo buffer are initialized. bit 4?ep2 clear (ep2 clr): when 1 is written to this bit, both fifos in the endpoint 2 transmit fifo buffer are initialized. bits 3 and 2?reserved bit 1?ep0o clear (ep0o clr): when 1 is written to this bit, the endpoint 0 receive fifo buffer is initialized. bit 0?ep0i clear (ep0i clr): when 1 is written to this bit, the endpoint 0 transmit fifo buffer is initialized. 23.5.11 usbep0o receive data size register (usbepsz0o) usbepsz0o indicates, in bytes, the amount of data received from the host by endpoint 0.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 700 of 1036 rej09b0254-0600 23.5.12 usb data status register (usbdasts) usbdasts indicates whether the tr ansmit fifo buffers contain valid data. a bit is set when data is written to the corresponding fifo buffer and the pa cket enable state is set, and cleared when all data has been transmitted to the host. bit: 7 6 5 4 3 2 1 0 ? ? ep3 de ep2 de ? ? ? ep0i de initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 7 and 6?reserved: these bits are always read as 0. the write value should always be 0. bit 5?ep3 data present (ep3 de): this bit is set when the endpoint 3 fifo buffer contains valid data. bit 4?ep2 data present (ep2 de): this bit is set when the endpoint 2 fifo buffer contains valid data. bits 3 to 1?reserved: these bits are always read as 0. the write value should always be 0. bit 0?ep0i data present (ep0i de): this bit is set when the endpoint 0 fifo buffer contains valid data. 23.5.13 usb endpoint stall register (usbepstl) the bits in usbepstl are used to forcibly stall the endpoints on the application side. while a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. the stall bit for endpoint 0 (ep0 stl) is cleared automatically on reception of 8-bit command data for which decoding is performed by the function. when the se tupts flag in usb interrupt flag register 0 is set, a write of 1 to the ep0 stl bit is ignored. for details see section 23.8, stall operations. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ep3 stl ep2 stl ep1 stl ep0 stl initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w bits 7 to 4?reserved: these bits are always read as 0. the write value should always be 0.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 701 of 1036 rej09b0254-0600 bit 3?ep3 stall (ep3 stl): when this bit is set to 1, endpoi nt 3 is placed in the stall state. bit 2?ep2 stall (ep2 stl): when this bit is set to 1, endpoi nt 2 is placed in the stall state. bit 1?ep1 stall (ep1 stl): when this bit is set to 1, endpoi nt 1 is placed in the stall state. bit 0?ep0 stall (ep0 stl): when this bit is set to 1, endpoi nt 0 is placed in the stall state. 23.5.14 usb interrupt enable register 0 (usbier0) usbier0 enables the interrupt requests indicated in usb interrupt flag register 0 (usbifr0). when an interrupt flag is set while the corresp onding bit in usbier0 is set to 1, an interrupt request is sent to the cpu. the contents of the interrupt event register (intevt2) are determined by the contents of usb interrupt select register 0 (usbisr0). bit: 7 6 5 4 3 2 1 0 brst ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 23.5.15 usb interrupt enable register 1 (usbier1) usbier1 enables the interrupt requests indicated in usb interrupt flag register 1 (usbifr1). when an interrupt flag is set while the corresp onding bit in usbier1 is set to 1, an interrupt request is sent to the cpu. the contents of the interrupt event register (intevt2) are determined by the contents of usb interrupt select register 1 (usbisr1). bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ep3 tr ep3 ts vbusf initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w 23.5.16 usbep1 receive data size register (usbepsz1) usbepsz1 is the endpoint 1 receive data size re gister, indicating the am ount of data received from the host. the endpoint 1 fifo buffer has a dual-fifo configuration; the receive data size indicated by this register refers to the currently selected fifo.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 702 of 1036 rej09b0254-0600 23.5.17 usb interrupt sel ect register 0 (usbisr0) usbisr0 selects the interrupt event register (intevt2) codes of the interrupt requests indicated in usb interrupt flag register 0. if the usb i ssues an interrupt request to the intc when the corresponding bit in usbisr0 is cleared to 0, the interrupt will be usbfi0 (usb function interrupt 0), with an interrupt event register (intevt2) code of h'a20. if the usb issues an interrupt request to the intc when the correspondin g bit in usbisr0 is set to 1, the interrupt will be usbfi1 (usb function interrupt 1), with an interrupt event register (intevt2) code of h'a40. the initial value designates an interrupt event register (intevt2) code of h'a20. if interrupts occur simultaneously, usbfi0 has priority by default. for details on the interrupt event register (intevt2), refer to section 4, excep tion handling, and section 7, interrupt controller (intc). bit: 7 6 5 4 3 2 1 0 bsrt ep1 full ep2 tr ep2 empty setup ts ep0o ts ep0i tr ep0i ts initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 23.5.18 usb interrupt sel ect register 1 (usbisr1) usbisr1 selects the interrupt event register (intevt2) codes of the interrupt requests indicated in usb interrupt flag register 1. if the usb i ssues an interrupt request to the intc when the corresponding bit in usbisr1 is cleared to 0, the interrupt will be usbfi0 (usb function interrupt 0), with an interrupt event register (intevt2) code of h'a20. if the usb issues an interrupt request to the intc when the correspondin g bit in usbisr1 is set to 1, the interrupt will be usbfi1 (usb function interrupt 1), with an interrupt event register (intevt2) code of h'a40. the initial value designates an interrupt event register (intevt2) code of h'a20. if interrupts occur simultaneously, usbfi0 has priority by default. for details on the interrupt event register (intevt2), refer to section 4, excep tion handling, and section 7, interrupt controller (intc). bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ep3 tr ep3 ts vbus initial value: 0 0 0 0 0 1 1 1 r/w: r r r r r r/w r/w r/w
section 23 usb function controller rev.6.00 mar. 27, 2009 page 703 of 1036 rej09b0254-0600 23.5.19 usbdma setting register (usbdmar) dma transfer can be carried out between the endpoint 1 and endpoint 2 data registers by means of the on-chip dma controller. dual a ddress transfer is performed, using byte transfer units. in order to start dma transfer, dma control settings must be made in addition to the settings in this register. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? pullup_ e ep2 dmae ep1 dmae initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bits 7 to 3?reserved: these bits are always read as 0. the write value should always be 0. bit 2?pull-up enable (pullup_e): this bit is for controlling connection notification (d + pull-up) to the usb host/hub. this bit enables th e level of the usb1_pwr_en pin to be controlled. writing 1 outputs the high level and 0 outputs the low level. for more information on the d + pull-up control, see section 22, usb pin multiplex controller. bit 1?endpoint 2 dma transfer enable (ep2 dmae): when this bit is set, dma transfer is enabled from memory to the endpoin t 2 transmit fifo buffer. if there is at least one byte of space in the fifo buffer, the transfer request signal to the dma controller is asserted. when 64 bytes are written to the fifo buffer in dma transfer, ep2 packet enabling is set automatically, and 64- byte data can be transferred. if there is a space in another fifo, a transfer request is asserted for the dma controller again. however, since ep2 packet enable is not set automatically if data packet size for transfer is less than 64 bytes, set ep2 packet enabling by the cpu with a dma transfer end interrupt. since ep2-related interrupt requests to the cpu are not masked automatically, interrupt requests must also be masked as necessary in the interrupt enable register. bit 0?endpoint 1 dma transfer enable (ep1 dmae): when this bit is set, dma transfer can be performed from the endpoint 1 receive fifo bu ffer to memory. if there is at least one byte of space in the fifo buffer, the transfer request signal to the dma controller is asserted. when all received data is read in dma transfer, the ep1 read-end trigger is performed automatically. ep1-related interrupt requests to the cpu are not masked automatically.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 704 of 1036 rej09b0254-0600 23.6 operation 23.6.1 cable connection cable disconnection vbus pin = 0 v udc core reset in progress connect usb cable usbf_vbus pin = 1 (usbifr1/vbusmn = 1) usbifr1/vbusf = 1 usb bus connection interrupt clear udc core reset bus reset usbifr0/brst = 1 bus reset interrupt wait receive-end interrupt of set-up command usb function application clear vbus flag (usbifr1/vbusf) prepare firmware since usb communication starts clear bus reset flag (usbifr0/brst) clear fifos (ep0, ep1, ep2, ep3) wait receive-end interrupt of set-up command interrupt request interrupt request figure 23.2 cable connection operation the above flowchart shows the operation in cable connection. when a usb connection interrupt occurs, connection can be detected by confirming the status of the usbf_vbus pin. processing by a usb bus connection interrupt is unnecessary for applications in which usb cable connection is not required to be detected. prepare processing by a bus reset interrupt.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 705 of 1036 rej09b0254-0600 23.6.2 cable disconnection usb function application cable connection state vbus pin = 1 disconnect usb cable usbf_vbus pin = 0 (usbifr/vbusmn = 0) usbifr1/vbusf = 1 usb bus connection interrupt reset udc core end clear vbusf flag (usbifr/vbusf) interrupt request figure 23.3 cable disconnection operation the above flowchart shows the operation in cable disconnection. when a usb bus connection interrupt occurs, disconnection can be detected by confirming the status of the usbf_vbus pin.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 706 of 1036 rej09b0254-0600 23.6.3 control transfer control transfer consists of three stages of setup, data (that may not be included), and status (figure 23.4). the data stage consists of multiple bus transactions. the operating flowchart of each stage is shown below. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 23.4 transfer st age for control transfer
section 23 usb function controller rev.6.00 mar. 27, 2009 page 707 of 1036 rej09b0254-0600 (1) setup stage usb function application setup token reception receive 8-byte command data in ep0s to data stage set receive-end flag of setup command (usbifr0/setup ts = 1) automatic processing by this module clear setup ts flag (usbifr0/setup ts = 0) clear ep0i fifo (usbfclr/ep0iclr = 1) clear ep0o fifo (usbfclr/ep0oclr = 1) read 8-byte data from ep0s decode command data decide data stage direction * 1 write 1 to ep0s read-end bit (usbtrg/ep0s rdfn = 1) to control-in data stage to control-out data stage command to be processed by application? interrupt request yes no notes: 1. the application analyzes command data from the host that must be processed by the application in the setup stage, and decides the following processing methods (for instance, data stage direction). 2. when the transfer direction is control-out, enable an ep0i transfer request interrupt that is required in the status stage. when the transfer direction is control-in, disable the interrupt since it is not used. * 2 figure 23.5 setup stage operation
section 23 usb function controller rev.6.00 mar. 27, 2009 page 708 of 1036 rej09b0254-0600 (2) data stage (control-in) usb function application in token reception data transmission to host from setup stage write data to usbep0i data register (usbepdr0i) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) clear ep0i transfer-end flag (usbifr0/ep0i ts = 0) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) write data to usbep0i data register (usbepdr0i) 1 written to usbtrg/ep0s rdfn? valid data in ep0i fifo? nack nack no no yes yes ack interrupt request set ep0i transfer-end flag to 1 (usbifr0/ep0i ts = 1) figure 23.6 data stag e operation (control-in)
section 23 usb function controller rev.6.00 mar. 27, 2009 page 709 of 1036 rej09b0254-0600 the application analyzes command data from the ho st in the setup stage and decides the following data stage direction. as a result of command data analysis, when the data stage is in-transfer, one- packet data to be sent to the host is written to fifo . if there is more data to be sent to the host, after data written first is sent to the host (u sbifr0/ep0i ts = 1), da ta is written to fifo. the end of the data stage is decided by transferring out-token by the host and entering the status stage. note: when the size of data transferred from the function is smaller than the size of data requested from the host, the function indicates data stage end by returning a packet smaller than the maximum packet to the host. when th e size of data transferred from the function is integer times larger than the maximum pack et size, a 0-length packet is transferred and the data stage end is indicated.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 710 of 1036 rej09b0254-0600 (3) data stage (control-out) usb function application out token reception data reception from host out token reception set ep0o receive-end flag to 1 (usbifr0/ep0o ts = 1) clear ep0o receive-end flag (usbifr0/ep0o ts = 0) read data from usbep0o data size register (usbepsz0o) write 1 to ep0o read-end bit (usbtrg/ep0o rdfn = 1) read data from usbep0o data register (usbepdr0o) 1 written to usbtrg/ep0s rdfn? 1 written to usbtrg/ep0o rdfn? nack nack ack no yes no yes interrupt request figure 23.7 data stage operation (control-out) the application analyzes command data from the ho st in the setup stage and decides the following data stage direction. as a result of command data analysis, when the data stage is out-transfer, data from the host is waited. after data rece ption (usbifr0/ep0o ts = 1), data is read from fifo. applications then write 1 to the ep0o read -end bit, make reception fifo empty, and wait for the next data reception. the end of the data stage is decided by transferring in-token by the host and entering the status stage.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 711 of 1036 rej09b0254-0600 (4) status stage (control-in) usb function application out token reception 0-byte reception from host end of control transfer set ep0o reception complete flag (ifr0.ep0o ts = 1) clear ep0o reception complete flag (ifr0.ep0o ts = 0) write 1 to ep0o read complete bit (trg.ep0o rdfn = 1) end of control transfer ack interrupt request figure 23.8 status stag e operation (control-in) the status stage in control-in st arts with out-token from the host. the application receives 0-byte data from the host and completes control transfer.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 712 of 1036 rej09b0254-0600 (5) status stage (control-out) usb function application in token reception 0-byte transmission to host end of control transfer clear ep0i transfer-request flag (usbifr0/ep0i tr = 0) write 1 to ep0i packet enable bit (usbtrg/ep0i pkte = 1) clear ep0i transfer-end flag (usbifr0/ep0i ts = 0) end of control transfer ack yes no nack interrupt request interrupt request set ep0i transfer-end flag (usbifr0/ep0i ts = 1) valid data in ep0i fifo? figure 23.9 status stag e operation (control-out) the status stage in control-out st arts with in-token from the host. in in-token reception at the start of status stage, an ep0o transfer-request interrup t occurs since no data is in ep0i fifo. the application acknowledges that the status stage has st arted by the interrupt. to transfer 0-byte data to the host, no data is written to the ep0i fifo, and 1 is written to the ep0i packet-enable bit. therefore, 0-byte data is transfer red to the host in the next in-token, and control transfer is completed. however, after the application completes all proces sing related to the data stage, write 1 to the ep0i packet-enable bit.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 713 of 1036 rej09b0254-0600 23.6.4 ep1 bulk-out transfer (dual fifos) usb function application out token reception data reception from host usbifr0/ep1 full status bit automatically cleared to 0 read usbep1 receive-data size register (usbepsz1) read data from usbep1 data register (usbepdr1) write 1 to ep1 read-end bit (usbtrg/ep1 rdfn = 1) space in ep1 fifo? no yes no yes nack ack interrupt request interrupt request both fifos are empty? usbifr0/ep1 full status bit automatically set to 1 figure 23.10 ep1 bulk-out transfer operation ep1 has two 64-byte fifos, but the user can perform data reception and receive-data reads without being aware of this dual-fifo configuration. when one fifo is full after recep tion is completed, the usbifr0/ ep1 full bit is set. after the first receive operation into one of the fifos when both fifos are em pty, the other fifo is empty, and so the next packet can be received immediatel y. when both fifos are fu ll, nack is returned
section 23 usb function controller rev.6.00 mar. 27, 2009 page 714 of 1036 rej09b0254-0600 to the host automatically. when r eading of the receive data is co mpleted following data reception, 1 is written to the usbtrg/ep1 rdfn bit. this operation empties the fifo that has just been read, and makes it ready to receive the next packet. 23.6.5 ep2 bulk-in transfer (dual fifos) usb function application in token reception data transmission to host usbifr0/ep2 tr interrupt write 1 to usbier0/ep2 empty enable bit usbifr0/ep2 empty interrupt write one-packet data to usbep2 data register write 1 to ep2 packet enable bit (usbtrg/ep2 pkte = 1) valid data in ep2 fifo? nack ack yes no usbifr0/ep2 empty status bit automatically cleared to 0 no yes interrupt request usbifr0/ep2 empty status bit automatically set 1 space in ep2 fifo? figure 23.11 ep2 bulk-in transfer operation
section 23 usb function controller rev.6.00 mar. 27, 2009 page 715 of 1036 rej09b0254-0600 ep2 has two 64-byte fifos, but the user can perform data transmission and transmit-data writes without being aware of this dual-f ifo configuration. write data to one fifo at one time. for instance, even if two fifos are empty, ep2/pk te cannot be performed after writing 128-byte data continuously. perform ep2/pkte in every 64-byte write. to perform bulk-in transfer, since there is no valid data in fifo in the first in-token, a usbifr0/ep2 tr interrupt is requested. by th e interrupt, write 1 to the usbier0/ep2 empty bit and enable the ep2 fifo empty interrupt. since the two ep2 fifos are empty first, the ep2 fifo empty interrupt is generated immediately. the data to be transmitted is written to the data register using this interrupt. after the first transmit data write, the other fifo is empty, and so the next transmit data can be written immediately. when both fifos are full, ep2 empty is cleared to 0. if at least one fifo is empty, usbifr0/ep2 empty is set to 1. when ack is returned from the host after data transmission is completed, the fifo used in the data transmission becomes empty. if the other fifo contains valid transmit data at this time, transmission is continued. when transmission of all data has been completed, write 0 to usbifr0/ep2 empty and disable interrupt requests.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 716 of 1036 rej09b0254-0600 23.6.6 ep3 int errupt-in transfer usb function application in token reception data transmission to host in token reception clear ep3 transfer-request flag (usbifr1/ep3 tr = 0) write data to usbep3 data register write to ep3 packet enable bit (usbtrg/ep3 pkte = 1) clear ep3 transfer-end flag (usbifr1/ep3 ts = 0) write data to usbep3 data register write to ep3 packet enable bit (usbtrg/ep3 pkte = 1) valid data in ep3 fifo? no yes nack ack note: this flow is an example of interrupt transfer processing. when there is data to be transferred, the following flow can also be considered. "confirm that fifo is empty by referring to the ep3 de bit of the usb data status register and write data to fifo." set ep3 transfer-end flag (usbifr1/ep3 ts = 1) figure 23.12 ep2 interrupt-in transfer operation
section 23 usb function controller rev.6.00 mar. 27, 2009 page 717 of 1036 rej09b0254-0600 23.7 processing of usb standa rd commands and class/vendor commands 23.7.1 processing of commands transmitted by control transfer a command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. whether command decoding is required on the application side is indicated in table 23.3 below. table 23.3 command decodi ng on application side decoding not necessary on application side decoding necessary on application side clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor sync frame set descriptor class/vendor command if decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. no processing is necessary by the user. an interrupt is not generated in this case. if decoding is necessary on the application side, the usb function module stores the command in the ep0s fifo. after normal reception is comple ted, the usbier0/setup ts flag is set and an interrupt request is generated. in the interrupt routine, 8 bytes of data must be read from the ep0s data register (usbepdr0s) and decoded by firmware . the necessary data stage and status stage processing should then be carried out accordi ng to the result of the decoding operation.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 718 of 1036 rej09b0254-0600 23.8 stall operations 23.8.1 overview this section describes stall operations in the usb function module. there are two cases in which the usb function module stall function is used: ? when the application forcibly sta lls an endpoint for some reason ? when a stall is performed automatically within the usb function module due to a usb specification violation the usb function module has internal status bits that hold the status (stall or non-stall) of each endpoint. when a transaction is se nt from the host, the module refere nces these internal status bits and determines whether to return a stall to th e host. these bits ca nnot be cleared by the application; they must be cleared with a clear feature command from the host. 23.8.2 forcible stall by application the application uses the usbepstl register to issue a stall request for the usb function module. when the application wishes to stall a specific endpoint, it sets the corresponding bit in usbepstl (1-1 in figure 23.13). the internal stat us bits are not changed. when a transaction is sent from the host for the endpoint for which the usbepstl bit was set, the usb function module references the internal status bit, and if this is not set, references the corresponding bit in usbepstl (1-2 in figure 23.13). if the correspo nding bit in usbepstl is set, the usb function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 23.13). if the corresponding bit in usbepstl is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains se t until cleared by a clear feature command from the host, without regard to the usbepstl register. ev en after a bit is cleared by the clear feature command (3-1 in figure 23.13), the usb function module continues to return a stall handshake while the bit in usbepstl is set, since the intern al status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figu re 23.13). to clear a st all, therefore, it is necessary for the corresponding bit in usbepstl to be cleared by the application, and also for the internal status bit to be cleared with a cl ear feature command (2-1, 2-2, and 2-3 in figure 23.13).
section 23 usb function controller rev.6.00 mar. 27, 2009 page 719 of 1036 rej09b0254-0600 (1) transition from normal operation to stall (1-1) transaction request usb reference (1-2) stall handshake stall to (2-1) or (3-1) normal status restored (1-3) (2) when clear feature is sent after usbepstl is cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before usbepstl is cleared to 0 (3-1) 1. 1 written to usbepstl by application 1. in/out token received from host 2. usbepstl referenced 1. transmission of stall handshake 1. internal status bit cleared to 0 1. internal status bit cleared to 0 2. usbepstl not changed 1. 1 set in usbepstl 2. internal status bit set to 1 3. transmission of stall handshake 1. usbepstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. usbepstl not referenced 5. internal status bit not changed to (1-2) internal status bit 0 usbepstl 0 1 internal status bit 0 usbepstl 1 internal status bit 0 1 usbepstl 1 internal status bit 1 usbepstl 1 0 internal status bit 1 usbepstl 0 internal status bit 1 0 usbepstl 0 internal status bit 1 0 usbepstl 1 figure 23.13 forcible stall by application
section 23 usb function controller rev.6.00 mar. 27, 2009 page 720 of 1036 rej09b0254-0600 23.8.3 automatic stall by usb function module when a stall setting is made with the set feature command, or in the event of a usb specification violation, the usb function module automatically sets the internal status bit for the relevant endpoint without regard to the usbepstl register, and returns a stall handshake (1-1 in figure 23.14). once an internal status bit is set, it remains se t until cleared by a clear feature command from the host, without regard to the usbepstl register. after a bit is cleared by the clear feature command, usbepstl is referenced (3-1 in figure 23.14). the usb function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 23.14). to clear a stall, therefore, the internal status bit must be cleared with a clear featur e command (3-1 in figure 23.14). if set by the application, usbepstl should also be cleared (2-1 in figure 23.14).
section 23 usb function controller rev.6.00 mar. 27, 2009 page 721 of 1036 rej09b0254-0600 (1) transition from normal operation to stall (1-1) (2) when clear feature is sent after usbepstl is cleared (2-1) stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before usbepstl is cleared to 0 (3-1) 1. in case of usb specification violation, etc., usb function module stalls endpoint automatically 1. transmission of stall handshake 1. internal status bit cleared to 0 2. usbepstl not changed 1. usbepstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. usbepstl not referenced 5. internal status bit not changed normal status restored internal status bit 0 1 usbepstl 0 internal status bit 1 usbepstl 0 internal status bit 1 usbepstl 0 internal status bit 1 0 usbepstl 0 stall status maintained to (2-1) or (3-1) figure 23.14 automatic stall by usb function module
section 23 usb function controller rev.6.00 mar. 27, 2009 page 722 of 1036 rej09b0254-0600 23.9 usage notes 23.9.1 receiving setup data note the following for epdr0s th at receives 8-byte setup data: 1. as a latest setup command must be received in high priority, the write from the usb bus takes priority over the read from the cpu. if the ne xt setup command reception is started while the cpu is reading data after the data is received, the read from the cpu is forcibly terminated. therefore, the data read after r eception is started becomes invalid. 2. epdr0s must always be read in 8-byte units. if the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 23.9.2 clearing the fifo if a usb cable is disconnected during data tran sfer, the data being received or transmitted may remain in the fifo. when disconn ecting a usb cable, clear the fifo. while a fifo is transferring data, it must not be cleared. 23.9.3 overreading and overwri ting the data registers note the following when reading or writing to a data register of this module. (1) receive data registers the receive data registers must not be read exceed ing the valid amount of receive data, that is, the number of bytes indicated by th e receive data size register. ev en for epdr1 which has double fifo buffers, the maximum data to be read at one ti me is 64 bytes. after the data is read from the current valid fifo buffer, be sure to write 1 to ep1rdfn in trg, which switches the valid buffer, updates the receive data size to the new num ber of bytes, and enables the next data to be received. (2) transmit data registers the transmit data registers must not be written to exceeding the maximum packet size. even for epdr2 which has double fifo buffers, write data within the maximum packet size at one time. after the data is written, write 1 to pkte in tr g to switch the valid buffer and enable the next data to be written. data must not be con tinuously written to th e two fifo buffers.
section 23 usb function controller rev.6.00 mar. 27, 2009 page 723 of 1036 rej09b0254-0600 23.9.4 assigning inte rrupt sources to ep0 the ep0-related interrupt sources indicated by the in terrupt source bits (bits 0 to 3) in ifr0 must be assigned to the same interrupt signal with isr0. the other interrupt sources have no limitations. 23.9.5 clearing the fifo wh en dma transfer is enabled the endpoint 1 data register (epdr1) cannot be cleared when dma transfer for endpoint 1 is enabled (ep1 dmae in usbdma = 1). cancel dma transfer before clearing the register. 23.9.6 notes on tr interrupt note the following when using the transfer request interrupt (tr inte rrupt) for in transfer to ep0i, ep2, or ep3. the tr interrupt flag is set if the fifo for the target ep has no data when the in token is sent from the usb host. however, at the timing shown in figure 23.15, multiple tr interrupts occur successively. take appropriate measures against malfunction in such a case. note: this module determines whether to return nak if the fifo of the target ep has no data when receiving the in token, but the tr inte rrupt flag is set only after a nak handshake is sent. if the next in token is sent before pkte of trg is written to, the tr interrupt flag is set again. cpu host in token in token in token sets tr flag (sets the flag again) sets tr flag determines whether to return nak transmits data tr interrupt routine clear tr flag writes transmit data trg. pkte tr interrupt routine usb nak determines whether to return nak nak ack figure 23.15 tr int errupt flag set timing
section 23 usb function controller rev.6.00 mar. 27, 2009 page 724 of 1036 rej09b0254-0600 23.9.7 peripheral clock (p ) operation frequency the peripheral clock frequency (p ) should be 13 mhz or above when using this module.
section 24 usb host module rev.6.00 mar. 27, 2009 page 725 of 1036 rej09b0254-0600 section 24 usb host module 24.1 general description the usb host controller module incorporated in SH7727 supports open host controller (open hci) specification for the universal serial bu s (usb) as well as the universal serial bus specification ver.1.1. the open hci specification for the usb is a regist er-level description of host controller for the usb which in turn is described by the usb specification. it is necessary to refer open hci specification to develop drivers for this usb host controller and hardware. also refer to the restrictions on the use of the module listed at the end of this section. 24.1.1 features ? support open hci standard ver.1.0 register set ? support universal serial bus standard ver.1.1 ? root hub function ? support full speed (12mbps) mode and low speed (1.5mbps) mode ? support overcurrent detection ? support 127 endpoints control in maximum ? the whole area of the synchronous dram in area 3 connected to the cpu can be used for transfer data and descriptor.
section 24 usb host module rev.6.00 mar. 27, 2009 page 726 of 1036 rej09b0254-0600 24.1.2 pin configuration pin configuration of the usb host controller is shown in table 24.1. for the detailed method for setting each pin, s ee section 22, usb pin multiplex controller. table 24.1 pin configuration pin name symbol i/o function power enable pin 1 usb1_pwr_en output usb port 1 power enable control power enable pin 2 usb2_pwr_en output usb port 2 power enable control over-current pin 1/ vbus pin usb1_ovr_current / usbf_vbus input usb port 1 over-current detect/ usb cable connection monitor pin over-current pin 2 usb2_ovr_current input usb port 2 over-current detect 1p pin usb1_p i/o d + port 1 transceiver pin 1m pin usb1_m i/o d ? port 1 transceiver pin 2p pin usb2_p i/o d + port 2 transceiver pin 2m pin usb2_m i/o d ? port 2 transceiver pin
section 24 usb host module rev.6.00 mar. 27, 2009 page 727 of 1036 rej09b0254-0600 24.1.3 register configuration table 24.2 register configuration register name symbol r/w initial value address access size hcrevision ? r h'00000010 h'04000400 32 hccontrol ? r/w h'00000000 h'04000404 32 hccommandstatus ? r/w h'00000000 h'04000408 32 hcinterruptstatus ? r/w h'00000000 h'0400040c 32 hcinterruptenable ? r/w h'00000000 h'04000410 32 hcinterruptdisable ? r/w h'00000000 h'04000414 32 hchcca ? r/w h'00000000 h'04000418 32 hcperiodcurrente ? r/w h'00000000 h'0400041c 32 hccontrolheaded ? r/w h'00000000 h'04000420 32 hccontrolcurrented ? r/w h'00000000 h'04000424 32 hcbulkheaded ? r/w h'00000000 h'04000428 32 hcbulkcurrented ? r/w h'00000000 h'0400042c 32 hcdonrheaded ? r/w h'00000000 h'04000430 32 hcfminterval ? r/w h'00002edf h'04000434 32 hcfmremaining ? r h'00000000 h'04000438 32 hcfmnumber ? r h'00000000 h'0400043c 32 hcperiodicstart ? r/w h'00000000 h'04000440 32 hclsthreshold ? r/w h'00000628 h'04000444 32 hcrhdescriptora ? r/w h'02001202 h'04000448 32 hcrhdescriptorb ? r/w h'00000000 h'0400044c 32 hcrhstatus ? r/w h'00000000 h'04000450 32 hcrhportstatus1 ? r/w h'00000100 h'04000454 32 hcrhportstatus2 ? r/w h'00000100 h'04000458 32
section 24 usb host module rev.6.00 mar. 27, 2009 page 728 of 1036 rej09b0254-0600 24.2 register description 24.2.1 hcrevision hcrevision register (h'04000400) register: hcrevision offset: 00?03 bits reset r/w description 31?8 0h ? reserved. 7?0 10h r revision (rev) these read only bits include the bcd expression of the hci specification version implement ed for the host controller. the value h'10 corresponds to version 1.0. all hci implementation complying to this specificat ion have the value of h'10.
section 24 usb host module rev.6.00 mar. 27, 2009 page 729 of 1036 rej09b0254-0600 24.2.2 hccontrol hccontrol register (h'04000404) the hccontrol register defines the operation mode for the host controller. most of bits of this register are amended only by the host controller driver other than hostcontroller function state and remote wakeup command. register: hccontrol offset: 04?07 bits reset r/w description 31?11 0h ? reserved. read/write 0's 10 0b r/w remotewakeupenable (rwe) this bit is used by hcd to enable/disable the remote wakeup function at the same time as the detection of an upstream resume signal. this function is not supported. be sure to write 0. 9 0b r/w remotewakeupconnected (rwc) this bit indicates whether the host controller supports a remote wakeup signal or not. when the remote wakeup is supported and used in the system, the host controller must set this bit between post in the system firmware. the host controller clears the bit at the same time of the hardware reset, however, does not change at the same time as the software reset. the remote wakeup signal to the system of the host is specific for the host bus, so it is not described in this specification. 0: remote wakeup signal is not supported. (initial value) 1: remote wakeup signal is supported. 8 0b r/w interruptrouting (ir) this bit determines the routing of interrupts generated by the event registered in hcinterruptstatus. hcd clears this bit at the same time as the hardware reset, however, does not clear at the same time as the software reset. hcd uses this bit as a tag to indicate the ownership of the host controller. 0: all interrupts are routed to normal bus interrupt mechanism. (initial value) 1: interrupts are routed to smi.
section 24 usb host module rev.6.00 mar. 27, 2009 page 730 of 1036 rej09b0254-0600 register: hccontrol offset: 04?07 bits reset r/w description 7, 6 00b r/w hostcontrollerfunctionalstate (hcfs) hcd determines whether the host cont roller has started to route sof after having read the startofframe bit of hcinterruptstatus. this bit can be changed by the host controller only in the usbsusp end state. the host controller can move from the usbsuspend state to the usbresume state after having detected the resume signal from the downstream port. in the host controller, usbsuspend is entered after the software reset so that usbreset is entered after the hardware reset. the former resets the route hub. 00: usb reset 01: usb resume 10: usb operation 11: usb suspend 5 0b r/w bulklistenable (ble) this bit is set to enable the processing of the bulk list in the next frame. the host controller checks this bit when the processing of the list has been determined. when disabling, hcd can correct the list. when hcbulkcurrented indicates ed to be deleted, hcd should hasten the pointer by updating hcbulkcurrented before re-e nabling the list processing. 0: bulk list processing is not carried out. (initial value) 1: bulk list processi ng is carried out. 4 0b r/w controllistenable (cle) this bit is set to enable the processing of the control list in the next frame. if cleared by hcd, t he processing of the control list is not carried out after next slf. the host controller must check this bit whenever the list will be processed. when disabling, hcd can correct the list. when hccontrolcurrented indicates ed to be deleted, hcd should hasten the pointer by updating hcbulk before re-enabling the list processing. 0: control list processing is not carried out. (initial value) 1: control list processing is carried out.
section 24 usb host module rev.6.00 mar. 27, 2009 page 731 of 1036 rej09b0254-0600 register: hccontrol offset: 04?07 bits reset r/w description 3 0b r/w isochronousenable (ie) this bit is used by hcd to enable/disable the processing of isochronous ed. while processing the periodic list, hc will check the status of this bit when it finds an isochronous ed (f =1). if set (enabled), the host c ontroller continues to process ed. if cleared (disabled), the host controller stops the processing of the periodic list (currently includes only isochronous ed) and starts to process the bulk/control list. setting this bit is guaranteed to be valid in the next frame (not in the current frame). 0: processes ed. (initial value) 1: processes the bulk/control list. 2 0b r/w periodiclistenable (ple) this bit is set to enable the processing of the periodic list. if cleared by hcd, no periodic list processing is carried out after next sof. hc must check this bit before hc starts to process the list. 0: the periodic list processing is not carried out after next sof. (initial value) 1: the periodic list processing is carried out after next sof. 1, 0 00b r/w controlbulkserviceratio (cbsr) this bit specifies the service ra tion of the control and bulk ed. the host controller must compar e the ratio specified by the internal calculation whether it has processed several non- vacant control ed in determining whether another control ed is continued to be supplied or switched to bulk ed before any a periodic list is processed. in case of reset, hcd is responsible for restoring this value. 00: 1:1 (initial value) 01: 2:1 10: 3:1 11: 4:1
section 24 usb host module rev.6.00 mar. 27, 2009 page 732 of 1036 rej09b0254-0600 24.2.3 hccommandstatus hccommandstatus register (h'04000408) the hccommandstatus register is used by the host controller not only for reflecting the current status of the host controller, but also for receiving a co mmand issued by the host controller driver. a write is for setting the host controller driver. the host controller must guarantee that the bit to which 1 is written to is set and the bit to whic h 0 is written to is unchanged. the host controller driver must distribute multiple clear commands to the host controller by a previously issued command. the host controller driver can read all bits normally. the schedulingoverruncount bit indicates the number of the frame that has detected the scheduling overrun error by the host controller. this occurs when the periodic list has not completed before eof. when the scheduling overrun error is detected, the host controller increments the counter and se ts schedulingoverrun in the hcinterruptstatus register. register: hccommandstatus offset: 08?0b bits reset r/w description 31?18 0h ? reserved. 17?16 00b r schedulingoverruncount (soc) these bits are incremented in each schedulingoverrun error. these bits are initially set to b'00 and returned to b'11. these bits are incremented when sched ulingoverrun is detected even though the schedulingoverrun bit in hcinterruptstatus is set. these bits are used by hcd to monitor any continuous scheduling problem. 15?4 0h ? reserved. 3 0b r/w ownershipchangerequest (ocr) this bit is set by os hcd to request the change of the control of the host controller. when this bit is set, the host controller sets the ownershipchange bit in the hcinterruptstatus register. after a change, this bit is cleared and remains until the next request from os hcd. 0: after a change, this bit is cleared and remains until the next request from os hcd. (initial value) 1: set the ownershipchange bi t in the hcinterruptstatus register.
section 24 usb host module rev.6.00 mar. 27, 2009 page 733 of 1036 rej09b0254-0600 register: hccommandstatus offset: 08?0b bits reset r/w description 2 0b r/w bulklistfilled (blf) this bit is used to indicate that there are some tds in the list. this bit is set by hcd to the list when td is added to ed. when the host controller starts to process the head of the list, it checks bf. as long as bulklistf illed is 0, the host controller does not start to process the list. when bulklistfilled is 1, the host controller starts to process the list to set bf to 0. when the host controller finds td in the list, the host controller sets bulklistfilled to 1. when td is never found in the list and hcd does not set bulklistfilled, the host controller completes the processing of the list. bulklistfilled is still 0 when the size list processing is stopped. 0: the list is not processed (initial value) 1: the list is processed. 1 0b r/w controllistfilled (clf) this bit is used to indicate that there are some tds in the control list. this bit is set by hcd when td is added to ed in the control list. when the host controller starts to process the head of the control list, it checks clk. as l ong as controllistfilled is 0, the host controller does not start to process the control list. if cf is 1, the host controller starts to process the control list and controllistfilled is set to 0. when the host controller finds td in the list, the host controller sets controllistfilled to 1. when td is never found in the control list and hcd does not set controllistfilled, the host controller completes the processing of the control list. controlllistfill ed is still 0 when the control list processing is stopped. 0: the list is not processed. (initial value) 1: the list is processed.
section 24 usb host module rev.6.00 mar. 27, 2009 page 734 of 1036 rej09b0254-0600 register: hccommandstatus offset: 08?0b bits reset r/w description 0 0b r/w hostcontrollerreset (hcr) this bit is set by hcd to initiate the software reset of the host controller. the system is mov ed to the usbsuspend state in which most of the operational r egisters are reset except for the next state regardless of the functional state of the host controller. for example, an access to the interruprouting field in hccontrol and without host bus are allowed. this bit is cleared by the host controller upon completion of the reset operation. this bit does not cause any reset to the route hub and the next reset signal is not issued to the downstream port. 0: cleared by the host controller at the completion of the reset control 1: usbsuspend state
section 24 usb host module rev.6.00 mar. 27, 2009 page 735 of 1036 rej09b0254-0600 24.2.4 hcinterruptstatus hcinterruptstatus register (h'0400040c) this register indicates the status in various even ts that cause hardware interrupts. when an event occurs, the host controller sets the corresponding bit in this register. when the bit is set to 1, a hardware interrupt is generated while an interrupt is enabled and the msterinterrupenable bit is set in the hcinterruptenable register (see section 24 .2.5, hcinterruptenable). the host control driver clears a specified bit in this register by writing 1 in the bit position to be cleared. the host controller driver cannot set any bit of these bits. the host controller never clears bits. register: hcinterruptstatus offset: 0c?0f bits reset r/w description 31 0h ? reserved. 30 0b r/w ownershipchange (oc) this bit is set by the host controller when the ownershipchangerequest bit in the hccommandstatus reigster is set. this event generates a system management interrupt at once when not masked. when there is no smi pin, this bit is set to 0. 0: the ocr bit in the hccommandstatus register is not set. (initial value) 1: the ocr bit in the hccommandstatus register is set. 29?7 0h ? reserved. 6 0b r/w roothubstatuschange (rhsc) this bit is set when the content of hcrhstatus or the content of any hcrhportstatus 1, 2 register [number of downstream port] has changed. 0: the content of t he hcrhstatus register or hcrhportstatus register is not changed. (initial value) 1: the content of t he hcrhstatus register or hcrhportstatus register is changed. 5 0b r/w framenumberoverflow (fno) this bit is set when msb (bit 15) in the hcfumnumber register changes value from 0 to 1 or from 1 to 0 or the hccaframenumber bit is updated. 0: msb or the hccaframenumber bit in the hcfmnumber register is not updated. (initial value) 1: msb or the hccaframenumber bit in the hcfmnumber register is updated.
section 24 usb host module rev.6.00 mar. 27, 2009 page 736 of 1036 rej09b0254-0600 register: hcinterruptstatus offset: 0c?0f bits reset r/w description 4 0b r/w unrecoverableerror (ue) this bit is set when the host controller detects a system error that is not related to usb. hcd clears this bit after the host controler is reset. 0: system error has not generated yet. (initial value) 1: system error is detected. 3 0b r/w resumedetected (rd) this bit is set when the host cont roller detects that a device of usb issues a resume signal. this bit is not set when hcd sets usbresume state. 0: the resume signal is not detected. (initial value) 1: the resume signal is detected. 2 0b r/w startofframe (sf) this bit is set by the host controller when each frame starts and after the hccaframenumber is updated. the host controller simultaneously generates the sof token. 0: each frame has not initiated or hccaframe number is not updated (initial value) 1: initiation of each frame and updating of hccaframenumber 1 0b r/w writebackdonehead (wdh) this bit is set immediately after the host controller has written hcdonehead to hccadonehead. hccadonehead is not updated until this bit is cleared. hcd should clear this bit only after the content of hccadonehead has been stored. 0: when cleared after set to 1. (initial value) 1: when hcdonehead is written to hccadonehead. 0 0b r/w schedulingoverrun (so) this bit is set when the usb schedule has overrun after hccaframenumber has updated. schedulingoverrun also increments the schedulingoverruncount bit in hccommandstatus. 0: the usb schedule has not overrun. (initial value) 1: the usb schedule has overrun.
section 24 usb host module rev.6.00 mar. 27, 2009 page 737 of 1036 rej09b0254-0600 24.2.5 hcinterruptenable hcinterrutpenable register (h'04000410) each enable bit in the hcinterruptenable register corresponds to the related interrupt bit in the hcinterruptstatus register. the hcin terruptenable register is used to control an event to generate a hardware interrupt. a hardware interrupt is requested in the host bus when a bit in the hcinterruptenable register is set, a corresponding bit in the hcinteruptenable register is set, and the masterinterrupenable bit is set. as a result, the usbhi bit in interrupt request register 3 (irr3) of interrupt controller intc is set (the usbhi bit is used in common regardless of the content of the interrupt generation event). therefore, the usbhi bit can be used when an interrupt generation is detected by hcd. writing 1 in this register sets the corresponding b it, while writing 0 leaves the bit. when read, the current value of this register is returned.
section 24 usb host module rev.6.00 mar. 27, 2009 page 738 of 1036 rej09b0254-0600 register: hcinterruptenable offset: 10?13 bits reset r/w description 31 0b r/w masterinterruptenable (mie) setting of this bit to 0 is ignored by the host controller. when this bit is set to 1, an interrupt generation by the event specified in another bit in this register is enabled. this is used by hdc that the master interrupt is enabled. when an interrupt is detected by hcd, use the usbi h bit of interrupt controller intc. 0: ignore (initial value) 1: enable interrupt generati on due to the specified event. 30 0b r/w ownershipchangeenable (oc) 0: ignore (initial value) 1: enable interrupt generation due to ownership change. 29?7 0h ? reserved. 6 0b r/w roothubstatuschangeenable (rhsc) 0: ignore (initial value) 1: enable interrupt generation due to root hub status change. 5 0b r/w framenumberoverflowenable (fno) 0: ignore (initial value) 1: enable interrupt generation due to frame number overflow. 4 0b r/w unrecoverableerrorenable(ue) 0: ignore (initial value) 1: enable interrupt generation due to unrecoverable error. 3 0b r/w resumedetectedenable (rd) 0: ignore (initial value) 1: enable interrupt generation due to resume detected. 2 0b r/w startofframeenable (sf) 0: ignore (initial value) 1: enable interrupt generati on due to start of frame. 1 0b r/w writebackdoneheadenable (wdh) 0: ignore (initial value) 1: enable interrupt generation due to writeback done head. 0 0b r/w schedulingoverrunenable (so) 0: ignore (initial value) 1: enable interrupt generation due to scheduling overrun.
section 24 usb host module rev.6.00 mar. 27, 2009 page 739 of 1036 rej09b0254-0600 24.2.6 hcinterruptdisable hcinterruptdisable register (h'04000414) each disable bit in the hcinterruptdisable register corresponds to the related interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is related to the hcinterruptenable register. therefore, writing a 1 to a bit in th is register clears the corresponding bit in hcinterruptenable register, while writing a 0 to a bit leaves the co rresponding bit in the hcinterruptenable register. when read, the current value of the hcinterruptenable register is returned. register: hcinterruptdisable offset: 14?17 bits reset r/w description 31 0b r/w masterinterruptenable (mie) 0: ignore 1: disable interrupt generation due to the specified event. 30 0b r/w ownershipchangeenable (oc) 0: ignore 1: disable interrupt generation due to ownership change. 29?7 0h ? reserved. read/write 0's 6 0b r/w roothubstatuschangeenable (rhsc) 0: ignore 1: disable interrupt generation due to root hub status change. 5 0b r/w framenumberoverflowenable (fno) 0: ignore 1: disable interrupt generation due to frame number overflow. 4 0b r/w unrecoverableerrorenable (ue) 0: ignore 1: disable interrupt generation due to unrecoverable error. 3 0b r/w resumedetectedenable (rd) 0: ignore 1: disable interrupt generation due to resume detected. 2 0b r/w startofframeenable (sf) 0: ignore 1: disable interrupt generat ion due to start of frame. 1 0b r/w writebackdoneheadenable (wdh) 0: ignore 1: disable interrupt generation due to writeback done head.
section 24 usb host module rev.6.00 mar. 27, 2009 page 740 of 1036 rej09b0254-0600 register: hcinterruptdisable offset: 14?17 bits reset r/w description 0 0b r/w schedulingoverrunenable (so) 0: ignore 1: disable interrupt generatio n due to scheduling overrun. 24.2.7 hchcca hcca register (h'04000418) the hchcca register includes physical addresse s of the host controller communication area. the host controller driver determines the alignment li mitation by writing 1 to all bits in the hchcca register and by reading the content of the hchcca register. alignment is evaluated by checking the number of 0 in the lower bits. the minimum alignment is 256 bytes. consequently, bits 0 to 7 must be always returned to 0 when they are read. this area is used to retain the control structure and interrupt table that are accessed by the host controller and host controller driver. register: hchcca offset: 18?1b bits reset r/w description 31?8 0h r/w hcca 7?0 0h ? reserved. 24.2.8 hcperiodcurrented hcperiodcurrented register (h'0400041c) the hcperiodcurrented register includes a physical address of current isochronous ed or interrupt ed. register: hcperiodcurrented offset: 1c?1f bits reset r/w description 31?4 0h r/w periodcurrented (pced) pointer to the current periodic list ed. (within memory area3) 3?0 0h ? reserved.
section 24 usb host module rev.6.00 mar. 27, 2009 page 741 of 1036 rej09b0254-0600 24.2.9 hccontrolheaded hccontrolheaded (h'04000420) the hccontrolheaded register include s a physical address of first ed. register: hccontrolheaded offset: 20?23 bits reset r/w description 31?4 0h r/w controlheaded (ched) pointer to the control list head ed. (within sram memory space) 3?0 0h ? reserved. 24.2.10 hccontrolcurrented hccontrolcurrented re gsiter (h'04000424) the hccontrolcurrented register includ es a physical address of current ed. register: hccontrolcurrented offset: 24?27 bits reset r/w description 31?4 0h r/w controlcurrented (cced) pointer to the current control list ed. (within memory area3) 3?0 0h ? reserved. 24.2.11 hcbulkheaded hcbulkheaded register (h'04000428) the hcbulkheadedregister includes a physi cal address of first ed in bulk list. register: hcbulkheaded offset: 28?2b bits reset r/w description 31?4 0h r/w bulkheaded (bhed) pointer to the bulk list head ed. (within memory area3) 3?0 0h ? reserved.
section 24 usb host module rev.6.00 mar. 27, 2009 page 742 of 1036 rej09b0254-0600 24.2.12 hcbulkcurrented hcbulkcurrented register (h'0400042c) the hcbulkcurrented register includes a physical address of current ed in the bulk list. when the bulk list is supplied by the round robin method, endpoints are ordered to the list according to these insertions. register: hcbulkcurrented offset: 2c?2f bits reset r/w description 31?4 0h r/w bulkcurrented (bced) pointer to the current bulk list ed. (within memory area3) 3?0 0h ? reserved. 24.2.13 hcdonehead hcdonehead register (h'04000430) the hcdonehead register include s a physical address of finally completed td added to done queue. the host controller needs not read this regi ster so that the content is written to hcca periodically in normal operation. register: hcdonehead offset: 30?33 bits reset r/w description 31?4 0h r/w donehead (dh) pointer to the current done list head ed. (within memory area 3) 3?0 0h ? reserved.
section 24 usb host module rev.6.00 mar. 27, 2009 page 743 of 1036 rej09b0254-0600 24.2.14 hcfminterval hcfminterval register (h'04000434) the hcfminterval register includes a 14-bit value indicating the bit time interval of the frame (i.e., between two serial sofs) and a 15-bit value indi cating the maximum packet size at a full speed that is transmitted and received by the host controller without causing scheduling overrun. the host controller driver adjusts the frame interval minutely by writing a new value over the current value in each sof. this supplies required programming ability to the host controller to synchronize with an external clock source and to synchronize with offset of an unknown local clock. register: hcfminterval offset: 34?37 bits reset r/w description 31 0b r/w frameintervaltoggle (fit) this bit is toggled by hcd whenever it loads a new value into frameinterval . 30?16 0h r/w fslargestdatapacket (fsmps) this field specifies a value which is loaded into the largest data packet counter at the beginning of each frame. the counter value expresses the largest data amount of the bit that can be transmitted and rece ived in one transaction by the host controller at any given time without causing scheduling overrun. the field value is calculated by hcd. 15?14 0h ? reserved. 13?0 2edfh r/w frameinterval (fi) these bits specifies the interval between two serial sofs with bit times. the nominal value is set to 11999. hcd must store the current value of this field bef ore resetting the host controller. with this procedure, this bit is reset to its nominal value by the host controller by setting the hostcontrollerreset bit in the hccommandstatus register. hcd can select to restore the stored value at the completi on of the reset sequence.
section 24 usb host module rev.6.00 mar. 27, 2009 page 744 of 1036 rej09b0254-0600 24.2.15 hcfmremaining hcframeremaining register (h'04000438) the hcfmremaining register is a 14-bit down counter indicating the bit time remaining in the current frame. register: hcframeremaining offset : 38?3b bits reset r/w description 31 0b r frameremainingtoggle (frt) this bit is always loaded from the frameintervaltoggle bit in hcfminterval when framereamining reaches 0. this bit is used by hcd for the synchronization between frameinterval and framereamining. 30?14 0h ? reserved. 13?0 0b r frameremaining (fr) this counter is decremented at each bit time. when this counter reaches 0, this counter is reset by loading the value of the framinterval bit specified in the hcfminterval register at the next bit time boundary. when the host controller transits to the usboperational state, it read the frameinterval bit in the hcfminterval register again and use the updated value from the next sof.
section 24 usb host module rev.6.00 mar. 27, 2009 page 745 of 1036 rej09b0254-0600 24.2.16 hcfmnumber hcfmnumberb register (h'040004bc) the hcfmnumber register is a 16-bit counter. it indicates the reference of timing between events occurring in the host controller and host controller driver. the host controller driver uses a 16-bit value specified in this register and generate s a 32-bit frame number without necessity for a frequent access to the register. register: hcfmnumber offset: 3c?3f bits reset r/w description 31?16 0h ? reserved. 15?0 0b r framenumber (fn) these bits are incremented when hcfmremaining is reloaded. the count will return to h'0 after h'ffff. when the host controller transits to the usboper ational state, these bits are automatically incremented. afte r the host controller increments the framnumber bit and sends sof in each frame boundary, the content is written to hcca bef ore the host controller reads first ed in the frame. after writ ing to hcca, the host controller sets the startofframe bit in the hcinterruptstatus register.
section 24 usb host module rev.6.00 mar. 27, 2009 page 746 of 1036 rej09b0254-0600 24.2.17 hcperiodicstart hcperiodicstart register (h'04000440) the hcperiodicstart register has a 14-bit programm able value, which determines the earliest time when the host controller should start to process the periodic list. register: hcperiodicstart offset: 40?43 bits reset r/w description 31?14 0h ? reserved. 13?0 0b r/w periodicstart (ps) this field is cleared after the hardware has reset. then this field is set by hcd while the host controller performs initial settings. the value is roughly calculated as the value of the hcfminterval register minus 10%. when the hcfm remaining register reaches the specified value, the processing of the periodic list has a higher priority than the control/bulk processing. consequently, the host controller starts to process the interrupt list after the comple tion of the current control/bulk transaction. 24.2.18 hclsthreshold hclsthreshold register (h'04000444) the hclsithreshold register includes an 11-bit value that is used by the host controller to determine whether or not to authorize the transfer of the ls packed 8 bytes in maximum before eof. the host controller and host controller driver cannot change this value. register: hclsthreshold offset: 44?47 bits reset r/w description 31?12 0h ? reserved. 11?0 628h r/w lsthreshold (lst) this field contains a value to be compared with the frameremaining bit prior to the beginning of low-speed transaction. the transaction is started only when the frame remaining bit value is beyond the value of the list. the value is calculated by hcd considering the transmission and set-up overhead.
section 24 usb host module rev.6.00 mar. 27, 2009 page 747 of 1036 rej09b0254-0600 24.2.19 hcrhdescriptora hcrhdescriptora register (h'04000448) the hcrhdescriptora register is the first register of two registers describing the features of the root hub. the reset value is implementation specific. the descriptor length (11), descriptor type (tbd), the hub controller current bit (0) of class descriptor of the hub are emulated by hcd. all other bits are placed in the hcrhdescriptor a register and hcrhdescriptorb register. register: hcrhdescriptora offset: 48?4b bits reset r/w description 31?24 02h r/w powerontopowergoodtime (potpgt) these bits specify the time required for waiting before accessing the power-on port of the root hub. these bits are implementation specific. the unit of time is 2 ms. the time is calculated as potpgt 2 ms. 23?13 0h ? reserved. 12 1 r/w noovercurrentprotection (nocp) this bit selects how the over-cu rrent status of the root hub is reported. when this bit is cleared, the overcureentprotectionmode bit s pecifies global report or report at each port. 0: over-current status is collec tively reported for all downstream ports. 1: over-current protection is no t supported. (initial value) 11 0 r/w overcurrentprotectionmode (ocpm) this bit selects how the over-cu rrent status in the root-hub port is reported. at reset, this bit reflects the same mode of powerswitchingmode. when the noovercureentprotection bit is cleared, this bit is valid. 0: over-current status is collec tively reported for all downstream ports. (initial value) 1: over-current protection is not supported. 10 0 r devicetype (dt) usb host controller is not a compound device. always set to 0.
section 24 usb host module rev.6.00 mar. 27, 2009 page 748 of 1036 rej09b0254-0600 register: hcrhdescriptora offset: 48?4b bits reset r/w description 9 1 r/w nopowerswitching (nps) this bit selects whether the power switching is supported or ports are always power-supplied. this bit is implementation specific. when this bit is cleared, power-switchingmode specifies the globa l/port switching. 0: ports can be power-switched. 1: ports are always powered on when the host controller is powered on. (initial value) note: because the initial value is 1, first clear this bit (write 0 with the hcd) to enable power switching of the port. 8 0 r/w powerswitchingmode (psm) this bit specifies how the power sw itching of the root-hub port is controlled. this bit is implementation specific. this bit is valid only when the nopowerswitching bit is cleared. 0: all ports are simultaneously power-supplied. (initial value) 1: each port is power-supplied individually. in this mode, the port power is controlled with eit her of global/port switching. when the portpowercontrolmask bit is set, the port is reacted only to the port-power command (set/clear port power). when the port mask is cleared, the port is controlled only by the global power-switch (set/clear global power). 7?0 02h r numberdownstreamports (ndp) these bits specify the number of downstream ports supported by the root hub. these bits are implementation specific. in the SH7727 their value is h'2.
section 24 usb host module rev.6.00 mar. 27, 2009 page 749 of 1036 rej09b0254-0600 24.2.20 hcrhdescriptorb hcrhdescriptorb register (h'0400044c) the hcrhdescriptorb register is the second register of two registers describing the features of the root hub. these bits are written during the initial setting so as to correspond to the system implementation. the reset value is implementation specific. register: hcrhdescriptorb offset: 4c?4f bits reset r/w description 31?16 0h r/w portpowercontrolmask (ppcm) this bit indicates that the port is influenced by the global power- control command when the powerswitchingmode bit is set. when this bit is set, the power state of the port is affected by the power control at each port (set/clear port power). when this bit is cleared, the port is controlled by the global power switch (set/clear global power). if the device is placed in the global switching mode (powerswitchingmode = 0), this bit is not valid. bit 15: assured bit 16: port #1 power mask bit 17: port #2 power mask ? bit 31: port #15 power mask note: clear the no power switching of the rhdescriptora register so that the power to all ports is off (port power status = 0), then set this bit. 15?0 0h r/w deviceremoveable (dr) these bits are dedicated to t he ports of the root hub. when these bits are cleared, the se t device becomes removable. when these bits are set, do not remove the set device. bit 0: assured bit 1: device affixed to port #1 bit 2: device affixed to port #2 ? bit 15: device affixed to port #15
section 24 usb host module rev.6.00 mar. 27, 2009 page 750 of 1036 rej09b0254-0600 24.2.21 hcrhstatus hcrhstatus register (h'04000450) the hcrhstatus register is divided into two parts. the lower word of a long word indicates the hub status bits and the upper word indicates the hub status change bit. reserved bits should be set to 0. register: hcrhstatus offset: 50?53 bits reset r/w description 31 0 w clearremotewakeupenable (crwe) writing a 1 to this bit clears deviceremotewakeupenable . writing a 0 has no effect. 30?18 0h ? reserved. read/write 0's 17 0 r/w overcurrentindicatorchange (ocic) this bit is set when overcurrentindicator changes. writing a 1 clears this bit. writing a 0 has no effect. 16 0 r/w (read) localpowerstatuschange (lpsc) the root hub does not support the local power status function. therefore, this bit is always read 0. (write) setglobalpower this bit is written to 1 to power on (clears the portpowerstatus bit) all ports in global power mode (powerswitchingmode = 0). this bit sets the portpowerstatus bit only to the port in which the portpowercontrolmask bit is not set in power mode at each port. when 0 is written to, this bit is not cleared. 15 0 r/w (read) deviceremotewakeupenable (drwe) this bit enables the connectstatuschange bit as a resume event and generates the state tr ansition from usbsuspend to usbresume and resumedetected interrupt. 0: connectstatuschange is not the remote wakeup event (initial value) 1: connectstatuschange is the remote wakeup event. (write) setremotewakeupenable writing a 1 sets deviceremotewakeupenable . writing a 0 has no effect. 14?2 0h ? reserved.
section 24 usb host module rev.6.00 mar. 27, 2009 page 751 of 1036 rej09b0254-0600 register: hcrhstatus offset: 50?53 bits reset r/w description 1 0 r overcurrentindicator (oci) this bit reports the over-current condition. when this bit is set, an over-current condition exists. when this bit is cleared, all power operations are normal. this bit is always 0 when the over-current protection at each port is carried out. 0: all power operations are normal. (initial value) 1: an over-current condition exists. 0 0 r/w (read) localpowerstatus (lps) the root hub does not support the local power status function. therefore, the bit is always read 0. (write) clearglobalpower this bit is written to 1 to po wer on (leaves the portpowerstatus bit) all ports in global power mode (power switching mode = 0). this bit clears the portpowerstatus bit only to the port in which the portpowercontrolmask bit is not set. writing a "0" has no effect. in the power mode at each port, the portpowerstatus bit is cleared to the port in which the portpowercontrolmask bit is not set. writing 0, has no effect. 24.2.22 hcrhportstatus[1:2] hcrhportstatus register ([1]:04000454 [2]:04000458) this register is reset by the u sb r eset state. hcrhportstatus 1, 2 registers are used for base-con trolling each port and to report the port event. the lower word is used to reflect the port status while the upper word reflects the status change. some status bits have special writing (see below). if an attempt to write to a bit indicating a change in port status occurs when a transaction in which a token is passed via a handshake is in progress, the writing to the bit is delayed until the transaction is completed. always write reserved bits to 0.
section 24 usb host module rev.6.00 mar. 27, 2009 page 752 of 1036 rej09b0254-0600 register: hcrhportstatus[1:2] offset: 54?57, 58?5b bits reset r/w description 31?21 0h ? reserved. 20 0 r/w portresetstatuschange (prsc) this bit is set when the 10 ms port reset signal has completed. writing a 1 clears this bit writing a 0 has no effect. 0 = port reset is not complete. 1 = port reset is complete. 19 0 r/w portovercurrentindicatorchange (ocic) this bit is valid when an over-current condition is reported on the base of each port. this bit is set when the root hub changes the portovercurrentindicator bit. writing a 1 clears this bit. writing a 0 has no effect. 0: portovercurrentindicator has not changed. (initial value) 1: portovercurrentindicator has changed. 18 0 r/w portsuspendstatuschange (pssc) this bit is set when all resume sequences have completed. these sequences include 20 ms resume pulse, ls eop, and 3 ms resychronization delay. writing a 1 clears this bit. writing a 0 has no effect. this bit is cleared also when resetstatuschange is set. 0: port resume has not completed. (initial value) 1: port resume has completed. 17 0 r/w portenablestatuschange (pesc) this bit is set when the portenablestatus bit is cleared due to a hardware event. this bit is not set by the change of writing of hcd. writing a 1 clears this bit. writing a 0 has no effect. 0: portenablestatus has not changed (initial value) 1: portenablestatus has changed
section 24 usb host module rev.6.00 mar. 27, 2009 page 753 of 1036 rej09b0254-0600 register: hcrhportstatus[1:2] offset: 54?57, 58?5b bits reset r/w description 16 0 r/w connectstatuschange (csc) this bit is set whenever the connection or disconnection event occurs. writing a 1 clears this bit. writing a 0 has no effect. if currentconnectstatus is cleared when setportreset, setportenable, or setportsuspend is written to, writing when the power supply of the port is disconnected does not occur, so this bit is set to enforce the driver to re-evaluate the connection status. 0: currentconnectionstatus has not changed (initial value) 1: currentconnectionstatus has changed note: if the device removable bi t is set, this bit is set only after the root hub reset to in form that the system that a device can be attached. 15?10 0h ? reserved. 9 0 r/w (read) lowspeeddeviceattached (lsda) this bit indicates the speed of the device attached to this port. when this bit is set, a low-seed device is attached to this port. when this bit is cleared, a full-speed device is attached to this port. this bit is valid only when the currentconnectstatus bit is set. 0: a full-speed device is set. (initial value) 1: a low-speed device is set. (write) clearportpower writing a 1 clears portpowerstatus . writing a 0 has no effect
section 24 usb host module rev.6.00 mar. 27, 2009 page 754 of 1036 rej09b0254-0600 register: hcrhportstatus[1:2] offset: 54?57, 58?5b bits reset r/w description 8 1 r/w (read) portpowerstatus (pps) this bit reflects the power state of the port regardless of the power switching mode to be executed. however, because the initial va lue of the no power switching bit of the hcrhdescriptora register is 1, this bit is first fixed to 1. no power switching bit must first be cleared before the power is switched, as shown below. when an over-current condition is detected, this bit is cleared. writing setportpower or setglovalpower sets this bit. writing clearportpower or clearglobalpower clears this bit. powerswitchingmode and portpowercontrolmask determine which power control switch can be used. only set/clearglobalpower controls this bit in global switching mode (powerswitchingmode= 0). if the portpowercontrolmask bit of that port is set in power switching mode (powerswitchingmode = 1). only the set/clearglobalpower command is enabled if the mask is not set. when the port power is disabled, currentconnectstatus, portenablestatus, portsuspendstatus, and portresetstatus are reset. 0 = port power is off. 1 = port power is on. (initial value) note: if nopowerswitching is set, this bit is always read as 1. (write) setportpower writing a 1 sets portpowerstatus . writing a 0 has no effect. 7?5 0h ? reserved. 4 0 r/w (read) portresetstatus (prs) when this bit is set by writing to setportreset, the port reset signal is output. this bit is cleared when portresetstatuschange is set upon completion of a reset. when currentconnectstatus is cleared, this bit is not set. 0 = port reset signal is not active. (initial value) 1 = port reset signal is active. (write) setportreset writing a 1 sets portreset signal. writing a 0 has no effect. when currentconnectstatus is cleared, this write does not set portresetstatus, instead, sets connectstatuschange. this reports a reset of the power disconnection port to the driver.
section 24 usb host module rev.6.00 mar. 27, 2009 page 755 of 1036 rej09b0254-0600 register: hcrhportstatus[1:2] offset: 54?57, 58?5b bits reset r/w description 3 0 r/w (read) portovercurrentindicator (poci) this bit is valid only when a root hub is placed in such a way that an over-current condition is reported on the base of each port. if the over-current report at each port is not supported, this bit is set to 0. if this bit is cleared, all power controls are normal in this port. if this bit is set, an over-current status exists in this port. this bit always reflects an over-current input signal. 0 = no over-current condition (initial value) 1 = over-current condition is detected (write) clearsuspendstatus writing a 1 initiates a resume. writing a 0 has no effect. if portsuspendstatus is set, a resume is initiated. 2 0 r/w (read) portsuspendstatus (pss) this bit indicates that the por t is suspended or during the resume sequence. writing setsuspendstate sets this bit and setting portsuspendstatuschange clears this bit at the end of the resume interval. if currentconn ectstatus is cleared, this bit cannot be set. when portresetstatuschange is set upon completion of the port reset or hc is placed in the usbresume state, this bit is cleared. if an upstream resume is in progress, it is transmitted to the host controller. 0 = port is not suspended 1 = port is selectively suspended (write) setportsuspend writing a 1 sets portsuspendstatus . writing a 0 has no effect. in addition, when currentconnectstatus is cleared, portsuspendstatus is not set by this writing. instead, connectstatuschange is set. this reports the suspended state of the power disconnection to the driver.
section 24 usb host module rev.6.00 mar. 27, 2009 page 756 of 1036 rej09b0254-0600 register: hcrhportstatus[1:2] offset: 54?57, 58?5b bits reset r/w description 1 0 r/w (read) portenablestatus (pes) this bit indicates whether the port is enabled or disabled. the root hub clears this bit when the over-current condition and a operational bus error such as disconnect event, power-off switch, or babble is detected. portenabledstatuschange is set by this change. this bit is set by writing setportenable and cleared by writing clearportenable. this bit cannot be set when currentconnectstatus is cleared. in addition, this bit is set upon completion of the port reset by which resetstatuschange is set, or uponcompletion of the port suspend by which suspendstatuschange is set. 0 = port disabled. (initial value) 1 = port enabled. (write) setportenable writing a 1 sets portenablestatus . writing a 0 has no effect. if currentconnectstatus is cleared, this writing does not set portenablestatus, instead, sets connectstatuschange. this reports the driver that the power disconnection port has been tried to be enabled. 0 0 r/w (read) currentconnectstatus (ccs) this bit indicates the status of the downstream port. 0 = no device connected. 1 = device connected. note: if deviceremoveable is set (not removable) this bit is always 1. (write) clearportenable writing a 1 clears portenablestatus . writing a 0 has no effect. currentconnectstatus is not affected by any writing.
section 24 usb host module rev.6.00 mar. 27, 2009 page 757 of 1036 rej09b0254-0600 24.3 data storage format which re quired by usb host controller 24.3.1 storage format of the transferred data usb host controller expects that data are co mpiled from lower address to upper address regardless endian setting of the cpu. below figu re shows data read operation which is done by usb host controller. program memory (area 3) usb host data.l h'11223344 data.l h'55667788 data.l h'00000099 lw read h'11223344 lw read h'5566778 8 lw read h'0000009 9 +3 11 +7 55 +11 00 +2 22 +6 66 +10 00 +1 33 +5 77 +9 00 +0 44 +4 88 8 99 the correspondence between data in memory and data read by usb host controller must be equal. when usb host controller reads data fr om external memory, usb host controller reads data by long word read operation every time regard less that the read data are written in byte ,word or long word. usb host controller uses data in byte from lower address in long word which it reads regardless the endian mode. even endian mode is set as big or little, set the data from down addresses. below program flow is the example of failure. 1 st in program, set transfer address a to register r0 at big endian 2 nd in program, ?mov.b #h'12,@r0? 3 rd in program , set transfer star t address a to usb host controlle r , and set 1byte as transfer size. memory data expected to be transferred actually transferred data lw read h'12000000 +3 12 +2 00 +1 00 +0 00 this example show that above opera tion transfers expected data #h'12.
section 24 usb host module rev.6.00 mar. 27, 2009 page 758 of 1036 rej09b0254-0600 data is filled from the lower bits of the memory in writing so that the data is read/written in bi- direction consistently regardless of the endian type . that is, the data is always aligned with the little endian specification. 24.3.2 storage format of the descriptor ed (endpoint descriptor) and td (t ransfer descriptor) that define each transfer transaction of usb host controller must be aligned so that each dword corresponds to the long-word boundary (addresses 4n to 4n + 3) of the memory. 24.4 data alignment restriction of usb host controller 24.4.1 restriction on the line bo undary of the synchronous dram the transferred data is stored in shared system memory with cpu. the data alignment in system memory are restricted depends on synchronous dram specification which is used as system memory. n n+1 n+2 dram row address memory area row address row address (1) (2) (3) in above figure, transfer data 1 and 3 are able to be read or written by usb host controller. but transfer data 2 are possibly unable to be read or written by usb host controller. any data which have possibility to be accessed by usb host cont roller must be aligned in synchronous dram not to cross row address alignment.
section 24 usb host module rev.6.00 mar. 27, 2009 page 759 of 1036 rej09b0254-0600 24.4.2 restriction on the memory access address mps in ed, cbp in general td, and bp0 and offse t0 to 7 in ischoronous td must be set in multiples of 4 (4n). in the openhci standard, 1 packet is transferred by itd in general td and 1 packet by 1 offset in ischronou s td. in addition, when the amount of the data specified by td during out transfer exceeds maxpacketsize (mps ), a packet transmission is carried out in maxpacketsize. therefore, the setting value can be made as above. this restriction is due to the difference between the specifications of the hc i interface which is the standard of the ip bus interface of usb and of the bus interface of SH7727 . data might be correctly written to if data is transferred from addresses other than 4n address. for example, when a two-byte transfer is carried out from the address that terminates at 1, a long -word transfer is carried out and an unexpected data is written to starting address 0. 24.5 restrictions on the data transfer of usb controller 24.5.1 restriction of the data size in in transfer when a data packet shorter than maxpacketsize (short packet) is transferred in the in data transfer, following usages are restricted. 1. usage when a dribble bit is added when hub are connected in mul tiple steps, a dribble bit may be added at the end of the packet. 2. when receiving the data with final 6 bits in crc are all 1 (in this case, bit stuffing occurs) in this case, this usb controller may write in data in the memory with one byte additionally. therefore, usage of 1 is prohibited. in usage of 2, the software must be written to so that no problem occurs even additional data of 1 byte is written to. in concrete, in the usage to connect the received short packets are connected in the memory, 1 byte of unnecessary data might be inserted. be sure to transfer maxpacketsize mainly and the processed data will be used so that the end of the data or head can be recogni zed when a short packet is sent. in applications where the receive data size cannot be controlled by software, it is not possible to use software to remove the 1 byte of unnecessary data. when using the module in such cases, appropriate countermeasures must be considered. 24.5.2 restrictions on the hub connection on nak/stall reception when nak or stall is received as a handshake from the usb function module, the following usage is restricted. 1. usage where a dribble bit is added
section 24 usb host module rev.6.00 mar. 27, 2009 page 760 of 1036 rej09b0254-0600 when hubs are connected in mu ltiple steps, a dribble bit may be added at the end of the packet. in this case, this usb controller might not correctly recognize the nak/stall handshake. be sure not to connect hub to d ecrease steps so that no dribble bit occurs. 24.5.3 restrictions when a lo w-speed device is disconnected when a low-speed device connected to the root po rt is disconnected while the data is transmitted to the host, this usb controller might hung. theref ore, be sure not to disconnect the low-speed device while the data is transmitted. if that disc onnection is detected, reset usb (write 00 to the hcfs bit in the hccontrol register). 24.6 restrictions on the software reset and usb reset the operation of the controller might become stuck if a software reset (1 written to the hcr bit in the hccommandstatus register) or usb reset (00 written to the hcfs bit in the hccontrol register) is performed while the usb host cont roller is carrying out a master memory write. master memory write operations are performed at the start of frame (sof) and during data transfer. to prevent the host controller from becoming stuck, use one of the following methods: 1. write the program so that the sdf timing is derived from the hcfmremaining value and a software reset or usb reset is applied around the middle of a frame in which all list processing is disabled. 2. if you issue a reset for the usbh module after applying a software reset or usb reset, no stack will occur. (set the module soft ware reset register (srstr).) 24.7 notes on using usb host with versions previous to the SH7727c the usb host controller of the SH7727 and SH7727b may erroneously recognize an se0 state during data transfer. as a result, the controlle r incorrectly detects a device not connected state (erroneous device not connected detection) even though the device actually is connected. the following methods may be used to work around this problem. 1. use the low speed (1.5 mbps) mode. erroneous device not connected detection does not occur during low speed data transfer. 2. when using the full speed (12 mbps) mode, use method (a) or (b) below to avoid erroneous device not connected detection. a. ensure that the d+, d? crossover voltage output by the usb function device exceeds SH7727 avcc_usb 0.55 (v). b. ensure that received data strings do not contain more than 28 consecutive 0 bits.
section 24 usb host module rev.6.00 mar. 27, 2009 page 761 of 1036 rej09b0254-0600 note: the prohibition on consecutive 0 bits applies to all bits of sync + pid + data + crc16 + eop. eop is counted as 2 bits. explanation of terms ? se0: usb data transfer uses a d+/d? differen tial signal. consequently , d+/d? is normally a reciprocal signal. however, in some special cases d+ and d? ar e both defined as low. this state is referred to as se0. ? device not connected detection: detection of a usb device not connected state when se0 continues beyond the device not connected detection duration. 24.8 usage notes of resume operation of usb host controller (usbh) 1. phenomenon while the usb host is providing an output of a resume * 1 signal, suppose that (a) portpower is turned off or that (b) overcurrent is produ ced. in this case, the resume signal should ordinarily be stopped so that the idle * 2 state will be established. actually, however, the result is that an idle signal is output. notes: 1. in fullspeed, d+ = low and d- = high. in lowspeed, d+ = high and d- = low. 2. in fullspeed, d+ = high and d- = low. in lowspeed, d+ = low and d- = high. 2. conditions when the above phenomenon occurs while a resume * 1 signal is being output, (a) portpower is turned off or (b) overcurrent is produced. 3. conditions when the above phenomenon does not occur the above phenomenon will not occur if there is no resume operation, that is, suspend operation has not been done. 4. workaround by software if the above phenomenon occurs, resume is interrupted and then an idle signal is output. however, turning on portpower enables device recognition. the above phenomenon is removed by the subsequent port reset for the device. normal operation is thus recovered. note, however, the above phenomenon will not be removed by usb reset, which is generated by the hcfs1 and hcfs0 bits in the hccontrol (usbhc) register. for this reason, if you are using software that issues usb reset by the hcfs1 and hcfs0 bits in the hccontrol (usbhc) register, modify the software so that it issues port reset by setting the prs bit in the hcrhportstatus1 or hcrhportstatus2 (usbhrps1 or usbhrps2) register. however, there is no need to take corrective action if port reset has already been issued by the prs bit before the recognition of usb device connection.
section 24 usb host module rev.6.00 mar. 27, 2009 page 762 of 1036 rej09b0254-0600
section 25 lcd controller rev.6.00 mar. 27, 2009 page 763 of 1036 rej09b0254-0600 section 25 lcd controller 25.1 overview a unified memory architecture is adopted for the lcd controller (lcdc) so that the image data for display is stored in system memory. the lcdc module reads data from system memory, uses the pallet memory to determine the colors, then puts the display on the lcd panel. it is possible to connect the lcdc to the lcd module of most ty pes other than microcomputer bus interface types and ntsc/pal types and those that apply the lvds interface ? . note: * an lvds-conversion lsi can be connect ed to the lcdc to allow connection to an lvds interface. 25.1.1 features the lcdc has the following features. ? panel interface ? serial interface method ? supports data formats for stn/dual-stn/tft panels (8/12/16/18-bit bus width) ? supports 4/8/15/16-bpp (bit per pixel) color modes ? supports 1/2/4/6-bpp grayscale modes ? supports lcd-panel sizes from 16 1 to 1024 1024 ? 24-bit color palette memory (16 of the 24 bits are valid; r:5/g:6/b:5) ? stn/dstn panels are prone to flicker and shadowing. the controller applies 65536-color control by 24-bit space-modulation frc with 8-bit rgb values for reduced flicker. ? dedicated display memory is unnecessary because the controller uses synchronous dram which is connected to area 3 of the cpu?s memory map ? the display is stable because of the large 2.4-kb yte line buffer ? supports the inversion of the output signal to suit the lcd panel?s signal polarity ? supports variation of the burst length in reading from the synchronous dram, to realize high- speeds in the reading of data ? supports the selection of data formats (the endian setting for bytes, backed pixel method) by register settings ? a hardware-rotation mode is included to support the use of landscape-format lcd panels as portrait-format lcd panels (the horizontal width of the panel before rotation must be within 320 pixels?see table 25.3).
section 25 lcd controller rev.6.00 mar. 27, 2009 page 764 of 1036 rej09b0254-0600 note: when connecting the lcdc to a tft panel with an unwired 18-bit bus, the lower-order bit lines should be connected to gnd or to the lowest bit from which data is output. 25.1.2 block diagram figure 25.1 shows a block diagram of lcdc. clock generator pallet ram 512 bytes lcdc power control register lclk bus clock (b ) peripheral clock (p ) bus interface li bus interface li bus line buffer 2.4 kbytes cl1 cl2 flm lcd 15 ? 0 don vcpwc vepwc m/disp peripheral bus clk figure 25.1 block diagram
section 25 lcd controller rev.6.00 mar. 27, 2009 page 765 of 1036 rej09b0254-0600 25.1.3 pin configuration table 25.1 summarizes the lcdc?s pin configuration. table 25.1 pin configuration name i/o function lcd 15 ? 0 o data for lcd panel don o display-on signal (don) cl1 o shift-clock 1 (stn/dstn)/horizontal sync signal (hsync) (tft) cl2 o shift-clock 2 (stn/dstn) /dot clock (dotclock) (tft) m/disp o lcd current-alternation signal/(stn/dstn), display enable blank (tft)/disp signal flm o first line marker/vertical sync signal (vsync) (tft) vcpwc o lcd-module power control (vcc) vepwc o lcd-module power control (v ee ) lclk i lcd clock-source input note: check the lcd module specifications carefu lly in section 25.4, clock and lcd data signal examples, before deciding on the wiring specifications for the lcd module. 25.1.4 register configuration table 25.2 summarizes the configur ation of the lcdc?s registers. table 25.2 register configuration register name abbreviation initial value address access size lcdc input clock register ldickr h?0101 h?04000c00 (h?a4000c00) * 16 lcdc module type register ldmtr h?0109 h?04000c02 (h?a4000c02) * 16 lcdc data format register lddfr h?000c h?04000c04 (h?a4000c04) * 16 lcdc scan mode register ldsmr h?0000 h?04000c06 (h?a4000c06) * 16 lcdc data fetch start address register for upper portion of display panel ldsaru h?0c000000 h?04000c08 (h?a4000c08) * 32 lcdc data fetch start address register for lower portion of display panel ldsarl h?0c000000 h?04000c0c (h?a4000c0c) * 32
section 25 lcd controller rev.6.00 mar. 27, 2009 page 766 of 1036 rej09b0254-0600 register name abbreviation initial value address access size lcdc fetch data line address offset register for display panel ldlaor h?0280 h?04000c10 (h?a4000c10) * 16 lcdc palette control register ldpalcr h?0000 h?04000c12 (h?a4000c12) * 16 lcdc palette data registers 00 to ff ldpr00?ff undefined h?04000800 to h?04000bfc (h?a4000800 to h?a4000bfc) * 32 lcdc horizontal character number register ldhcnr h?4f52 h?04000c14 (h?a4000c14) * 16 lcdc horizontal synchronization signal register ldhsynr h?0050 h?04000c16 (h?a000c16) * 16 lcdc vertical displayed line number register ldvdlnr h?01df h?04000c18 (h?a4000c18) * 16 lcdc vertical total line number re gister ldvtlnr h?01df h?04000c1a (h?a4000c1a) * 16 lcdc vertical synchronization signal register ldvsynr h?01df h?04000c1c (h?a4000c1c) * 16 lcdc ac modulation signal toggle line number register ldaclnr h?000c h?04000c1e (h?a4000c1e) * 16 lcdc interrupt control register ldintr h?0000 h?04000c20 (h?a4000c20) * 16 lcdc power management mode register ldpmmr h?0010 h?04000c24 (h?a4000c24) * 16 lcdc power supply sequence period register ldpspr h?f60f h?04000c26 (h?a4000c26) * 16 lcdc control register ldcntr h?0000 h?04000c28 (h?a4000c28) * 16 note: * when the lcdc is not a target for address conver sion by the mmu, use the addresses in parentheses.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 767 of 1036 rej09b0254-0600 25.2 register descriptions 25.2.1 lcdc input clock register (ldickr) this lcdc can select the bus clock (b ), the peripheral clock (p ), or the external clock as its operation clock source. the selected clock source can be divided using an internal divider into a clock of 1/1 to 1/16 and be used as the lcdc operating clock (dotclock). the clock output from the lcdc is used to generate the synchronous clock output (cl2) for the lcd panel from the operating clock selected in this register. the average frequency of cl2 can be calculated using the formula below. the actual frequency, however, w ill differ depending on the type of lcd panel and the bus width of the data output to the lcd panel. see section 25.4, clock and lcd data signal examples, for details. tft panel cl2 = dotclock stn or dstn panel monochrome: cl2 = (dotclock/data bus width of output to lcd panel) color: cl2 = 3 (dotclock/data bus width of output to lcd panel) set this register so that the clock input to th e lcdc is 50 mhz or less regardless of cl2. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? icksel 1 icksel 0 ? ? ? ? ? ? ? dcdr4 dcdr3 dcdr2 dcdr1 dcdr0 initial value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 r/w: r r r/w r/w r r r r r r r r/w r/w r/w r/w r/w bits 15, 14, and 11 to 5?reserved bits 13 and 12?input clock select (icksel1 and icksel0): set the clock source for dotclock. bit 13 icksel1 bit 12 icksel0 description 0 0 bus clock (b ) is selected (initial value) 1 peripheral clock (p ) is selected 1 0 external clock (lclk) is selected 1 reserved (setting prohibited)
section 25 lcd controller rev.6.00 mar. 27, 2009 page 768 of 1036 rej09b0254-0600 bits 4 to 0?denominator of clock division ratio (dcdr4 to dcdr0): set denominator of the input clock division ratio. i/o clock frequency (mhz) dcdr[4:0] clock division ratio 50.000 00001 1/1 50.000 (initial value) 00010 1/2 25.000 00100 1/4 12.500 01000 1/8 6.250 10000 1/16 3.125 any setting other than above is handled as a clock division ratio of 1/1 (initial value). note: the access size indicates the size the cp u uses to access (read from or write to) the register. when accessing this register in a size other than the displayed one, lcdc operation is not guaranteed. only 0 can be written to a reserved bit. when a setting not allowed is made, e.g. a reserved bit is written to, though the lcdc operates with its initial values, no rmal operation is not guaranteed. this is the common rule to all registers in this lcdc. 25.2.2 lcdc module type register (ldmtr) ldmtr sets the control signals output from this lcdc and the polarity of the data signals, according to the polarity of the signals fo r the lcd module connected to the lcdc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 flm pol cl1 pol disp pol dpol ? mcnt cl1 cnt cl2 cnt ? ? mif typ5 mif typ4 mif typ3 mif typ2 mif typ1 mif typ0 initial value: 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 r/w: r/w r/w r/w r/w r r/w r/w r/w r r r/w r/w r/w r/w r/w r/w bits 11, 7, and 6?reserved bit 15?flm (vertical sync signal) polarity select (flmpol): selects the polarity of the flm (vertical sync signal, first line marker) for the lcd module. bit 15 flmpol description 0 flm pulse is high active (initial value) 1 flm pulse is low active
section 25 lcd controller rev.6.00 mar. 27, 2009 page 769 of 1036 rej09b0254-0600 bit 14?cl1 (horizontal sync signal) polarity select (cl1pol): selects the polarity of the cl1 (horizontal sync signal) for the lcd module. bit 14 cl1pol description 0 cl1 pulse is high active (initial value) 1 cl1 pulse is low active bit 13?disp (display enable) polarity select (disppol): selects the polarity of the disp (display enable) for the lcd module. valid for tft panels only. bit 13 disppol description 0 disp is high active (initial value) 1 disp is low active bit 12?display data polarity select (dpol): selects the polarity of the lcdd (display data) for the lcd module. this bit supports inversion of the lcd module. bit 12 dpol description 0 lcdd is high active, transparent-type lcd panel (initial value) 1 lcdd is low active, can be used for reflective-type lcd panels bit 10?m signal control (mcnt): sets whether or not to output the lcd's current-alternating signal of the lcd module. valid for stn/dstn. bit 10 mcnt description 0 m (ac line modulation) signal is output (initial value) 1 m signal is fixed low
section 25 lcd controller rev.6.00 mar. 27, 2009 page 770 of 1036 rej09b0254-0600 bit 9?cl1 (horizontal sync signal) control (cl1cnt): sets whether or not to enable cl1 output during the ver tical retrace period. bit 9 cl1cnt description 0 cl1 is output during vertical retrace period (initial value) 1 cl1 is inactive during vertical retrace period bit 8?cl2 (data latch clock of lcd module) control (cl2cnt): sets whether or not to enable cl2 output during the vertical retrace period. bit 8 cl2cnt description 0 cl2 is output during vertical retrace period (initial value) 1 cl2 is inactive during vertical and horizontal retrace periods bits 5 to 0?module interface type select (miftyp5 to miftyp0): set the lcd panel type and data bus width for output to the lcd panel. there are three lcd panel types: stn, dstn, and tft. there are four data bus widths for output to the lcd panel: 4, 8, 12, and 16 bits. when the required data bus width for a tft panel is 16 bits or less, connect the lcdc and lcd panel according to the data bus size of the lcd panel. unlike in a tft panel, in an stn or dstn panel, the data bus width setting does not have a 1:1 correspondence with the number of display colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus can be used for 4 bpp. this is because the number of display colors in an stn or dstn panel is determined by how data is placed on the bus, and not by the bus width. for data specifications for an stn or dstn panel, see the specifications of the lcd panel used. the output data bus width should be set according to the mechanical interface specifi cations of the lcd panel. if an stn or dstn panel is selected, display control is performed using a 24-bit space- modulation frc (frame rate controller) consisting of the 8-bit r, g, and b included in the lcdc, regardless of the color and gradation settings. accordingly, the color and gradation specified by dspcolor is selected from 16 million colors in an stn or dstn panel. if a palette is used, the color specified in the palette is displayed.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 771 of 1036 rej09b0254-0600 bit 5 miftyp5 bit 4 miftyp4 bit 3 miftyp3 bit 2 miftyp2 bit 1 miftyp1 bit 0 miftyp0 description 0 0 0 0 0 0 stn monochrome 4-bit data bus module 1 stn monochrome 8-bit data bus module 1 0 0 0 stn color 4-bit data bus module 1 stn color 8-bit data bus module (initial value) 1 0 stn color 12-bit data bus module 1 stn color 16-bit data bus module 1 0 0 0 1 dstn monochrome 8-bit data bus module 1 1 dstn monochrome 16-bit data bus module 1 0 0 1 dstn color 8-bit data bus module 1 0 dstn color 12-bit data bus module 1 dstn color 16-bit data bus module 1 0 1 0 1 1 tft color 16-bit data bus module other than above reserved 25.2.3 lcdc data format register (lddfr) lddfr sets the bit alignment for pixel data in one byte and selects the data type and number of colors used for display so as to match the display driver software specifications. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? pabd ? dsp color 6 dsp color 5 dsp color 4 dsp color 3 dsp color 2 dsp color 1 dsp color 0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 r/w: r r r r r r r r/w r r/w r/w r/w r/w r/w r/w r/w bits 15 to 9 and 7?reserved
section 25 lcd controller rev.6.00 mar. 27, 2009 page 772 of 1036 rej09b0254-0600 bit 8?byte data pixel alignment (pabd): sets the pixel data alignment type in one byte of data. the contents of aligned data per pixel are the same regardless of this bit's setting. for example, data h'05 should be expressed as 0101 (binary) which is the normal style handled by a mov instruction of the SH7727 cpu, and should not be selected between 0101 (binary) and 1010 (binary). bit 8 pabd description 0 big endian for byte data (initial value) 1 little endian for byte data bits 6 to 0?display color select (dspcolor6 to dspcolor0): set the number of display colors for the display (0 is written to upper bits of for unpacked 4, 5, and 6 bpp). for display colors to which the description (via palette) is added below, the color set by the color palette is actually selected by the display data and displayed. bit 6 dsp color6 bit 5 dsp color5 bit 4 dsp color4 bit 3 dsp color3 bit 2 dsp color2 bit 1 dsp color1 bit 0 dsp color0 description 0 0 0 0 0 0 0 monochrome, 2 grayscales, 1 bpp (via palette) 1 monochrome, 4 grayscales, 2 bpp (via palette) 0 1 0 monochrome, 16 grayscales, 4 bpp (via palette) 1 0 0 monochrome, 64 grayscales, 6 bpp (via palette) 1 0 1 0 color, 16 colors, 4 bpp (via palette) 1 0 0 color, 256 colors, 8 bpp (via palette) 1 1 1 0 1 color, 32k colors (rgb: 555), 15 bpp 1 0 1 1 0 1 color, 64k colors (rgb: 565), 16 bpp other than above reserved note: the number of colors that can be selected in rotation mode is restricted by the display resolution. for details, see table 25. 3, in section 25.3, operation.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 773 of 1036 rej09b0254-0600 25.2.4 lcdc scan mode register (ldsmr) ldsmr selects whether or not to enable the hardware rotation function that is used to rotate the lcd panel, and sets the burst length for the system memory (vram) obtained for display. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? rot ? ? ? au1 au0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r/w r r r r/w r/w r r r r r r r r bits 15, 14, 12 to 10, and 7 to 0?reserved bit 13?rotation module select (rot): selects whether or not to rotate the display by hardware. note that the following restrictions are applied to rotation. ? an stn or tft panel must be used. a dstn panel is not allowed. ? the maximum horizontal (internal scan direction of the lcd panel) width of the lcd panel is 320. ? set a binary exponential that exceeds the displa y size in ldlaor. (for example, select 256 when a 320 240 panel is rotated to be used as a 240 320 panel and the horizontal width of the image is 240 bytes.) bit 13 rot description 0 not rotated (initial value) 1 rotated 90 degrees rightwards (left side of image is displayed on the upper side of the lcd module) bits 9 and 8?access unit select (au1 and au0): select the unit for accessing vram. this bit is valid only when the rot bit is set to 1 (rota tion is performed). when the rot bit is cleared to 0, 16-burst operation is perfor med regardless of the au bits. bit 9 au1 bit 8 au0 description 0 0 4-burst operation (initial value) 1 8-burst operation 1 0 16-burst operation 1 32-burst operation
section 25 lcd controller rev.6.00 mar. 27, 2009 page 774 of 1036 rej09b0254-0600 25.2.5 lcdc start address register fo r upper display data fetch (ldsaru) ldsaru sets the start address from which data is fetched by the lcdc for upper display of the lcdc panel. when a dstn panel is used, this re gister specifies the fetch start address for the upper side of the panel. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? sau25 sau24 sau23 sau22 sau21 sau20 sau19 sau18 sau17 sau16 initial value: 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sau15 sau14 sau13 sau12 sau11 sau10 sau9 sau8 sau7 sau6 sau5 sau4 sau3 sau2 sau1 sau0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 26?reserved bits 25 to 0?start address for upper display data fetch (sau31 to sau0): the start address for data fetch of the display data must be set within the synchronous dram area of area 3. notes: 1. when using the hardware rotation function (rot = 1), set the ldsaru value so that the upper-left address of the image is aligned with the 512-byte boundary. 2. when the hardware rotation function is used (rot = 1), set the upper-left address of the image which can be calculated from the display image size in this register. the equation below shows how to calculate the ldsaru value when the image size is 240 340 and ldlaor = 256. the ldsaru value is obtained not from the panel size but from the memory size of the image to be displayed. note that ldlaor must be a binary exponential at least as large as the horizontal width of the image. calculate backwards using the ldsaru value (ldsaru ? 256 (ldlaor value) (320 ? 1)) to ensure that the upper-left address of the image is aligned with the 512-byte boundary. ldsaru = (upper-left address of image) + 256 (ldlaor value) 319 (line)
section 25 lcd controller rev.6.00 mar. 27, 2009 page 775 of 1036 rej09b0254-0600 25.2.6 lcdc start address register fo r lower display data fetch (ldsarl) ldsarl sets the start address from which data is fetched by the lcdc for lower display of the lcd panel. when a dstn panel is used, this regist er specifies the fetch start address for the lower side of the panel. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? sal25 sal24 sal23 sal22 sal21 sal20 sal19 sal18 sal17 sal16 initial value: 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sal15 sal14 sal13 sal12 sal11 sal10 sal9 sal8 sal7 sal6 sal5 sal4 sal3 sal2 sal1 sal0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 31 to 26?reserved bits 25 to 0?start address for lower panel display data fetch (sal31 to sal0): the start address for data fetch of the display data must be set within the synchronous dram area of area 3. stn and tft: cannot be used dstn: start address for fetching displa y data corresponding to the lower panel note: the minimum alignment unit of ldsaru and ldsarl is four bytes. because the lcdc handles these values as longword data, the values written to the lower two bits of each register are always treated as 0. the lower two bits of each register are always read as 0. for 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits). (data at th e start of each line is always valid.) data that exceeds the longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. for 4, 8, 15, 16, or 32 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits).
section 25 lcd controller rev.6.00 mar. 27, 2009 page 776 of 1036 rej09b0254-0600 25.2.7 lcdc line address offset register for display data fetch (ldlaor) ldlaor sets the address width of the y-coordina tes increment used for lcdc to read the image recognized by the graphi cs driver. this register specifies how many bytes the address from which data is to be read should be moved when the y coordinates (vertical direction) have been incremented by 1. this register does not have to be equal to the horizontal width of the lcd panel. when the memory address of a point (x, y) in the two-dimensional image is calculated by ax + by+ c, this register becomes equal to b in this equation. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lao15 lao14 lao13 lao12 lao11 lao10 lao9 lao8 lao7 lao6 lao5 lao4 lao3 lao2 lao1 lao0 initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0?line address offset (ldlaor) notes: 1. the minimum alignment unit of ldlaor is four bytes. because the lcdc handles these values as longword data, the values written to the lower two bits of the register are always treated as 0. the lower two bits of the register are al ways read as 0. the initial values ( resolution = 640) will continuously and accurately place the vga (640 480 dots) display data without skipping an address between lines. for details, see table 25.3, in section 25.3, operation. 2. a binary exponential at least as large as the horizontal width of the image is recommended for the ldlaor value, taking into consideration the software operation speed. when the hardware rotation function is used (rot = 1), the ldlaor value should be a binary exponential (in this exampl e, 256) at least as large as the horizontal width of the image (after rotation, it becomes 240 in a 240 320 panel) instead of the horizontal width of the lcd panel (320 in a 320 240 panel).
section 25 lcd controller rev.6.00 mar. 27, 2009 page 777 of 1036 rej09b0254-0600 25.2.8 lcdc palette control register (ldpalcr) ldpalcr selects whether the cpu or lcdc acce sses the palette memory. when the palette memory is being used for display operation, display mode should be selected. when the palette memory is being written to, cpu access mode should be selected. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? pals ? ? ? palen initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r r r r r/w bits 15 to 5 and 3 to 1?reserved bit 4?palette state (pals): indicates the access right state of the palette. bit 4 pals description 0 display mode: lcdc uses the palette (initial value) 1 cpu access mode: the host (cpu) uses the palette bit 0?palette read/write enable (palen): controls cpu accesses to the palette. bit 0 palen description 0 display mode: lcdc uses the palette (initial value) 1 cpu access mode: the host (cpu) uses the palette
section 25 lcd controller rev.6.00 mar. 27, 2009 page 778 of 1036 rej09b0254-0600 25.2.9 palette data registers 00 to ff (ldpr00 to ldprff) these registers are for accessing palette data directly allocated (4 bytes 256 addresses) to the memory space. to access the palette memory, acce ss the corresponding register among this register group (ldpr00 to ldprff). each palette re gister is a 32-bit register including three 8-bit areas for r, g, and b. for details on the colo r palette specifications, see section 25.3.3, color palette specification. bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff initial value: * * * * * * * * * * * * * * * * r/w: r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff pal d00-ff initial value: * * * * * * * * * * * * * * * * r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined bits 31 to 24?reserved bits 18 to 16, 9, 8, and 2 to 0?reserved bits in palettes r, g, and b (though they cannot be changed, they are extended a ccording to the upper bits.) bits 23 to 19, 15 to 10, 7 to 3?palette data (pald00 to paldff): pald00: h'10008000 paldnn: (h'10008000+4 nn) paldff: h'100083fc
section 25 lcd controller rev.6.00 mar. 27, 2009 page 779 of 1036 rej09b0254-0600 25.2.10 lcdc horizontal character number register (ldhcnr) ldhcnr specifies the lcd module's horizontal size (in the scan direction) and the entire scan width including the horizontal retrace period. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hdcn7 hdcn6 hdcn5 hdcn4 hdcn3 hdcn2 hdcn1 hdcn0 htcn7 htcn6 htcn5 htcn4 htcn3 htcn2 htcn1 htcn0 initial value: 0 0 1 0 1 1 1 1 0 1 0 1 0 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8?horizontal di splay character number (hdcn): set the number of horizontal display characters (unit: character = 8 dots). subtract 1 from the setting (0 to 252 (h'fc)). example: for an lcd module with a width of 640 pixels hdcn = (640/8) ? 1 = 79 = h'4f bits 7 to 0?horizontal to tal character number (htcn): set the number of total horizontal characters (unit: character = 8 dots). subtr act 1 from the setting (3 to 255 (h'ff)). the minimum horizontal retrace peri od is three char acters (24 dots). the values set in hdcn and htcn must satisfy the relationship of htcn hdcn + 3. htcn should be set to an odd number value when using a color stn 16-bit i/f module. example: for an lcd module with a width of 640 pixels htcn = [(640/8) ? 1] + 3 = 82 = h'52
section 25 lcd controller rev.6.00 mar. 27, 2009 page 780 of 1036 rej09b0254-0600 25.2.11 lcdc horizontal sync signal register (ldhsynr) ldhsynr specifies the timing of the generation of the horizontal (scan direction) sync signals (cl1/hsync) for the lcd module. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hsyn w3 hsyn w2 hsyn w1 hsyn w0 ? ? ? ? hsynp 7 hsynp 6 hsynp 5 hsynp 4 hsynp 3 hsynp 2 hsynp 1 hsynp 0 initial value: 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 r/w: r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12?horizontal sy nc signal width (hsynw): sets the width in characters of the horizontal sync sign als (cl1 and hsync). subtract 1 from the setting (0 to 15 (h'f)). example: for a horizontal sync signal width of 8 dots hsynw = (8 dots/8 dots/character) ? 1 = 0 = h'0 bits 7 to 0?horizontal sync signal output position (hsynp): sets the output position in characters of the horizo ntal sync signals. subtract 1 from the setting (0 to 255 (h'ff)). the following conditions must be satisfied: htcn >= hsynp + hsynw + 1 hsynp >= hdcn + 1 example: for an lcd module with a width of 640 pixels hsynp = [(640/8) + 1] ? 1 = 80 = h'50 in this case, the horizontal sync signal is active from the 648th through the 655th dot.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 781 of 1036 rej09b0254-0600 25.2.12 lcdc vertical display line number register (ldvdlnr) ldvdlnr specifies the lcd module's vertical size (for both scan direction and vertical direction). for a dstn panel, specify an even numbe r at least as large as the lcd panel's vertical size regardless of the size of the up and down panels, e.g. 480 for a 640 480 panel. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? vdln 10 vdln 9 vdln 8 vdln 7 vdln 6 vdln 5 vdln 4 vdln 3 vdln 2 vdln 1 vdln 0 initial value: 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 r/w: r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 11?reserved bits 10 to 0?vertical display line number (vdln): set the number of vertical display lines (unit: line). subtract 1 from the setting (0 to 2047 (h'7ff)). example: for an 480-line lcd module vdln = 480 ? 1 = h'1df
section 25 lcd controller rev.6.00 mar. 27, 2009 page 782 of 1036 rej09b0254-0600 25.2.13 lcdc vertical total li ne number register (ldvtlnr) ldvtlnr specifies the lcd panel's entire vertical size including the vertical retrace period. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? vtln 10 vtln 9 vtln 8 vtln 7 vtln 6 vtln 5 vtln 4 vtln 3 vtln 2 vtln 1 vtln 0 initial value: 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 r/w: r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 11?reserved bits 10 to 0?vertical total line number (vtln): set the total number of vertical display lines (unit: line). subtract 1 from the setting (1 to 2047 (h'7ff)). the minimum for the total number of vertical lines is 2 lines. the following conditions must be satisfied: vtln >= vdln, vtln >= 1 example: for an 480-line lcd module an d a vertical retrace period of 0 lines vtln = (480 + 0) ? 1 = 479 = h'1df
section 25 lcd controller rev.6.00 mar. 27, 2009 page 783 of 1036 rej09b0254-0600 25.2.14 lcdc vertical sync signal register (ldvsynr) ldvsynr specifies the timing of the generation of the vertical (scan direction and vertical direction) sync signals (flm/vsync) for the lcd module. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vsyn w3 vsyn w2 vsyn w1 vsyn w0 ? vsynp 10 vsynp 9 vsynp 8 vsynp 7 vsynp 6 vsynp 5 vsynp 4 vsynp 3 vsynp 2 vsynp 1 vsynp 0 initial value: 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 r/w: r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 11?reserved bits 15 to 12?vertical sy nc signal width (vsynw): set the width of the vertical sync signals (flm and vsync) (unit: line). subtract 2 from the setting (0 to 15 (h'f)). example: for a vertical sync signal width of 1 line vsynw = (1 ? 1) = 0 = h'0 bits 10 to 0? vertical sync signal output position (vsynp): set the output position of the vertical sync signals (flm and vsync) (unit: line). subtract 2 from the setting (0 to 2046 (h'7fe)). dstn should be set to an odd number value. it is handled as (setting value + 1)/ 2. example: for an 480-line lcd module and a verti cal retrace period of 0 lines (in other words, vtln = 479 and the vertical sync signal is active for the first line): ? single display vsynp=[(1-1)+vtln] mod (vtln+1) = [(1-1)+479] mod (479+1) = 479 mod 480 = 479 = h'1df ? dual displays vsynp=[(1-1) 2+vtln] mod (vtln+1) = [(1-1) 2+479] mod (479+1) = 479 mod 480 = 479 = h'1df
section 25 lcd controller rev.6.00 mar. 27, 2009 page 784 of 1036 rej09b0254-0600 25.2.15 lcdc ac modulation signal to ggle line number register (ldaclnr) ldaclnr specifies the timing to toggle the ac modulation signal (lcd current-alternating signal) of the lcd module. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? acln 4 acln3 acln2 acln1 acln0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 r/w: r r r r r r r r r r r r/w r/w r/w r/w r/w bits 15 to 5?reserved bits 4 to 0?ac line number (acln): set the line number where the lcd current-alternating signal of the lcd module is toggled (unit: line). subtract 1 from the setting (0 to 31 (h'1f)). note: when the total line number of the lcd panel is even, set an even number so that toggling is performed at an odd line. example: for toggling every 13 lines acln = 13 ? 1 = 12 = h'0c 25.2.16 lcdc interrupt control register (ldintr) ldintr specifies where to star t the vsync interrupt (lcdci). bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? vint sel ? ? ? vinte ? ? ? ? ? ? ? vints initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r/w r r r r/w r r r r r r r r/w bits 15 to 13, 11 to 9, and 7 to 1?reserved
section 25 lcd controller rev.6.00 mar. 27, 2009 page 785 of 1036 rej09b0254-0600 bit 12?vsync interrupt select (vintsel): sets the starting point of the lcdc?s vsync interrupt. bit 12 vintsel description 0 vsync interrupt is generated at starting point of vertical retrace period for memory access (initial value) 1 vsync interrupt is generated at starting point of vertical retrace period for lcd display bit 8?vsync interrupt enable (vinte): sets whether or not to enable lcdc?s vsync interrupts. bit 8 vinte description 0 vsync interrupts are disabled (initial value) 1 vsync interrupts are enabled bit 0?vsync interrupt state (vints): indicates the lcdc?s vsync interrupt handling state. this bit is set to 1 at the time a vsync interrupt is generated. during the vsync interrupt handling routine, this bit should be cleared by writing 0 to it. bit 0 vints description 0 lcdc did not generate a vsync interrupt or has been informed that the generated vsync interrupt has completed (initial value) 1 lcdc has generated a vsync interrupt and has not yet been informed that the generated vsync interrupt has completed notes: ? interrupt handling flow: 1. an interrupt signal is input to the cpu. 2. the cpu reads from vints. 3. if vints is set to 1, a vsync interrupt has occurred, and the vsync interrupt handling is carried out. 4. if vints is cleared to 0, no vsync interrupt has occurred and another processing is carried out. ? when vsync interrupts are enabled, the vinte bit must be set to 1 before the don bit is set to 1, and the vinte bit must not be cleared to 0.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 786 of 1036 rej09b0254-0600 left border h addressable video right border front porch vsync time top border v addressable video bottom border front porch h total time v total time back porch back porch hsync signal vsync signal active video = top/left border + addressable video + bottom/right border total h blank = hsync time + back porch + front porch total v blank = vsync time + back porch + front porch htcn = h total time hdcn = h addressable video hsynp = h addressable video + right border + front porch hsynw = hsync time vtln = v total time cdln = v addressable video vsynp = v addressable video + bottom border + front porch vsynw = vsync time hsync time figure 25.2 valid display and retrace period 25.2.17 lcdc power management mode register (ldpmmr) ldpmmr controls the power supply circuit that provides power to the lcd module. the usage of two types of power-supply control pins, vcpwc and vepwc, and turning on or off the power supply are selected. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 onc3 onc2 onc1 onc0 offd3 offd2 offd1 offd0 ? vcpe vepe done ? ? lps1 lps0 initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r r r r
section 25 lcd controller rev.6.00 mar. 27, 2009 page 787 of 1036 rej09b0254-0600 bits 7, 3, and 2?reserved bits 15 to 12?lcdc power- on sequence period (onc): set the period from vepwc assertion to don assertion in the power-on sequence of the lcd module in frame units. this period is the (c) period in figures 25.4 to 25.7. for details on setting this register, see table 25.4. (the setting method is common for onc, on a, onb, offd, offe, and offf.) 1 is to be subtracted from the setting. bits 11 to 8?lcdc power- off sequence period (offd): set the period from don negation to vepwc negation in the power-off sequence of the lcd module in frame units. this period is the (d) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. bit 6?vcpwc pin enable (vcpe): sets whether or not to enable a power-supply control sequence using the vcpwc pin. bit 6 vcpe description 0 disabled: vcpwc pin is masked and fixed low (initial value) 1 enabled: vcpwc pin output is asserted and negated according to the power-on or power-off sequence bit 5?vepwc pin enable (vepe): sets whether or not to enable a power-supply control sequence using the vepwc pin. bit 5 vepe description 0 disabled: vepwc pin is masked an d fixed low (initial value) 1 enabled: vepwc pin output is asserted and negated according to the power-on or power-off sequence bit 4?don pin enable (done): sets whether or not to enable a power-supply control sequence using the don pin. bit 4 done description 0 disabled: don pin is masked and fixed low 1 enabled: don pin output is asserted and negated according to the power-on or power- off sequence (initial value)
section 25 lcd controller rev.6.00 mar. 27, 2009 page 788 of 1036 rej09b0254-0600 bits 1 and 0?lcd module power-suppl y input state (lps1 and lps0): indicate the power- supply input state of the lcd module when using the power-supply control function. bit 1 lps1 bit 0 lps0 description 0 0 lcd module power off (initial value) 1 1 lcd module power on 25.2.18 lcdc power-supply sequence period register (ldpspr) ldpspr controls the power supply circuit that provides power to the lcd module. the timing to start outputting the timing signals to the vepwc and vcpwc pins is specified. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ona3 ona2 ona1 ona0 onb3 onb2 onb1 onb0 offe3 offe2 o ffe1 offe0 offf3 offf2 offf1 offf0 initial value: 1 1 1 1 0 1 1 0 0 0 0 0 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12?lcdc power- on sequence period (ona): set the period from vcpwc assertion to starting output of the display data (lcdd) and timing signals (flm, cl1, cl2, and m/disp) in the power-on sequence of the lcd module in frame units. this period is the (a) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. bits 11 to 8?lcdc power-on sequence period (onb): set the period from starting output of the display data (lcdd) and timing signals (flm, cl1, cl2, and disp/m) to the vepwc assertion in the power-on sequence of the lcd module in frame units. this period is the (b) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. bits 7 to 4?lcdc power-of f sequence period (offe): set the period from vepwc negation to stopping output of the display data (lcdd) and timing signals (flm, cl1, cl2, and disp/m) in the power-off sequence of the lcd module in frame units. this period is the (e) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting. bits 3 to 0?lcdc power-off sequence period (offf): set the period from stopping output of the display data (lcdd) and timing signa ls (flm, cl1, cl2, and disp/m) to vcpwc negation to in the power-off sequence of the lcd module in frame units. this period is the (f) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 789 of 1036 rej09b0254-0600 25.2.19 lcdc control register (ldcntr) ldcntr specifies start and st op of display by the ldcd. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? don2 ? ? ? don initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r r r r r r r r r r r r/w r r r r/w bits 15 to 1?reserved bit 4? display start auxiliary bit (don2): specifies the start of display operation using lcdc. lcdc operation cannot be guaranteed if 0 is written to this bit at any time other than the start of display operation. note that a 1 written to this bit is automatically cleared to 0, so it is not necessary to write 0 to it in order to clear it. bit 0?display on (don): specifies the start and stop of the lcdc display operation. the control sequence state can be checked by refe rencing the lps value in bit 0 of the lcdc power management mode register (ldpmmr). bit 4 don2 bit 0 don description 0 0 display-off mode: lcdc is stopped (initial value) 1 1 display-on mode: lcdc operates starting lcdc display operation (don2 and don bits change from b'00 to b'11): 1. start lcdc operation. 2. turn on the lcd module following the sequence set in the lcdc power management mode register (ldpmmr) and lcdc control register (ldcntr). the sequence ends when the lps value changes from b'00 to b'11. do not make any action to the don bit until the sequence ends. stopping lcdc display operation (don2 and don bits change from b'01 to b'00): 1. turn off the lcd module following the sequence set in the lcdc power management mode register (ldpmmr) and lcdc control register (ldcntr). 2. stop lcdc operation. the sequence ends when the lps value changes from b'11 to b'00. do not make any action to the don bit until the sequence ends.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 790 of 1036 rej09b0254-0600 25.3 operation 25.3.1 lcd module sizes which ca n be displayed in this lcdc this lcdc is capable of controlling displays with up to 1024 1024 dots and 16 bpp (bits per pixel). the image data for display is stored in system memory, which is shared with the cpu. this lcdc should read the data from system memory between display periods. the SH7727 has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although a complete breakdown of the display is unlikely, there may be some problems with the display depending on the combination. the bus-occupancy rate described below should not, as a rule, exceed 40 % . bus-occupancy rate ( % ) = overhead coefficient total number of display pixels ((hdcn + 1) 8 (vdln + 1)) frame rate (hz) number of colors (bpp) 100 ckio (hz) bus width (bits) the overhead coefficient depends on the bus used by the sdram in cl2, as indicated below. if the hardware rotation function is not used (rot = 0), the overhead coefficient is 1.375 if a 32- bit bus is used and 1.188 if a 16-bit bus is used. if the hardware rotation function is used (rot = 1), the overhead coefficient is determined by the access unit select (au) setting an d the bus width, as follows. access unit select (au) setting 32-bit bus 16-bit bus 4-burst operat ion 2.500 1.750 8-burst operat ion 1.750 1.375 16-burst operation 1.375 1.188 32-burst operation 1.188 1.094
section 25 lcd controller rev.6.00 mar. 27, 2009 page 791 of 1036 rej09b0254-0600 25.3.2 limits on the resolution of rotated displays, burst length, and connected memory (sdram) this lcdc is capable of displaying a landscape-format image on a lcd module by rotating a portrait format image for display by 90 degrees. only the numbers of colors for each resolution are supported as shown in tables 25.3 and 25.4. the size of the sdram (the number of column address bits) and its burst length are lim ited to read the sdram continuously. the number of colors for displa y, sdram column addresses, and lcdc burst length are shown table 25.3 and 25.4. a monochromatic lcd module is necessary for the display of images in the above monochromatic formats. a color lcd module is n ecessary for the display of images in the above color formats.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 792 of 1036 rej09b0254-0600 table 25.3 limits on the re solution of rotated displays, burst length, and connected memory (32-bit bus sdram) image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 240 320 320 240 monochrome 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (packed) 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 4 bpp (unpacked) 10 bits not more than 16 bursts 6 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts color 8 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts 16 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts 234 320 320 234 monochrome 6 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts color 16 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts
section 25 lcd controller rev.6.00 mar. 27, 2009 page 793 of 1036 rej09b0254-0600 image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 80 160 160 80 monochrome 2 bpp 8 bits ? 9 bits ? 10 bits ? 8 bits not more than 16 bursts 4 bpp (packed) 9 bits ? 10 bits ? 8 bits not more than 8 bursts 4 bpp (unpacked) 9 bits not more than 16 bursts 10 bits ? 6 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? color 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 8 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? 16 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts
section 25 lcd controller rev.6.00 mar. 27, 2009 page 794 of 1036 rej09b0254-0600 image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 64 128 128 64 monochrome 1 bpp 8 bits ? 9 bits ? 10 bits ? 2 bpp 8 bits ? 9 bits ? 10 bits ? 8 bits ? 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (unpacked) 10 bits ? 6 bpp 8 bits not more than 16 bursts 9 bits ? 10 bits ? color 8 bits ? 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (unpacked) 10 bits ? 8 bpp 8 bits not more than 16 bursts 9 bits ? 10 bits ? n ote: * specify the data of the number of line specified as burst length can be stored in address of sdram same as that of row.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 795 of 1036 rej09b0254-0600 table 25.4 limits on the re solution of rotated displays, burst length, and connected memory (16-bit bus sdram) image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 240 320 320 240 monochrome 8 bits not more than 4 bursts 9 bits not more than 8 bursts 4 bpp (packed) 10 bits not more than 16 bursts 8 bits unusable 9 bits 4 bursts 4 bpp (unpacked) 10 bits not more than 8 bursts 6 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts color 8 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts 16 bpp 8 bits unusable 9 bits unusable 10 bits 4 bursts 234 320 320 234 monochrome 6 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts color 16 bpp 8 bits unusable 9 bits unusable 10 bits 4 bursts
section 25 lcd controller rev.6.00 mar. 27, 2009 page 796 of 1036 rej09b0254-0600 image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 80 160 160 80 monochrome 2 bpp 8 bits not more than 16 bursts 9 bits ? 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (packed) 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 4 bpp (unpacked) 10 bits not more than 16 bursts 6 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts color 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (packed) 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 4 bpp (unpacked) 10 bits not more than 16 bursts 8 bpp 8 bits 4 bursts 9 bits not more than 8 bursts 10 bits not more than 16 bursts 16 bpp 8 bits unusable 9 bits 4 bursts 10 bits not more than 8 bursts
section 25 lcd controller rev.6.00 mar. 27, 2009 page 797 of 1036 rej09b0254-0600 image for display in memory (x-resolution y-resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 64 128 128 64 monochrome 1 bpp 8 bits ? 9 bits ? 10 bits ? 2 bpp 8 bits ? 9 bits ? 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 6 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? color 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 8 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? note: * specify the data of the number of line specified as burst length can be stored in address of sdram same as that of row. 25.3.3 color palette specification color palette register : this lcdc has a color palette which outputs 24 bits of data per entry and is able to simultaneously hold 256 entries. the color palette thus allows the simultaneous display of 256 colors chosen from among 16-m colors. the below procedure may be used to set up color palettes at any time.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 798 of 1036 rej09b0254-0600 1. the palen bit in the lcdc color palette regi ster is 0 (initial value); normal display operation 2. access ldpalcr and set the palen bit to 1; enter color-palette setting mode 3. access ldpalcr and confirm that the pals bit is 1. 4. access ldpr00 to ldprff and write the re quired values to the pald00 to paldff bits. 5. access ldpalcr and clear the palen bit to 0; return to normal display mode 0 is output on the lcdc display data output (lcdd) while the controller is in color palette setting mode. 0 7 15 23 31 color monochrome b0 b1 b2 b3 b4 b5 b6 b7 g0 g1 g2 g3 g4 g5 g6 g7 r0 r1 r2 r3 r4 r5 r6 r7 m0 m1 m2 m3 m4 m5 m6 m7 figure 25.3 color-palette data format paldnn color and gradation data should be set as above, using 256-gradation values for r, g, b, and m. for a color display, paldnn [23:16], paldnn [15:8], and paldnn [7:0] respectively hold the r, g, and b data. although the bits paldnn [18:16], paldnn [9:8], and paldnn [2:0] exist, no memory is associated with these bits. paldnn [18:16], paldnn [9:8], and paldnn [2:0] are thus not available for storing palette data. the numbe rs of valid bits are thus r: 5, g: 6, and b: 5.24-bit (r: 8 bits, g: 8 bits, and b: 8 bits) data should, however, be written to the palette-data registers. when the values for paldnn [23:19], paldnn [15:10], or paldnn [7:3] are not 0, 1s should be written to paldnn [18: 16], paldnn [9:8], or paldnn [2:0], respectively. when the values of paldnn [23:19], paldnn [15:10], or paldnn [7:3] are 0, 0 should be written to paldnn [18:16], paldnn [9:8], or paldnn [2:0], respectively. then 24 bits are extended. grayscale data for a monochromatic display should be set in paldnn [7:3]. paldnn [23:8] are all ?don?t care?. when the value in paldnn [7:3] is not 0, 1s should be written to paldnn [2:0]. when the value in paldnn [7:3] is 0, 0s shoul d be written to paldnn [2:0]. then 8 bits are extended.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 799 of 1036 rej09b0254-0600 25.3.4 data format 1. packed 1bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb top left pixel p00 p08 p01 p02 p03 p04 p05 p06 p07 p10 p18 p11 p12 p13 p14 p15 p16 p17 76543210 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display memory 4. packed 1bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p07 p08 p06 p05 p04 p03 p02 p01 p00 p17 p18 p16 p15 p14 p13 p12 p11 p10 76543210 display memory 2. packed 2bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 76543210 display memory 3. packed 4bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p02 p03 p00 p01 p02 p03 p04 p05 p04 p05 76543210 display memory display pn: put 1bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn: put 1bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn=pn[1:0]: put 2bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn=pn[3:0]: put 4bit data lao: line address offset ? unused bits should be 0
section 25 lcd controller rev.6.00 mar. 27, 2009 page 800 of 1036 rej09b0254-0600 5. packed 2bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p03 p02 p01 p00 p07 p06 p05 p04 p13 p12 p11 p10 p17 p16 p15 p14 76543210 display memory 6. packed 4bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p01 p00 p04 p03 p11 p10 p13 p12 p06 p05 p15 p14 76543210 display memory 7. unpacked 4bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory 8. unpacked 5bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[1:0]: put 2bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[3:0]: put 4bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[3:0]: put 4bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[4:0]: put 5bit data lao: line address offset ? unused bits should be 0
section 25 lcd controller rev.6.00 mar. 27, 2009 page 801 of 1036 rej09b0254-0600 9. unpacked 6bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory 10. packed 8bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory 11. unpacked color 15bpp (rgb 555) [windows ce recommended format] address +00 +02 +04 +06 +lao +lao+02 +lao+04 +lao+06 [bit] (word0) (word2) (word4) msb lsb p00r p01r p10r p11r p02r p12r p00g p01g p10g p11g p02g p12g p00b p01b p10b p11b p02b p12b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 display memory 12. packed color 16bpp (rgb 565) [windows ce recommended format] address +00 +02 +04 +06 +lao +lao+02 +lao+04 +lao+06 [bit] (word0) (word2) (word4) msb lsb p00r p01r p10r p11r p02r p12r p00g p01g p10g p11g p02g p12g p00b p01b p10b p11b p02b p12b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 display memory top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[5:0]: put 6bit data lao: line address offset ? unused bits should be 09 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[7:0]: put 8bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display prr = prr[4.0]. pr 5bit red data prg = prg[4.0]. pr 5bit green data prb = prb[4.0]. pr 5bit blue data pr = (prr, prg, prb). pr 15bit data lao: line address offset ? unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display prr = prr[4.0]. pr 5bit red data prg = prg[5.0]. pr 6bit green data prb = prb[4.0]. pr 5bit blue data pr = (prr, prg, prb). pr 16bit data lao: line address offset ? unused bits should be 0
section 25 lcd controller rev.6.00 mar. 27, 2009 page 802 of 1036 rej09b0254-0600 25.3.5 timing controller register the timing controller register is used to run th e controller in a way that matches the display resolution of the lcd module. the display resolution is set up in the lcdc horizontal number character number register, lcdc ho rizontal synchronization signal register, lcdc vertical line displayed number register, lcdc vertical to tal line number register, and lcdc vertical synchronization signal register. the lcd current-alternating period for an stn or dstn display is set by using the lcdc ac modulation signal to ggle line number register. the initial values in these registers are typical settings for vga (640 480 dots) on an stn or dstn display. the clock to be used is set with the lcd input clock register. the lcd module frame rate is determined by the display interval + retrace line in terval (non-display inte rval) for one screen set in a size related register and the frequency of the clock used. this lcdc has a v sync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the display). this function is set up by using the lcdc interrupt control register. 25.3.6 power man agement registers an lcd module normally requires a specific sequence for processing to do with the cutoff of the input power supply. settings in the lcdc power management mode register, lcdc power supply sequence period register, and lcdc control register, in conjunction with the lcd power-supply control pins (vcpwc, vepwc, and don), are used to provide processing of power-supply control sequences that suits the requirements of the lcd module. figures 25.4 to 25.7 are summary timing charts for power-supply control sequences and table 25.5 is a summary of available power -supply control sequence periods.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 803 of 1036 rej09b0254-0600 start power supply start power cutoff arbitrary undefined undefined 00b 00b 11b (a) 0 frame (b) 1 frame (c) 1 frame (e) 1 frame (d) 1 frame (f) 0 frame lcd module active lcd module stopped lcd module stopped vcpe = on (1) stn, dstn power-supply control vepe = on done = on (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) don pin register control sequence figure 25.4 power-supply control se quence and states of the lcd module 00b 00b 11b (a) 0 frame (b) 0 frame (c) 1 frame (d) 1 frame (f) 0 frame (e) 0 frame vcpe = off vepe = off done = on start power supply start power cutoff arbitrary undefined undefined lcd module active lcd module stopped lcd module stopped (internal signal) (internal signal) (2) power-supply control for lcd panels other than stn or dstn (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) don pin register control sequence figure 25.5 power-supply control se quence and states of the lcd module
section 25 lcd controller rev.6.00 mar. 27, 2009 page 804 of 1036 rej09b0254-0600 vcpe = on (3) power-supply control for tft panels vepe = on done = off 00b 00b 11b (b) 6 frame (c) 0 frame (d) 0 frame (internal signal) undefined start power supply start power cutoff arbitrary undefined (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) don pin register control sequence lcd module active lcd module stopped lcd module stopped (e) 1 frame (f) 1 frame (a) 1 frame figure 25.6 power-supply control se quence and states of the lcd module 00b 00b 11b (a) 0 frame (b) 0 frame (c) 0 frame (d) 0 frame (e) 0 frame (f) 0 frame vcpe = off (4) power supply control for lcd panels other than tft vepe = off done = off (internal signal) (internal signal) (internal signal) start power supply start power cutoff arbitrary undefined undefined (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) don pin register control sequence lcd module active lcd module stopped lcd module stopped figure 25.7 power-supply control se quence and states of the lcd module
section 25 lcd controller rev.6.00 mar. 27, 2009 page 805 of 1036 rej09b0254-0600 table 25.5 available power-supply control- sequence periods at typical frame rates frame rate onx, offx register value 120 hz 60 hz h?f ( ? 1+1)/120 = 0.00 (ms) ( ? 1+1)/60 = 0.00 (ms) h?0 (0+1)/120 = 8.33 (ms) (0+1)/60 = 16.67 (ms) h?1 (1+1)/120 = 16.67 (ms) (1+1)/60 = 33.33 (ms) h?2 (2+1)/120 = 25.00 (ms) (2+1)/60 = 50.00 (ms) h?3 (3+1)/120 = 33.33 (ms) (3+1)/60 = 66.67 (ms) h?4 (4+1)/120 = 41.67 (ms) (4+1)/60 = 83.33 (ms) h?5 (5+1)/120 = 50.00 (ms) (5+1)/60 = 100.00 (ms) h?6 (6+1)/120 = 58.33 (ms) (6+1)/60 = 116.67 (ms) h?7 (7+1)/120 = 66.67 (ms) (7+1)/60 = 133.33 (ms) h?8 (8+1)/120 = 75.00 (ms) (8+1)/60 = 150.00 (ms) h?9 (9+1)/120 = 83.33 (ms) (9+1)/60 = 166.67 (ms) h?a (10+1)/120 = 91.67 (ms) (10+1)/60 = 183.33 (ms) h?b (11+1)/120 = 100.00 (ms) (11+1)/60 = 200.00 (ms) h?c (12+1)/120 = 108.33 (ms) (12+1)/60 = 216.67 (ms) h?d (13+1)/120 = 116.67 (ms) (13+1)/60 = 233.33 (ms) h?e (14+1)/120 = 125.00 (ms) (14+1)/60 = 250.00 (ms) ona, onb, onc, offd, offe, and offf are used to set the power-supply control-sequence periods, in units of frames, from 0 to 15. 1 is subtracted from each register. h?0 to h?e settings select from 1 to15 frames. th e setting h?f selects 0 frames. actual sequence periods depend on the register values and the frame frequency of the display. the following table gives power-supply control-sequence periods for display frame frequencies used by typical lcd modules. when onb is set to 6h and display?s frame frequency is 120 hz: the display?s frame frequency is 120 hz. 1 frame period is thus 8.33 (ms) = 1/120 (sec). the power-supply input sequence period is 7 fra mes because onb setting is subtracted by 1. as a result, the sequence period is 58.33 (ms) = 8.33 (ms) 7.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 806 of 1036 rej09b0254-0600 table 25.6 lcdc operating modes mode function display on (lcdc active) register setting: don = 1 don = 2 fixed resolution, the format of the data for display is determined by the number of colors, timing signals are output to the lcd module. display off (lcdc stopped) register setting: don = 0 don2 = 0 register access is enabled. fixed resolution, the format of the data for display is determined by the number of colors, timing signals are not output to the lcd module. table 25.7 lcd module power-supply states (stn, dstn module) state power supply for logic display data, timing signal power supply for high-voltage systems don signal control pin vcpwc cl2, cl1, flm, m/disp, lcd vepwc don operating state supply supply supply supply supply supply supply supply supply (transitional state) supply stopped state (tft module) state power supply for logic display data, timing signal power supply for high-voltage systems control pin vcpwc cl2, cl1, flm, m/disp, lcd vepwc operating state supply supply supply supply supply (transitional state) supply stopped state
section 25 lcd controller rev.6.00 mar. 27, 2009 page 807 of 1036 rej09b0254-0600 the above table shows the states of the power supply, display data, and timing signals for the typical lcd module in its active and stopped states. some of the supply voltages described may not be necessary, because some modules internally generate the power supply required for high- voltage systems from the logic-level power-supply voltage. notes on display-off mode (lcdc stopped): if lcd-module power-supply control-sequence processing is in use by the lcdc or the supply of power is cut off while the lcdc is in its display-on mode, normal operation is not guaranteed. in the worst case, the connected lcd module may be damaged. 25.3.7 operation fo r hardware rotation operation in hardware-rotation mode is describe d below. hardware-rotation mode can be thought of as using a landscape-format lcd panel instead of a portrait-format lcd panel by placing the landscape-format lcd panel as if it were a portra it-format panel. whether the panel is intended for use in landscape or portrait format is thus no problem. the panel must, however, be within 320 pixels wide. when making settings for hardware rotation, the following five differences from the setting for no hardware rotation must be noted. (the following example is for a display at 8 bpp. at 16 bpp, the amount of memory per dot will be doubled. the im age size and register values used for rotation will thus be different.) 1. the image data must be prepared for display in the rotated panel. (if 240 320 pixels will be required after rotation, 240 320 pixel image data must be prepared.) 2. the register settings for the address of the image data must be changed (ldsaru and ldlaor). 3. ldlaor should be power of 2 (when the horizontal width after rotation is 240 pixels, ldlaor should be set to 256). 4. graphics software should be set up for the number 3 setting. 5. ldsaru should be changed to represent the address of the data for the lower-left pixel of the image rather than of the data for the upper-left pixel of the image.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 808 of 1036 rej09b0254-0600 picture image ldsaru (start point) ldsaru + ldlaor ? 1 scanning starts from ldsaru. scanning is done from small address to large address of x coordination. ldsaru + ldlaor ldvdlnr ? 1(end point) picture image picture image lcd panel start point end point 1) normal mode for example, the registers have been set up for th e display of image data in landscape format (320 240), which starts from ldsaru = 0x0c001000, on a 320 240 lcd panel. the graphics driver software is complete. some changes are required to apply hardware rotation and use the panel as a 240 320 display. if ldlaor is 512, the graphics driver software uses this power of 2 as the offset for the calculation of the addresses of y coordinates in the image data. before setting rot to 1, the image data must be redrawn to suit the 240 320 lcd panel. ldlaor will then be 256 because the size has changed and the graphics driver software must be altered accordingly. the point that corresponds to ldsaru moves from th e upper left to the lower left of the display, so ldsaru should be changed to 0x0c001000 + 256 * 319. note: hardware rotation allows the use of an lcd panel that has been rotated by 90 degrees. the settings in relation to the lcd panel should match the settings for the lcd panel before rotation. rotation is possible regardless of the drawing processing carried out by the graphics driver software. however, the sizes in the image data and address offset values which are managed by the graphics driver software must be altered.
section 25 lcd controller rev.6.00 mar. 27, 2009 page 809 of 1036 rej09b0254-0600 picture image ldsaru (start point) ldsaru ? ldlaor (hdcn 8 ? 2) ? 1(end point) scanning starts from ldsaru. scanning is done from large address to small address of y coordination. lcd panel start point end point 2) rotation mode 25.4 clock and lcd data signal examples dot clk 1) stn monochrome 4-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 lcd5 to 15 low figure 25.8 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 810 of 1036 rej09b0254-0600 dotclock 2) stn monochrome 8-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 lcd8 to 15 low lcd4 lcd5 lcd6 lcd7 b12 b13 b14 b15 figure 25.9 clock and lcd data signal example dotclock 3) stn color 4-bit data bus module cl2 r0 g0 b0 r1 lcd4 to 15 low lcd0 lcd1 lcd2 lcd3 g1 b1 r2 g2 b2 r3 g3 b3 r4 g4 b4 r5 g5 b5 r6 g6 b6 r7 g7 b7 r8 g8 b8 r9 g9 b9 r10 g10 b10 r11 g11 b11 b14 r15 g15 b15 r12 g12 b12 r13 g13 b13 r14 g14 figure 25.10 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 811 of 1036 rej09b0254-0600 dotclock 4) stn color 8-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 r0 g0 b0 r1 g1 r2 g2 lcd8 to 15 low lcd4 lcd5 lcd6 lcd7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 figure 25.11 clock and lcd data signal example dotclock 5) stn color 12-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 r0 g0 b0 r1 g1 r2 g2 lcd12 to 15 low lcd4 lcd5 lcd6 lcd7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 lcd8 lcd9 lcd10 lcd11 figure 25.12 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 812 of 1036 rej09b0254-0600 dotclock 6) stn color 16-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 r0 g0 b0 r1 g1 r2 g2 lcd4 lcd5 lcd6 lcd7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 figure 25.13 clock and lcd data signal example dotclock 7) dstn monochrome 8-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 ub0 ub1 ub2 ub3 lb0 lb1 lb2 lb3 ub4 ub5 ub6 ub7 lcd8 to 15 low lcd4 lcd5 lcd6 lcd7 lb4 lb5 lb6 lb7 figure 25.14 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 813 of 1036 rej09b0254-0600 dotclock 8) dstn monochrome 16-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 lcd4 lcd5 lcd6 lcd7 ub0 ub1 ub2 ub4 ub5 ub3 ub7 ub6 lb0 lb1 lb2 lb3 lb5 lb6 lb4 lb7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 figure 25.15 clock and lcd data signal example dotclock 9) dstn color 8-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 ur0 ug0 ub0 ur1 ug1 ur2 ug2 lcd8 to 15 low lcd4 lcd5 lcd6 lcd7 ub1 ub2 ur3 ug3 ur4 ug4 ub3 ur5 ub4 ug5 ub5 ur6 ug6 ur7 ug7 ub6 ub7 lr0 lg0 lb0 lr1 lg1 lr2 lg2 lb1 lb2 lr3 lg3 lr4 lg4 lb3 lr5 lb4 lg5 lb5 lr6 lg6 lr7 lg7 lb6 lb7 figure 25.16 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 814 of 1036 rej09b0254-0600 dotclock 10) dstn color 12-bit data bus module cl2 lcd8 lcd9 lcd10 lcd11 ur0 ug0 ub0 ur1 ur2 ug2 ub2 ur3 ur4 ug4 ub4 ur5 ur6 ug6 ub6 ur7 lcd12 to 15 low lcd4 lcd5 lcd6 lcd7 ug1 ub1 lr0 lg0 ug3 ub3 lr2 lg2 ug5 ub5 lr4 lg4 ug7 ub7 lr6 lg6 lcd0 lcd1 lcd2 lcd3 lb0 lr1 lg1 lb1 lb2 lr3 lg3 lb3 lb4 lr5 lg5 lb5 lb6 lr7 lg7 lb7 figure 25.17 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 815 of 1036 rej09b0254-0600 dotclock 11) dstn color 16-bit data bus module cl2 lcd0 lcd1 lcd2 lcd3 ur0 ug0 ub0 ur1 ug1 ur2 ug2 lcd4 lcd5 lcd6 lcd7 ub1 ub2 ur3 ug3 ur4 ug4 ub3 ur5 ub4 ug5 ub5 ur6 ug6 ur7 ug7 ub6 ub7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 lr0 lg0 lb0 lr1 lg1 lr2 lg2 lb1 lb2 lr3 lg3 lr4 lg4 lb3 lr5 lb4 lg5 lb5 lr6 lg6 lr7 lg7 lb6 lb7 figure 25.18 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 816 of 1036 rej09b0254-0600 dotclock 12) tft color 16-bit data bus module cl2 lcd0 lcd1 lcd2 b01 b02 b03 b04 lcd3 lcd4 lcd5 lcd6 b05 lcd7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 g00 g01 g02 g03 g04 g05 r01 r02 r03 r04 r05 b11 b12 b13 b14 b15 g10 g11 g12 g13 g14 g15 r11 r12 r13 r14 r15 b21 b22 b23 b24 b25 g20 g21 g22 g23 g24 g25 r21 r22 r23 r24 r25 b31 b32 b33 b34 b35 g30 g31 g32 g33 g34 g35 r31 r32 r33 r34 r35 figure 25.19 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 817 of 1036 rej09b0254-0600 13) 8-bit i/f color 640 840 stn-lcd dotclock cl2 lcd0 lcd1 lcd2 lcd3 r0 g0 b0 r1 g1 r2 g2 lcd8 to 15 low lcd4 lcd5 lcd6 lcd7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 g637 b637 r638 g638 r639 g639 b638 b639 r0 g0 b0 r1 g1 r2 g2 b1 cl1 one horizontal time ( ex. 640 + 8 3 (:3 character) = 664 dclk) one horizontal display time (640 dclk) horizontal synchronization position horizontal synchronization width horizontal retrace time cl1 valid valid valid valid valid lcd one horizontal time flm 1st line data 2nd line data one frame time (480 cl1) 1st line data cl2 2nd line data 480th line data next frame time (480 cl1) no vertical retrace one vertical retrace cl1 lcd valid valid one horizontal time flm 1st line data 2nd line data one frame time (481 cl1) 1st line data cl2 2nd line data 480th line data next frame time (480 cl1) vertical retrace time (one horizontal time) horizontal wave valid valid valid valid figure 25.20 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 818 of 1036 rej09b0254-0600 14) 16-bit i/f color 640 480 tft-lcd dotclock cl2 lcd0 lcd1 lcd2 lcd3 b 0 , 3 b1, 3 b1, 4 b1, 5 b1, 6 b1, 7 g1, 2 b 0, 4 b 0, 5 b 0, 6 b 0, 7 g 0, 2 g 0, 3 g1, 3 g1, 4 g1, 5 g1, 6 g1, 7 r1, 3 g 0, 4 g 0, 5 g 0, 6 g 0, 7 r 0, 3 r 0, 4 r1, 4 r1, 5 r1, 6 r1, 7 r 0, 5 r 0, 6 r 0, 7 lcd4 lcd5 lcd6 lcd7 cl1 one horizontal display time (640 dclk) horizontal synchronization width horizontal retrace time cl1 lcd valid valid valid one horizontal time flm 1st line data 2nd line data one frame time (480 cl1) 1st line data cl2 2nd line data 480th line data next frame time (480 cl1) no vertical retrace horizontal wave b639,3 b639,4 b639,5 b639,6 b639,7 g639,2 g639,3 g639,4 g639,5 g639,6 g639,7 r639,3 r639,4 r639,5 r639,6 r639,7 lcd8 lcd9 lcd10 lcd11 lcd12 lcd13 lcd14 lcd15 b0, 3 b0, 4 b0, 5 b0, 6 b0, 7 g0, 2 g0, 3 g0, 4 g0, 5 g0, 6 g0, 7 r0, 3 r0, 4 r0, 5 r0, 6 r0, 7 8dclk 8dclk 8dclk disp disp horizontal synchronization position one horizontal time ( ex. 640 + 8 3 (:3 character) = 664 dclk) valid valid valid figure 25.21 clock and lcd data signal example
section 25 lcd controller rev.6.00 mar. 27, 2009 page 819 of 1036 rej09b0254-0600 25.5 usage notes note the following points when using the lcdc. 1. the following steps should be performed to prohibit access to the sy stem memory used for lcdc module display (synchronous dram in area 3). (1) confirm that bits lps1 and lps0 in the ldpmmr register are set to 1. (2) clear the don bit in ldcntr to 0 (display off mode). (3) confirm that bits lps1 and l ps0 in ldpmmr are cleared to 0. (4) wait the display duration of one frame. the above steps to prohibit access are necessary before entering standby mode or using the lcdc module?s standby function. 2. notes on use of lcdc external clock when in clock mode 2 (crystal resonator used) and an external clock (lclk) is used as the lcd clock, changes in the state of the lclk output pin can cause noise that affects the crystal oscillator circuit, resulting in unstable pll operation and possible malfunction. in such a case, implement one of the following measures: ? use an internal clock as the lcd clock when in clock mode 2. ? when using an external clock (lclk) as the lcd clock, select a mode other than clock mode 2 (external input on extal pin).
section 25 lcd controller rev.6.00 mar. 27, 2009 page 820 of 1036 rej09b0254-0600
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 821 of 1036 rej09b0254-0600 section 26 pin function controller (pfc) 26.1 overview the pin function of the SH7727 can be changed by the pin function controller (switch of the i/o port function), pc card controller (described in section 30), usb pin multiplexed controller (described in section 22), and user debugging in terface (described in section 31). figure 26.1 shows the overview of the pin selection function. pin function controller external pin external pin (not i/o port and pin multiplex) i/o port a6pcm pouse usb_trans other functions pc card controller usb pin multiplexed controller pcc/usb selection (i/o port and pin multiplex) figure 26.1 overview of the pin selection function table 26.1 list of multiplexed pins port port function (related module) other function 1 (related module) other function 2 (related module) a pta7 in/out (port) d23 in/out (data bus) a pta6 in/out (port) d22 in/out (data bus) a pta5 in/out (port) d21 in/out (data bus) a pta4 in/out (port) d20 in/out (data bus) a pta3 in/out (port) d19 in/out (data bus) a pta2 in/out (port) d18 in/out (data bus) a pta1 in/out (port) d17 in/out (data bus) a pta0 in/out (port) d16 in/out (data bus)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 822 of 1036 rej09b0254-0600 port port function (related module) other function 1 (related module) other function 2 (related module) b ptb7 in/out (port) d31 in/out (data bus) b ptb6 in/out (port) d30 in/out (data bus) b ptb5 in/out (port) d29 in/out (data bus) b ptb4 in/out (port) d28 in/out (data bus) b ptb3 in/out (port) d27 in/out (data bus) b ptb2 in/out (port) d26 in/out (data bus) b ptb1 in/out (port) d25 in/out (data bus) b ptb0 in/out (port) d24 in/out (data bus) c ptc7 in/out (port)/pint3 in (intc) lcd11 out (lcdc) c ptc6 in/out (port)/pint2 in (intc) lcd10 out (lcdc) c ptc5 in/out (port)/pint1 in (intc) lcd9 out (lcdc) c ptc4 in/out (port)/pint0 in (intc) lcd8 out (lcdc) c ptc3 in/out (port) lcd5 out (lcdc) c ptc2 in/out (port) lcd4 out (lcdc) c ptc1 in/out (port) lcd3 out (lcdc) c ptc0 in/out (port) lcd2 out (lcdc) d ptd7 in/out (port) don out (lcdc) d ptd6 in (port) lclk in (lcdc)/uclk (usb) d ptd5 in/out (port) cl1 out (lcdc) d ptd4 in (port) dreq0 in (dmac) d ptd3 in/out (port) lcd7 out (lcdc) d ptd2 in/out (port) lcd6 out (lcdc) d ptd1 in/out (port) lcd1 out (lcdc) d ptd0 in/out (port) lcd0 out (lcdc)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 823 of 1036 rej09b0254-0600 port port function (related module) other function 1 (related module) other function 2 (related module) e pte7 in/out (port) audsync out (aud) * 3 pcc0rdy in (pcc) * 2 e pte6 in/out (port) m/disp out (lcdc) e pte5 in/out (port) ce2b out (pcmcia) e pte4 in/out (port) ce2a out (pcmcia) e pte3 in/out (port) flm out (lcdc) e pte2 in/out (port) usb1_pwr_en out (usb) e pte1 in/out (port) usb2_pwr_en out (usb) e pte0 in/out (port) tdo out (h-udi) * 2 f ptf7 in (port)/pint15 in (intc) trst in (aud, h-udi) * 3 f ptf6 in (port)/pint14 in (intc) tms in (h-udi) * 3 f ptf5 in (port)/pint13 in (intc) td1 in (h-udi) * 3 f ptf4 in (port)/pint12 in (intc) tck in (h-udi) * 3 f ptf3 in (port)/pint11 in (intc) reserved f ptf2 in (port) reserved pccoreg out (pcc) * 2 f ptf1 in (port) reserved pccovs1 in (pcc) * 2 f ptf0 in (port) reserved pccovs2 in (pcc) * 2 g ptg7 in (port) iois16 in (pcmcia) g ptg5 in (port) asebrkak out (aud) * 3 g ptg4 in (port) ? g ptg3 in (port) audata3 out (aud) * 3 pcc0bvd2 (pcc) * 2 g ptg2 in (port) audata2 out (aud) * 3 pcc0bvd1 (pcc) * 2 g ptg1 in (port) audata1 out (aud) * 3 pcc0cd2 (pcc) * 2 g ptg0 in (port) audata0 out (aud) * 3 pcc0cd1 (pcc) * 2 h pth7 in/out (port) cl2 out (lcdc) h pth6 in (port) audck in (aud) * 1 pcc0wait (pcc) h pth5 in (port) adtrg in (adc) h pth4 in (port)/irq4 in (intc) irq4 in (intc) h pth3 in (port)/irq3 in irl3 in (intc) irq3 in irl3 in (intc) h pth2 in (port)/irq2 in irl2 in (intc) irq2 in irl2 in (intc) h pth1 in (port)/irq1 in irl1 in (intc) irq1 in irl1 in (intc) h pth0 in (port)/irq0 in irl0 in (intc) irq0 in irl0 in (intc)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 824 of 1036 rej09b0254-0600 port port function (related module) other function 1 (related module) other function 2 (related module) j ptj7 in/out (port) status1 out (cpg) j ptj6 in/out (port) status0 out (cpg) j ptj5 in/out (port) reserved j ptj4 in/out (port) reserved j ptj3 in/out (port) reserved j ptj2 in/out (port) cas out (bsc) reserved j ptj1 in/out (port) reserved j ptj0 in/out (port) ras out (bsc) k ptk7 in/out (port) we3 out (bsc)/dqmuu out (bsc)/ iciowr out (bsc) k ptk6 in/out (port) we2 out (bsc)/dqmul out (bsc)/ iciord out (bsc) k ptk5 in/out (port) cke out (bsc) k ptk4 in/out (port) bs out (bsc) k ptk3 in/out (port) cs5 out (bsc)/ ce1a out (bsc) k ptk2 in/out (port) cs4 out (bsc) k ptk1 in/out (port) afe_rlycnt out (afe) usb1d_dmns in (usb) * 2 k ptk0 in/out (port) afe_hc1 out (afe) usb1d_dpls in (usb) * 2 l ptl7 in (port) an7 in (adc)/da0 out (dac) l ptl6 in (port) an6 in (adc)/da1 out (dac) l ptl5 in (port) an5 in (adc) l ptl4 in (port) an4 in (adc) l ptl3 in (port) an3 in (adc) l ptl2 in (port) an2 in (adc) m ptm7 in (port)/pint7 in (intc) afe_fs in (afe) usb1d_rcv in (usb) * 2 m ptm6 in (port)/pint6 in (intc) afe_rxin in (afe) usb1d_speed out (usb) * 2 m ptm5 in (port)/pint5 in (intc) afe_txout out (afe) usb1d_txse0 out (usb) * 2 m ptm4 in (port)/pint4 in (intc) afe_rdet in (afe) m ptm3 in (port)/ pint10 in (intc) lcd15 out (lcdc) m ptm2 in (port)/pint9 in (intc) lcd14 out (lcdc) m ptm1 in (port)/pint8 in (intc) lcd13 out (lcdc) m ptm0 in (port) lcd12 out (lcdc)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 825 of 1036 rej09b0254-0600 port port function (related module) other function 1 (related module) other function 2 (related module) scpt scpt7 in (port)/irq5 in (intc) cts2 in (scif)/irq5 in (intc) scpt scpt6 in/out (port) siofsync in/out (siof) scpt scpt5 in/out (port) sck_sio in/out (siof) scpt4 in (port) * 1 rxd2 in (scif) scpt scpt4 out (port) * 1 txd2 out (scif) scpt scpt3 in/out (port) siomclk in (siof) scpt2 in (port) * 1 rxd_sio in (siof) scpt scpt2 out (port) * 1 txd_sio out (siof) scpt scpt1 in/out (port) sck0 in/out (sci) scpt scpt0 in (port) * 1 rxd0 in (sci) scpt0 out (port) * 1 txd0 out (sci) ? ? afe_sclk in (afe) usb1d_txdpls out (usb) ? ? reserved usb1d_suspend out (usb) ? ? rts2 out (scif) usb1d_txenl out (usb) ? ? drak0 out (dmac) pcc0reset out (pcc) ? ? dack0 out (dmac) pcc0drv out (pcc) notes: 1. scpt0, scpt2, and scpt4 are different input pins and output pins, but the accessed data register is the same. 2. for pins with which pcc or usb pin multip lex controller related pins are multiplexed, other functions (in normal operation) and ot her functions (with special settings) are switched according to the setting of the p0 use bit in pcc, the a6pcm bit in bsc, and a usb pin multiplex controller register setting. to enable a pcc pin, set a6pcm and p0use to use of a pc card. switching to the pcc pin is performed automatically according to the value of the two bits. for i/o ports with which pcc or usb pin multiplex controller related pins are multiplexed, do not change the p0use bit in pcc, the a6pcm bit in bsc, or the usb pin multiplex controller register, a fter switching to the other function. 3. enabled when asemd0 is low.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 826 of 1036 rej09b0254-0600 26.2 register configuration table 26.2 summarizes the registers of the pin function controller (pfc). table 26.2 pin function controller registers name abbreviation r/w initia l value address access size port a control register pacr r/w h'0000 h'04000100 (h'a4000100) * 16 port b control register pbcr r/w h'0000 h'04000102 (h'a4000102) * 16 port c control register pccr r/w h'aaaa h'04000104 (h'a4000104) * 16 port d control register pdcr r/w h'aaaa h'04000106 (h'a4000106) * 16 port e control register pe cr r/w h'aaaa/h'2 aa8 h'04000108 (h'a4000108) * 16 port f control register pf cr r/w h'aaaa/h'00a a h'0400010a (h'a400010a) * 16 port g control register pg cr r/w h'aaaa/h'a2 00 h'0400010c (h'a400010c) * 16 port h control register p hcr r/w h'aaaa/h'8aaa h'0400010e (h'a400010e) * 16 port j control register pjcr r/w h'0000 h'04000110 (h'a4000110) * 16 port k control register pkcr r/w h'0000 h'04000112 (h'a4000112) * 16 port l control register plcr r/w h'0000 h'04000114 (h'a4000114) * 16 sc port control register scpcr r/w h'8008 h'04000116 (h'a4000116) * 16 port m control register pmcr r/w h'aaaa h'04000118 (h'a4000118) * 16 notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. see section 31, user-debugging interface (h-udi), for more information on the h-udi. the initial value of the port e, f, g, and h control registers depends on the state of the asemd0 pin. * when address translation by the mmu does not apply, the address in parentheses should be used.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 827 of 1036 rej09b0254-0600 26.3 register descriptions 26.3.1 port a control register (pacr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pa7 md1 pa7 md0 pa6 md1 pa6 md0 pa5 md1 pa5 md0 pa4 md1 pa4 md0 pa3 md1 pa3 md0 pa2 md1 pa2 md0 pa1 md1 pa1 md0 pa0 md1 pa0 md0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port a control register (pacr) is a 16-bit read /write register that selects the pin functions. pacr is initialized to h'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pa7 mode 1, 0 (pa7md1, pa7md0) bits 13, 12: pa6 mode 1, 0 (pa6md1, pa6md0) bits 11, 10: pa5 mode 1, 0 (pa5md1, pa5md0) bits 9, 8: pa4 mode 1, 0 (pa4md1, pa4md0) bits 7, 6: pa3 mode 1, 0 (pa3md1, pa3md0) bits 5, 4: pa2 mode 1, 0 (pa2md1, pa2md0) bits 3, 2: pa1 mode 1, 0 (pa1md1, pa1md0) bits 1, 0: pa0 mode 1, 0 (pa0md1, pa0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n panmd1 panmd0 pin function 0 0 other function (see tabl e 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 828 of 1036 rej09b0254-0600 26.3.2 port b control register (pbcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pb7 md1 pb7 md0 pb6 md1 pb6 md0 pb5 md1 pb5 md0 pb4 md1 pb4 md0 pb3 md1 pb3 md0 pb2 md1 pb2 md0 pb1 md1 pb1 md0 pb0 md1 pb0 md0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port b control register (pbcr) is a 16-bit read/wr ite register that selects the pin functions. pbcr is initialized to h'0000 by power-on resets; howe ver, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pb7 mode 1, 0 (pb7md1, pb7md0) bits 13, 12: pb6 mode 1, 0 (pb6md1, pb6md0) bits 11, 10: pb5 mode 1, 0 (pb5md1, pb5md0) bits 9, 8: pb4 mode 1, 0 (pb4md1, pb4md0) bits 7, 6: pb3 mode 1, 0 (pb3md1, pb3md0) bits 5, 4: pb2 mode 1, 0 (pb2md1, pb2md0) bits 3, 2: pb1 mode 1, 0 (pb1md1, pb1md0) bits 1, 0: pb0 mode 1, 0 (pb0md1, pb0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pbnmd1 pbnmd0 pin function 0 0 other function (see tabl e 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 829 of 1036 rej09b0254-0600 26.3.3 port c control register (pccr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pc7 md1 pc7 md0 pc6 md1 pc6 md0 pc5 md1 pc5 md0 pc4 md1 pc4 md0 pc3 md1 pc3 md0 pc2 md1 pc2 md0 pc1 md1 pc1 md0 pc0 md1 pc0 md0 initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port c control register (pccr) is a 16-bit read/wr ite register that selects the pin functions. pccr is initialized to h'aaaa by power-on resets; ho wever, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pc7 mode 1, 0 (pc7md1, pc7md0) bits 13, 12: pb6 mode 1, 0 (pc6md1, pc6md0) bits 11, 10: pc5 mode 1, 0 (pc5md1, pc5md0) bits 9, 8: pc4 mode 1, 0 (pc4md1, pc4md0) bits 7, 6: pc3 mode 1, 0 (pc3md1, pc3md0) bits 5, 4: pc2 mode 1, 0 (pc2md1, pc2md0) bits 3, 2: pc1 mode 1, 0 (pc1md1, pc1md0) bits 1, 0: pc0 mode 1, 0 (pc0md1, pc0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pcnmd1 pcnmd0 pin function 0 0 other function (see table 26.1) 0 1 port output 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 830 of 1036 rej09b0254-0600 26.3.4 port d control register (pdcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pd7 md1 pd7 md0 pd6 md1 pd6 md0 pd5 md1 pd5 md0 pd4 md1 pd4 md0 pd3 md1 pd3 md0 pd2 md1 pd2 md0 pd1 md1 pd1 md0 pd0 md1 pd0 md0 initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port d control register (pdcr) is a 16-bit read /write register that selects the pin functions. pdcr is initialized to h'aaaa by power-on rese ts; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pd7 mode 1, 0 (pd7md1, pd7md0) bits 13, 12: pd6 mode 1, 0 (pd6md1, pd6md0) bits 11, 10: pd5 mode 1, 0 (pd5md1, pd5md0) bits 9, 8: pd4 mode 1, 0 (pd4md1, pd4md0) bits 7, 6: pd3 mode 1, 0 (pd3md1, pd3md0) bits 5, 4: pd2 mode 1, 0 (pd2md1, pd2md0) bits 3, 2: pd1 mode 1, 0 (pd1md1, pd1md0) bits 1, 0: pd0 mode 1, 0 (pd0md1, pd0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pdnmd1 pdnmd0 pin function 0 0 other function (see table 26.1) 0 1 port output (n = value other t han 4 or 6), reserved (n = 4 or 6) 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 831 of 1036 rej09b0254-0600 26.3.5 port e control register (pecr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe7 md1 pe7 md0 pe6 md1 pe6 md0 pe5 md1 pe5 md0 pe4 md1 pe4 md0 pe3 md1 pe3 md0 pe2 md1 pe2 md0 pe1 md1 pe1 md0 pe0 md1 pe0 md0 initial value: 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 1/0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port e control register (pecr) is a 16-bit read/w rite register that selects the pin functions. pecr is initialized to h'aaaa ( asemd0 = 1) or h'2aa8 ( asemd0 = 0) by power-on resets; however, it is not initialized by manual resets, in software standby mode, or in sleep mode. bits 15, 14: pe7 mode 1, 0 (pe7md1, pe7md0) bits 13, 12: pe6 mode 1, 0 (pe6md1, pe6md0) bits 11, 10: pe5 mode 1, 0 (pe5md1, pe5md0) bits 9, 8: pe4 mode 1, 0 (pe4md1, pe4md0) bits 7, 6: pe3 mode 1, 0 (pe3md1, pe3md0) bits 5, 4: pe2 mode 1, 0 (pe2md1, pe2md0) bits 3, 2: pe1 mode 1, 0 (pe1md1, pe1md0) bits 1, 0: pe0 mode 1, 0 (pe0md1, pe0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n penmd1 penmd0 pin function 0 0 reserved (n = 0, 7) (see table 26.1) (initial value) asemd0 = 0 0 1 port output 1 0 port input (pullup mos: on) (initial value) asemd0 = 1 1 1 port input (pullup mos: off) if asemd0 = 0, port function cannot be selected with any pe7md1, pe7md0 value. (n = 0, 7) bit (2n + 1) bit 2n penmd1 penmd0 pin function 0 0 other function (see table 26.1) 0 1 port output 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 1 to 6)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 832 of 1036 rej09b0254-0600 26.3.6 port f control register (pfcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pf7 md1 pf7 md0 pf6 md1 pf6 md0 pf5 md1 pf5 md0 pf4 md1 pf4 md0 pf3 md1 pf3 md0 pf2 md1 pf2 md0 pf1 md1 pf1 md0 pf0 md1 pf0 md0 initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port f control register (pfcr) is a 16-bit read/w rite register that selects the pin functions. pfcr is initialized to h'aaaa ( asemd0 = 1) or h'00aa ( asemd0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pf7 mode 1, 0 (pf7md1, pf7md0) bits 13, 12: pf6 mode 1, 0 (pf6md1, pf6md0) bits 11, 10: pf5 mode 1, 0 (pf5md1, pf5md0) bits 9, 8: pf4 mode 1, 0 (pf4md1, pf4md0) bits 7, 6: pf3 mode 1, 0 (pf3md1, pf3md0) bits 5, 4: pf2 mode 1, 0 (pf2md1, pf2md0) bits 3, 2: pf1 mode 1, 0 (pf1md1, pf1md0) bits 1, 0: pf0 mode 1, 0 (pf0md1, pf0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pfnmd1 pfnmd0 pin function 0 0 reserved (see table 26.1) (initial value) asemd0 = 0 0 1 reserved 1 0 port input (pullup mos: on) (initial value) asemd0 = 1 1 1 port input (pullup mos: off) (n = 4 to7) bit (2n + 1) bit 2n pfnmd1 pfnmd0 pin function 0 0 other function (see table 26.1) 0 1 reserved 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 0 to 3)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 833 of 1036 rej09b0254-0600 26.3.7 port g control register (pgcr) for details on using versions previous to the SH7727b please refer to appendix f, specifications for using port g control register (pgcr) with versions previous to the SH7727b. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pg7 md1 pg7 md0 ? ? pg5 md1 pg5 md0 pg4 md1 pg4 md0 pg3 md1 pg3 md0 pg2 md1 pg2 md0 pg1 md1 pg1 md0 pg0 md1 pg0 md0 initial value: 1 0 1 0 1/0 0 1 0 1/0 0 1/0 0 1/0 0 1/0 0 r/w: r/w r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port g control register (pgcr) is a 16-bit read /write register that selects the pin functions. pgcr is initialized to h'aaaa ( asemd0 = 1) or h'a200 ( asemd0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pg7 mode 1, 0 (pg7md1, pg7md0) bits 13, 12: reserved bits 11, 10: pg5 mode 1, 0 (pg5md1, pg5md0) bits 9, 8: pg4 mode 1, 0 (pg4md1, pg4md0) bits 7, 6: pg3 mode 1, 0 (pg3md1, pg3md0) bits 5, 4: pg2 mode 1, 0 (pg2md1, pg2md0) bits 3, 2: pg1 mode 1, 0 (pg1md1, pg1md0) bits 1, 0: pg0 mode 1, 0 (pg0md1, pg0md0) these bits select the pin functions and the input pullup mos control.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 834 of 1036 rej09b0254-0600 bit (2n + 1) bit 2n pgnmd1 pgnmd0 pin function 0 0 other function (n = 1, 2, 3, 5) (see table 26.1) (initial value) asemd0 = 0 0 1 reserved 1 0 port input (pullup mos: on) (initial value) asemd0 = 1 1 1 port input (pullup mos: off) (n = 0 to 3, 5) bit (2n + 1) bit 2n pgnmd1 pgnmd0 pin function 0 0 other function (n = 7) (see table 26.1), reserved (n = 4) 0 1 reserved 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 4, 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 835 of 1036 rej09b0254-0600 26.3.8 port h control register (phcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ph7 md1 ph7 md0 ph6 md1 ph6 md0 ph5 md1 ph5 md0 ph4 md1 ph4 md0 ph3 md1 ph3 md0 ph2 md1 ph2 md0 ph1 md1 ph1 md0 ph0 md1 ph0 md0 initial value: 1 0 1/0 0 1 0 1 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port h control register (phcr) is a 16-bit read /write register that selects the pin functions. phcr is initialized to h'aaaaa( asemd0 = 1) or h'8aaa ( asemd0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: ph7 mode 1, 0 (ph7md1, ph7md0) bits 13, 12: ph6 mode 1, 0 (ph6md1, ph6md0) bits 11, 10: ph5 mode 1, 0 (ph5md1, ph5md0) bits 9, 8: ph4 mode 1, 0 (ph4md1, ph4md0) bits 7, 6: ph3 mode 1, 0 (ph3md1, ph3md0) bits 5, 4: ph2 mode 1, 0 (ph2md1, ph2md0) bits 3, 2: ph1 mode 1, 0 (ph1md1, ph1md0) bits 1, 0: ph0 mode 1, 0 (ph0md1, ph0md0) these bits select the pin functions and the input pullup mos control. bit 15 bit 14 ph7md1 ph7md0 pin function 0 0 other function (see table 26.1) 0 1 port output 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) bit 13 bit 12 ph6md1 ph6md0 pin function 0 0 other function (see table 26.1) (initial value) asemd0 = 0 0 1 reserved 1 0 port input (pullup mos: on) (initial value) asemd0 = 1 1 1 port input (pullup mos: off)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 836 of 1036 rej09b0254-0600 bit (2n + 1) bit 2n phnmd1 phnmd0 pin function 0 0 other function (see table 26.1) 0 1 reserved 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 0 to 5) 26.3.9 port j control register (pjcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pj7 md1 pj7 md0 pj6 md1 pj6 md0 pj5 md1 pj5 md0 pj4 md1 pj4 md0 pj3 md1 pj3 md0 pj2 md1 pj2 md0 pj1 md1 pj1 md0 pj0 md1 pj0 md0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port j control register (pjcr) is a 16-bit read/wr ite register that selects the pin functions. pjcr is initialized to h'0000 by power-on re sets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pj7 mode 1, 0 (pj7md1, pj7md0) bits 13, 12: pj6 mode 1, 0 (pj6md1, pj6md0) bits 11, 10: pj5 mode 1, 0 (pj5md1, pj5md0) bits 9, 8: pj4 mode 1, 0 (pj4md1, pj4md0) bits 7, 6: pj3 mode 1, 0 (pj3md1, pj3md0) bits 5, 4: pj2 mode 1, 0 (pj2md1, pj2md0) bits 3, 2: pj1 mode 1, 0 (pj1md1, pj1md0) bits 1, 0: pj0 mode 1, 0 (pj0md1, pj0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pjnmd1 pjnmd0 pin function 0 0 other function (see tabl e 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 837 of 1036 rej09b0254-0600 26.3.10 port k control register (pkcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pk7 md1 pk7 md0 pk6 md1 pk6 md0 pk5 md1 pk5 md0 pk4 md1 pk4 md0 pk3 md1 pk3 md0 pk2 md1 pk2 md0 pk1 md1 pk1 md0 pk0 md1 pk0 md0 initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port k control register (pkcr) is a 16-bit read /write register that selects the pin functions. pkcr is initialized to h'0000 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pk7 mode 1, 0 (pk7md1, pk7md0) bits 13, 12: pk6 mode 1, 0 (pk6md1, pk6md0) bits 11, 10: pk5 mode 1, 0 (pk5md1, pk5md0) bits 9, 8: pk4 mode 1, 0 (pk4md1, pk4md0) bits 7, 6: pk3 mode 1, 0 (pk3md1, pk3md0) bits 5, 4: pk2 mode 1, 0 (pk2md1, pk2md0) bits 3, 2: pk1 mode 1, 0 (pk1md1, pk1md0) bits 1, 0: pk0 mode 1, 0 (pk0md1, pk0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pknmd1 pknmd0 pin function 0 0 other function (see tabl e 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 838 of 1036 rej09b0254-0600 26.3.11 port l control register (plcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pl7 md1 pl7 md0 pl6 md1 pl6 md0 pl5 md1 pl5 md0 pl4 md1 pl4 md0 pl3 md1 pl3 md0 pl2 md1 pl2 md0 ? ? ? ? initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r port l control register (plcr) is a 16-bit read/w rite register that selects the pin functions. plcr is initialized to h'0000 by power-on resets; howe ver, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pl7 mode 1, 0 (pl7md1, pl7md0) bits 13, 12: pl6 mode 1, 0 (pl6md1, pl6md0) bits 11, 10: pl5 mode 1, 0 (pl5md1, pl5md0) bits 9, 8: pl4 mode 1, 0 (pl4md1, pl4md0) bits 7, 6: pl3 mode 1, 0 (pl3md1, pl3md0) bits 5, 4: pl2 mode 1, 0 (pl2md1, pl2md0) bits 3 to 0: reserved these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n plnmd1 plnmd0 pin function 0 0 other function (see tabl e 26.1) (initial value) 0 1 reserved 1 ? port input (n = 2 to 7) when the da0 and da1 pins are used as the d/ a converter outputs or when ptl7 and ptl6 are used as the other function states, plcr should remain at its initial value.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 839 of 1036 rej09b0254-0600 26.3.12 port m control register (pmcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pm7 md1 pm7 md0 pm6 md1 pm6 md0 pm5 md1 pm5 md0 pm4 md1 pm4 md0 pm3 md1 pm3 md0 pm2 md1 pm2 md0 pm1 md1 pm1 md0 pm0 md1 p0 md0 initial value: 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w port m control register (pmcr) is a 16-bit read /write register that selects the pin functions. pmcr is initialized to h'aaaa by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. bits 15, 14: pm7 mode 1, 0 (pm7md1, pm7md0) bits 13, 12: pm6 mode 1, 0 (pm6md1, pm6md0) bits 11, 10: pm5 mode 1, 0 (pm5md1, pm5md0) bits 9, 8: pm4 mode 1, 0 (pm4md1, pm4md0) bits 7, 6: pm3 mode 1, 0 (pm3md1, pm3md0) bits 5, 4: pm2 mode 1, 0 (pm2md1, pm2md0) bits 3, 2: pm1 mode 1, 0 (pm1md1, pm1md0) bits 1, 0: pm0 mode 1, 0 (pm0md1, pm0md0) these bits select the pin functions and the input pullup mos control. bit (2n + 1) bit 2n pmnmd1 pmnmd0 pin function 0 0 other function (see table 26.1) 0 1 reserved 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) (n = 0 to 7)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 840 of 1036 rej09b0254-0600 26.3.13 sc port control register (scpcr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scp7 md1 scp7 md0 scp6 md1 scp6 md0 scp5 md1 scp5 md0 scp4 md1 scp4 md0 scp3 md1 scp3 md0 scp2 md1 scp2 md0 scp1 md1 scp1 md0 scp0 md1 scp0 md0 initial value: 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w sc port control register (scpcr) is a 16-bit read/w rite register that selects the pin functions. the setting of scpcr is valid only when the transmit/r eceive operation is disabled in the setting of the scscr register. scpcr is initialized to h'8008 by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. when the te bit in scscr is set to 1, the other function output state has a higher priority than the scpcr setting of the txd[2:0] pin. when the re bit in scscr is set to 1, the input state has a higher priority than the scpcr setting of the rxd[2:0] pin. bits 15, 14?scp7 mode 1, 0 (scp7md1, scp7md0): these bits select the pin functions and the input pullup mos control. bit 15 bit 14 scp7md1 scp7md0 pin function 0 0 other function (see table 26.1) 0 1 reserved 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) bits 13, 12?scp6 mode 1, 0 (scp6md1, scp6md0): these bits select the pin functions and the input pullup mos control. bit 13 bit 12 scp6md1 scp6md0 pin function 0 0 other function (see table 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off)
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 841 of 1036 rej09b0254-0600 bits 11, 10?scp5 mode 1, 0 (scp5md1, scp5md0): these bits select the pin functions and the input pullup mos control. bit 11 bit 10 scp5md1 scp5md0 pin function 0 0 other function (see table 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) bits 9, 8?scp4 mode 1, 0 (scp4md1, scp4md0): these bits select the pin functions and the input pullup mos control. bit 9 bit 8 scp4md1 scp4md0 pin function 0 0 transmit data output 2 (txd2) receive data input 2 (rxd2) (initial value) 0 1 general output (scpt[4] output pin) receive data input 2 (rxd2) 1 0 scpt[4] input pin pullup (input pin) transmit data output 2 (txd2) 1 1 general input (scpt[4] input pin) transmit data output 2 (txd2) note: there is no combination of simultaneous i/o of scpt[4] because one bit (scp4dt) is accessed using two pins of txd2 and rxd2. when the port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd2 pin is in the output state. when the te bit is cleared to 0, the txd2 pin is in the high- impedance state.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 842 of 1036 rej09b0254-0600 bits 7, 6?scp3 mode 1, 0 (scp3md1, scp3md0): these bits select the pin functions and the input pullup mos control. bit 7 bit 6 scp3md1 scp3md0 pin function 0 0 other function (see table 26.1) (initial value) 0 1 port output 1 0 port input (pullup mos: on) 1 1 port input (pullup mos: off) bits 5, 4?scp2 mode 1, 0 (scp2md1, scp2md0): these bits select the pin functions and the input pullup mos control. bit 5 bit 4 scp2md1 scp2md0 pin function 0 0 transmit data output 1 (txd_sio) receive data input 1 (rxd_sio) (initial value) 0 1 general output (scpt[2] output pin) receive data input 1 (rxd_sio) 1 0 scpt[2] input pin pullup (input pin) transmit data output 1 (txd_sio) 1 1 general input (scpt[2] input pin) transmit data output 1 (txd_sio) note: there is no combination of simultaneous i/o of scpt[2] because one bit (scp2dt) is accessed using two pins of txd_sio and rxd_sio. when the port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd_sio pin is in the output state. when the te bit is cleared to 0, the txd_sio pin is in the high-impedance state.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 843 of 1036 rej09b0254-0600 bits 3, 2?scp1 mode 1, 0 (scp1md1, scp1md0): these bits select the pin functions and the input pullup mos control. bit 3 bit 2 scp1md1 scp1md0 pin function 0 0 other function (see table 26.1) 0 1 port output 1 0 port input (pullup mos: on) (initial value) 1 1 port input (pullup mos: off) bits 1, 0?scp0 mode 1, 0 (scp0md1, scp0md0): these bits select the pin functions and the input pullup mos control. bit 1 bit 0 scp0md1 scp0md0 pin function 0 0 transmit data output 0 (txd0) receive data input 0 (rxd0) (initial value) 0 1 general output (scpt[0] output pin) receive data input 0 (rxd0) 1 0 scpt[0] input pin pullup (input pin) transmit data output 0 (txd0) 1 1 general input (scpt[0] input pin) transmit data output 0 (txd0) note: there is no combination of simultaneous i/o of scpt[0] because one bit (scp0dt) is accessed using two pins of txd0 and rxd0. when the port input is set (bit scpnmd1 is set to 1) and when the te bit in scscr is set to 1, the txd0 pin is in the output state. when the te bit is cleared to 0, the txd0 pin is in the high- impedance state.
section 26 pin function controller (pfc) rev.6.00 mar. 27, 2009 page 844 of 1036 rej09b0254-0600
section 27 i/o ports rev.6.00 mar. 27, 2009 page 845 of 1036 rej09b0254-0600 section 27 i/o ports 27.1 overview this lsi has thirteen 8-bit ports (ports a to m an d sc). all port pins are multiplexed with other pin functions (pin function controller (pfc) selects the pin functions and pullup mos control). each port has a data register which stores data for the pins.
section 27 i/o ports rev.6.00 mar. 27, 2009 page 846 of 1036 rej09b0254-0600 27.2 register configuration table 27.1 summarizes the registers of the pin function controller. table 27.1 pin function controller registers name abbreviation r/w initia l value address access size port a data register padr r/w h'00 h'04000120 (h'a4000120) * 1 8 port b data register pbdr r/w h'00 h'04000122 (h'a4000122) * 1 8 port c data register pcdr r/w h'00 h'04000124 (h'a4000124) * 1 8 port d data register pddr r/w or r b'0 * 0 * 0000 h'04000126 (h'a4000126) * 1 8 port e data register pedr r/w h'00 h'04000128 (h'a4000128) * 1 8 port f data register pfdr r h' ** h'0400012a (h'a400012a) * 1 8 port g data register pgdr r h' ** h'0400012c (h'a400012c) * 1 8 port h data register phdr r/w or r b'0 ******* h'0400012e (h'a400012e) * 1 8 port j data register pjdr r/w h'00 h'04000130 (h'a4000130) * 1 8 port k data register pkdr r/w h'00 h'04000132 (h'a4000132) * 8 port l data register pldr r h' ** h'04000134 (h'a4000134) * 1 8 sc port data register scpdr r/w or r b' * 0000000 h'04000136 (h'a4000136) * 1 8 port m data register pmdr r b' ******** h'04000138 (h'a4000138) * 1 8 notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. * means no value. 1. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 27 i/o ports rev.6.00 mar. 27, 2009 page 847 of 1036 rej09b0254-0600 27.3 ports a to c, e, j, k each pin has an input pullup mos, which is controlled by port a to c, e, j, k control register in pfc. 27.3.1 ports a to c, e, j, k data rgister (padr, pbdr, pcdr, pedr, pjdr, pkdr) bit: 7 6 5 4 3 2 1 0 px7dt px6dt px5dt px4dt px3dt px2dt px1dt px0dt initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ports a to c, e, j, k data register (padr , pbdr, pcdr, pedr, pjdr, pkdr) is an 8-bit read/write register that stores data for pins ptx7 to ptx0. px7dt to px0dt bit corresponds to ptx7 to ptx0 pin. when the pin function is general output port, if the port is read, the value of the corresponding padr, pbdr, pcdr, pedr, pjdr and pkdr bit is returned directly. when the function is general input port, if the port is read , the corresponding pin level is read. table 27.2 shows the function of padr, pb dr, pcdr, pedr, pjdr, pkdr. padr, pbdr, pcdr, pedr , pjdr, pkdr is initialized to h'00 by a power-on reset. when asemd0 is equal to 1, after pdcr and pedr are initialized to h'00, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are fetched. it retains its previous value in standby mode and sleep mode, and by a manual reset. table 27.2 read/write operation of the ports a to c, e, j, k data register pxnmd1 pxnmd0 pin state read write 0 0 other function pxdr value value is written to pxdr, but does not affect pin state. 1 output pxdr value write value is output from pin. 1 0 input (pullup mos: on) pin state value is written to pxdr, but does not affect pin state. 1 input (pullup mos: off) pin state value is written to pxdr, but does not affect pin state. (n = 0 to 7) (x = a to c, e, j, k)
section 27 i/o ports rev.6.00 mar. 27, 2009 page 848 of 1036 rej09b0254-0600 27.4 port d each pin has an input pullup mos, which is controlled by port d control register (pdcr) in pfc. 27.4.1 port d data register (pddr) bit: 7 6 5 4 3 2 1 0 pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt initial value: 0 * 0 * 0 0 0 0 r/w: r/w r r/w r r/w r/w r/w r/w note: * undefined port d data register (pddr) is a 6-bit read/write an d 2-bit read register that stores data for pins ptd7 to ptd0. pd7dt to pd0dt bit corresponds to ptd7 to ptd0 pin. when the pin function is general output port, if the port is read, the value of the corresponding pddr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 27.3 shows the function of pddr. pddr is initialized to b'0*0*0000 by a power-on reset. after initialization, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are fetched. it retains its previous value in standby mode and sleep mode, and by a manual reset.
section 27 i/o ports rev.6.00 mar. 27, 2009 page 849 of 1036 rej09b0254-0600 table 27.3 read/write operation of the port d data register (pddr) pdnmd1 pdnmd0 pin state read write 0 0 other function pddr value value is written to pddr, but does not affect pin state. 1 output pddr value write value is output from pin. 1 0 input (pullup mos: on) pin state value is written to pddr, but does not affect pin state. 1 input (pullup mos: off) pin state value is written to pddr, but does not affect pin state. (n = 0 to 3, 5, 7) pdnmd1 pdnmd0 pin state read write 0 0 other function h'00 ignored (no affect on pin state) 1 reserved * ? ? 1 0 input (pullup mos: on) pin state ignored (no affect on pin state) 1 input (pullup mos: off) pin state ignored (no affect on pin state) note: * operation cannot be guaranteed when this bit it set to ?reserved.? (n = 4, 6)
section 27 i/o ports rev.6.00 mar. 27, 2009 page 850 of 1036 rej09b0254-0600 27.5 ports f, m each pin has an input pullup mos, which is controlled by ports f, m control register (pfdr, pmdr) in pfc. 27.5.1 ports f, m data register (pfdr, pmdr) bit: 7 6 5 4 3 2 1 0 px7dt px6dt px5dt px4dt px3dt px2dt px1dt px0dt initial value: * * * * * * * * r/w: r r r r r r r r note: * undefined ports f, m data register (pfdr, pmdr) is an 8-bit read register that stores data for pins ptx7 to ptx0. px7dt to px0dt bit corresponds to ptx7 to ptx0 pin. when the pin function is general input port, if the port is read, the corresponding pin level is read. table 27.4 shows the function of pfdr and pmdr. pfdr and pmdr are initialized by a power-on rese t. after initialization, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are read. table 27.4 read/write operation of the ports f, m data register (pfdr, pmdr) pxnmd1 pxnmd0 pin state read write 0 0 other function h?00 ignored (no affect on pin state) 1 reserved * ? ? 1 0 input (pullup mos on) pin state ignored (no affect on pin state) 1 input (pullup mos off) pin state ignored (no affect on pin state) note: * operation cannot be guaranteed when this bit it set to ?reserved.? (n = 0 to 7) (x = f, m)
section 27 i/o ports rev.6.00 mar. 27, 2009 page 851 of 1036 rej09b0254-0600 27.6 port g each pin has an input pullup mos, which is controlled by port g control register (pgcr) in pfc . 27.6.1 port g data register (pgdr) bit: 7 6 5 4 3 2 1 0 pg7dt ? pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt initial value: * * * * * * * * r/w: r r r r r r r r note: * undefined port g data register (pgdr) is an 8-bit read register that stores data for pins ptg7 and ptg5 to ptg0. pg7dt and ptg5dt to pg0d t bit corresponds to ptg7 and ptg5 to ptg0 pin. when the pin function is general input port, if the port is read, the corresponding pin level is read. table 27.5 shows the function of pgdr. when asemd0 is equal to 1, after pgdr is initialized by a power-on reset, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are fetched. table 27.5 read/write operation of the port g data register (pgdr) pgnmd1 pgnmd0 pin state read write 0 0 other function h?00 ignored (no affect on pin state) 1 reserved * ? ? 1 0 input (pullup mos: on) pin state ignored (no affect on pin state) 1 input (pullup mos: off) pin state ignored (no affect on pin state) note: * operation cannot be guaranteed when this bi t it set to ?reserved.? (n = 0 to 5, 7)
section 27 i/o ports rev.6.00 mar. 27, 2009 page 852 of 1036 rej09b0254-0600 27.7 port h each pin has an input pullup mos, which is controlled by port h control register (phcr) in pfc. 27.7.1 port h data register (phdr) bit: 7 6 5 4 3 2 1 0 ph7dt ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt initial value: 0 * * * * * * * r/w: r/w r r r r r r r note: * undefined port h data register (phdr) is a 1-bit read/write an d 7-bit read register that stores data for pins pth7 to pth0. ph7dt to ph0dt bit corresponds to pth7 to pth0 pin. when the pin function is general output port, if the port is read, the value of the corresponding phdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. table 27.6 shows the function of phdr. when asemd0 is equal to 1, after phdr is initialized to b'0******* by a power-on reset, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are fetched. it retains its previous value in standby mode and sleep mode, and by a manual reset.
section 27 i/o ports rev.6.00 mar. 27, 2009 page 853 of 1036 rej09b0254-0600 table 27.6 read/write operation of the port h data register (phdr) phnmd1 phnmd0 pin state read write 0 0 other function phdr value value is written to phdr, but does not affect pin state. 1 output phdr value write value is output from pin. 1 0 input (pullup mos: on) pin state value is written to phdr, but does not affect pin state. 1 input (pullup mos: off) pin state value is written to phdr, but does not affect pin state. (n = 7) phnmd1 phnmd0 pin state read write 0 0 other function h'00 ignored (no affect on pin state) 1 reserved * ? ? 1 0 input (pullup mos: on) pin state ignored (no affect on pin state) 1 input (pullup mos: off) pin state ignored (no affect on pin state) note: * operation cannot be guaranteed when this bit it set to ?reserved.? (n = 0 to 6)
section 27 i/o ports rev.6.00 mar. 27, 2009 page 854 of 1036 rej09b0254-0600 27.8 port l 27.8.1 port l data register (pldr) bit: 7 6 5 4 3 2 1 0 pl7dt pl6dt pl5dt pl4dt pl3dt pl2dt ? ? initial value: * * * * * * * * r/w: r r r r r r r r note: * undefined port l data register (pldr) is an 8-bit read register that stores data for pins ptl7 to ptl2. pl7dt to pl2dt bit corresponds to ptl7 to ptl2 pin. when the pin function is general input port, if the port is read, the corresponding pin level is read. table 27.7 shows the function of pldr. pldr is initialized to a power-on reset. it retains its previous value in software standby mode and sleep mode, and by a manual reset. table 27.7 read/write operation of the port l data register (pldr) plnmd1 plnmd0 pin state read write 0 0 other function h'00 ignored (no affect on pin state) 1 reserved * 1 ? ? 1 * input pin state ignored ( no affect on pin state) notes: * undefined (n = 2 to 7) 1. operation cannot be guaranteed when this bit it set to ?reserved.?
section 27 i/o ports rev.6.00 mar. 27, 2009 page 855 of 1036 rej09b0254-0600 27.9 sc port each pin has an input pullup mos, which is controlled by sc port control register (scpcr) in pfc. 27.9.1 port sc data register (scpdr) bit: 7 6 5 4 3 2 1 0 scp7dt scp6dt sp5dt scp4dt scp3dt scp2dt scp1dt scp0dt initial value: * 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * undefined port sc data register (scpdr) is a 7-bit read/wr ite and 1-bit read register that stores data for pins scpt7 to scpt0. scp7dt to scp0dt bit corresponds to scpt7 to scpt0 pin. when the pin function is general output port, if the port is read, the value of the corresponding scpdr bit is returned directly. when the function is general inpu t port, if the port is read, the corresponding pin level is read. table 27.8 shows the function of scpdr. scpdr is initialized to b'*0000000 by a power-on reset. after initialization, the general input port function (pullup mos: on) is set as the initial pin function, and the corresponding pin levels are read from bits scp7dt to scp5dt, scp3dt, and scp1dt. it retains its previous value in standby mode and sleep mode, and by a manual reset. note that the low level is read if bit 7 is read except in general-purpose input. set the re bit in scscr to 1, when reading rx d2 to rxd0 pin states of the scp4dt, scp2dt, and scp0dt bits in sdpdr while the te or re b it in scscr is not cleared to 0. when the re bit is set to 1, the rxd pins function as input pi ns and their states are read in preference to the scpcr setting.
section 27 i/o ports rev.6.00 mar. 27, 2009 page 856 of 1036 rej09b0254-0600 table 27.8 read/write operation of the sc port data register (scpdr) scpnmd1 scpnmd0 pin state read write 0 0 other function scpdr value value is written to scpdr, but does not affect pin state. 1 output scpdr value write value is output from pin. 1 0 input (pullup mos: on) pin state value is written to scpdr, but does not affect pin state. 1 input (pullup mos: off) pin state value is written to scpdr, but does not affect pin state. (n = 0 to 6) scpnmd1 scpnmd0 pin state read write 0 0 other function h'00 ignored (no affect on pin state) 1 reserved * ? ? 1 0 input (pullup mos: on) pin state ignored (no affect on pin state) 1 input (pullup mos: off) pin state ignored (no affect on pin state) note: * operation cannot be guaranteed when th is bit it set to ?reserved.? (n = 7)
section 28 a/d converter rev.6.00 mar. 27, 2009 page 857 of 1036 rej09b0254-0600 section 28 a/d converter 28.1 overview this lsi includes a 10-bit successive-approximation a/d converter with a selection of up to six analog input channels. 28.1.1 features a/d converter features are listed below. ? 10-bit resolution ? six input channels ? high-speed conversion ? conversion time: maximum 15 s per channel (with 33-mhz peripheral clock) ? three conversion modes ? single mode: a/d conversion of one channel ? multi mode: a/d conversion on one to four channels ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers ? a/d conversion results are transferred for storag e into data registers corresponding to the channels. ? sample-and-hold function ? a/d conversion can be externally triggered ? a/d interrupt requested at the end of conversion ? at the end of a/d conversion, an a/d end interrupt (adi) can be requested.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 858 of 1036 rej09b0254-0600 28.1.2 block diagram figure 28.1 shows a block diagram of the a/d converter. 10-bit d/a addra addrb addrd bus interface peripheral data bus analog multi- plexer control circuit successive approxi- mation register + ? comparator sample-and- hold circuit adi interrupt signal av ss an 2 an 3 an 4 an 5 an 6 an 7 /8 /16 adcsr adcr av cc a/d converter legend: a dcr: a/d control register a dcsr: a/d control/status register a ddra: a/d data register a a ddrb: a/d data register b a ddrc: a/d data register c a ddrd: a/d data register d internal data bus adtrg addrc figure 28.1 a/d converter block diagram
section 28 a/d converter rev.6.00 mar. 27, 2009 page 859 of 1036 rej09b0254-0600 28.1.3 input pins table 28.1 summarizes the a/d converter?s input pins. the six analog input pins are divided into two groups: group 0 (an2 , an3), and group 1 (an4 to an7). av cc and av ss are the power supply for the analog circuits in the a/d conv erter. avcc also functions as the a/d converter reference voltage. table 28.1 a/d converter pins pin name abbreviation i/o function analog power-supply pin avcc input a nalog power supply and a/d converter standard voltage analog ground pin avss input analog ground and reference voltage analog input pin 2 an2 input group 0 analog inputs analog input pin 3 an3 input analog input pin 4 an4 input group 1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 28 a/d converter rev.6.00 mar. 27, 2009 page 860 of 1036 rej09b0254-0600 28.1.4 register configuration table 28.2 summarizes the a/ d converter?s registers. table 28.2 a/d converter registers name abbreviation r/w initial value address access size a/d data register a (hi gh) addrah r h'00 h'04000080 (h'a4000080) * 2 16, 8 a/d data register a (low ) addral r h'00 h'04000082 (h'a4000082) * 2 8 a/d data register b (hi gh) addrbh r h'00 h'04000084 (h'a4000084) * 2 16, 8 a/d data register b (low ) addrbl r h'00 h'04000086 (h'a4000086) * 2 8 a/d data register c (hig h) addrch r h'00 h'04000088 (h'a4000088) * 2 16, 8 a/d data register c (low ) addrcl r h'00 h'0400008a (h'a400008a) * 2 8 a/d data register d (high) addrdh r h'00 h'0400008c (h'a400008c) * 2 16, 8 a/d data register d (low ) addrdl r h'00 h'0400008e (h'a400008e) * 2 8 a/d control/status r egister adcsr r/(w) * 1 h'00 h'04000090 (h'a4000090) * 2 8 a/d control register adcr r/w h'07 h'04000092 (h'a4000092) * 2 8 notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. only 0 can be written to bit 7, to clear the flag. 2. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 861 of 1036 rej09b0254-0600 28.2 register descriptions 28.2.1 a/d data registers a to d (addra to addrd) upper register: h bit: 15 14 13 12 11 10 9 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r lower register: l bit: 7 6 5 4 3 2 1 0 ad1 ad0 ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the converted data are transferred to upper register h (bits 7 to 0) of the a/d data register, and the lower 2 bits are transferred to lower register l (bits 7 and 6), for st orage. lower register l (bits 5 to 0) is always read as 0. table 28.3 indicates the pairings of analog input channels and a/d data registers. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 28.3 analog input channels and a/d data registers analog input channel group 0 group 1 a/d data register reserved an4 addra reserved an5 addrb an2 an6 addrc an3 an7 addrd
section 28 a/d converter rev.6.00 mar. 27, 2009 page 862 of 1036 rej09b0254-0600 28.2.2 a/d control/status register (adcsr) bit: 7 6 5 4 3 2 1 0 adf adie adst multi cks ch2 ch1 ch0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * write 0 to clear the flag. adcsr is an 8-bit read/write register that cont rols the a/d converter and indicates the status. adcsr is initialized to h'00 by a reset and in standby mode. bit 7?a/d end flag (adf): indicates the end of a/d conversion. bit 7: adf description 0 [clear condition] (initial value) (1) cleared by reading adf while adf = 1, then writing 0 in adf (2) cleared when dmac is activated by adi interrupt and addr is read 1 [set conditions] single mode: a/d conversion ends multi mode and scan mode: a/d conversion ends in all selected channels bit 6?a/d interrupt enable (adie): enables or disables the interrupt (adi) requested at the end of a/d conversion. bit 6: adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled
section 28 a/d converter rev.6.00 mar. 27, 2009 page 863 of 1036 rej09b0254-0600 bit 5?a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin. bit 5: adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; ad st is automatically cleared to 0 when conversion ends. multi mode: a/d conversion starts, cyclin g among the selected channels. after the cycling has been completed, adst is cleared to 0. scan mode: a/d conversion starts and cont inues, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. bit 4?multi mode (multi): selects single mode, multi mode or scan mode. for further information on operation in these m odes, see section 28.4, operation. bit 4: multi adcr: bit 5: scn description 0 0 single mode (initial value) 1 1 0 multi mode 1 scan mode bit 3?clock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3:cks description 0 conversion time = 536 states (maximum) (initial value) 1 conversion time = 266 states (maximum) * note: * the cks value should be set so that the a/d conversion time is 16 s (minimum).
section 28 a/d converter rev.6.00 mar. 27, 2009 page 864 of 1036 rej09b0254-0600 bits 2 to 0?channel select 2 to 0 (ch2 to ch0): these bits and the multi bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. channel selection description ch2 ch1 ch0 single mode (multi = 0) multi mode (multi = 1) 0 0 0 reserved reserved 1 reserved reserved 1 0 an2 an2 1 an3 an2, an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 28.2.3 a/d control register (adcr) bit: 7 6 5 4 3 2 1 0 trge1 trge0 scn resvd1 resvd2 ? ? ? initial value: 0 0 0 0 0 1 1 1 r/w: r/w r/w r/w r/w r/w r r r adcr is an 8-bit read/write regi ster that enables or disables external triggering of a/d conversion. adcr is initialized to h'07 by a reset and in standby mode. bits 7 and 6?trigger enable (trge1, trge0): enables or disables external triggering of a/d conversion. bit 7: trge1 bit 6: trge0 description 0 0 when an external trigger is in put, the a/d conversion does not 0 1 start (initial value) 1 0 1 1 the a/d conversion starts at t he falling edge of an input signal from the external trigger pin ( adtrg ).
section 28 a/d converter rev.6.00 mar. 27, 2009 page 865 of 1036 rej09b0254-0600 bit 5?scan mode (scn): selects multi mode or scan mode when the multi bit is set to 1. see the description of bit 4 in section 28.2.2, a/d control/status register (adcsr). bits 4 and 3?reserved (resvd1, resvd2): these bits always read 0. the write value should always be 0. bits 2 to 0?resrved: these bits are always read as 0. the write value should always be 0. 28.3 bus master interface addra to addrd are 16-bit registers, but they ar e connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. therefore, although the u pper byte can be accessed directly by the bus master, the lower byte is read th rough an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the bus master and the lo wer-byte value is transferred into temp. next, when the lower byte is read, the temp cont ents are transferred to the bus master. when reading an a/d data register, always read th e upper byte before the lower byte. it is possible to read only the upper byte, but if only the lowe r byte is read, the read value is not guaranteed. figure 28.2 shows the data flow for access to an a/d data register. see section 28.7.3, access size and read data.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 866 of 1036 rej09b0254-0600 bus interface cpu (h'aa) temp (h'40) lower byte of a/d data register [h'40] upper byte of a/d data register [h'aa] lower byte of a/d data register [h'40] upper byte of a/d data register [h'aa] upper byte read module internal data bus bus interface cpu (h'40) lower byte read module internal data bus temp (h'40) figure 28.2 a/d data register access operation (reading h'aa40)
section 28 a/d converter rev.6.00 mar. 27, 2009 page 867 of 1036 rej09b0254-0600 28.4 operation the a/d converter operates by su ccessive approximations with 10 -bit resolution. it has three operating modes: single mode, multi mode, and scan mode. 28.4.1 single mode (multi = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adf, then write 0 in adf. when the mode or analog input channel must be switched during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an2) is selected in single mode are described next. figure 28.3 shows a timing diagram for this example. 1. single mode is selected (multi = 0), input channel an2 is selected (ch2 = ch0 = 0, ch1 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrc. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt processing routine starts. 5. the routine reads adf, then writes 0 in the adf flag. 6. the routine reads and processes the conversion result (addrc = 0). 7. execution of the a/d interrupt processing rou tine ends. then, when the adst bit is set to 1, a/d conversion starts to execute 2 to 7 above.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 868 of 1036 rej09b0254-0600 channel 0 operating adie adst adf channel 1 operating channel 2 (an2) operating channel 3 (an3) operating addra addrc addrb addrd waiting waiting waiting waiting waiting waiting a/d conversion starts set * set * set * clear * clear * a/d conversion result 1 a/d conversion result 2 read result read result a/d conversion 1 a/d conversion result 2 note: * downward arrows ( ) indicate instruction execution. figure 28.3 example of a/d converter op eration (single mode, channel 2 selected)
section 28 a/d converter rev.6.00 mar. 27, 2009 page 869 of 1036 rej09b0254-0600 28.4.2 multi mode (multi = 1, scn = 0) multi mode should be selected when performing multi channel a/d conversions on one or more channels including channel 1. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an2 when ch2 = 0, and an4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel (an2 or an4) ends, conversion of the second channel (an3 or an5) starts immediately. finally, all of the specified channels are converted in a loop. the co nversion results are tran sferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during a/d conversion, to prevent incorrect operation, first clear the adst b it to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 1 (an4 to an6) are selected in multi mode are described next. figure 28.4 shows a timing diagram for this example. 1. multi mode is selected (multi = 1), channel group 1 is selected (ch2 = 1), analog input channels an4 to an6 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an4 ) is completed, the result is transferred into addra. next, conversion of the second channel (an5) starts automatically. 3. conversion proceeds in the same way through the thir d channel (an6). 4. when conversion of all selected channels (an4 to an6) is completed, the adf flag is set to 1 and adst bit is cleared to 0. if the adie bit is set to 1, an adi interrupt is requested after a/d conversion.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 870 of 1036 rej09b0254-0600 channel 0 (an4) operating adst adf channel 1 (an5) operating channel 2 (an6) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting set * clear * clear * a/d conversion result 2 waiting waiting a/d conversion result 3 a/d conversion 1 waiting a/d conversion result 1 transfer a/d conversion 3 a/d conversion a/d conversion 2 note: * downward arrows ( ) indicate instruction executed by software. figure 28.4 example of a/d co nverter operation (multi mode, channels an4 to an6 selected)
section 28 a/d converter rev.6.00 mar. 27, 2009 page 871 of 1036 rej09b0254-0600 28.4.3 scan mode (multi = 1, scn = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels including channel 1. when the adst bit in the a/d control/s tatus register (adcsr) is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an2 when ch2 = 0, an4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second cha nnel (an3 or an5) starts immediately. a/d conversion is repeated continuously on the sel ected channels until the adst bit is cleared to 0. the conversion results are transferred for storage in to the a/d data registers corresponding to the channels. when the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clea r the adst bit to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conversion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels (an4 to an6) are selected in scan mode are described next. figure 28.5 shows a timing diagram for this example. 1. scan mode is selected (multi = 1, scn = 1) , channel group 1 is selected (ch2 = 1), analog input channels an4 to an6 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an4 ) is completed, the result is transferred into addra. next, conversion of the second channel (an5) starts automatically. 3. conversion proceeds in the same way through the thir d channel (an6). 4. when conversion of all the selected channels (an4 to an6) is completed, the adf flag is set to 1 and conversion of the first channel (an4) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an4).
section 28 a/d converter rev.6.00 mar. 27, 2009 page 872 of 1036 rej09b0254-0600 adst adf channel 0 (an 0 ) operating channel 1 (an 1 ) operating channel 2 (an 2 ) operating channel 3 (an 3 ) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting waiting waiting waiting transfer a/d conversion 1 a/d conversion 4 a/d conversion 2 a/d conversion 3 a/d conversion result 1 a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 clear * clear * set * continuous a/d conversion a/d conversion 5 note: * downward arrow indicates instruction executed by software. figure 28.5 example of a/d converter operation (scan mode, channels an4 to an6 selected)
section 28 a/d converter rev.6.00 mar. 27, 2009 page 873 of 1036 rej09b0254-0600 28.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit of adcsr is set to 1, then starts conversion. figure 28.6 shows the a/d conversion timing. table 28 .4 indicates the a/d conversion time. as indicated in figure 28.6, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. th e total conversion time therefore varies within the ranges indicated in table 28.4. in multi mode and scan mode, the values given in table 28.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 536 states when cks = 0 or 266 states when cks = 1. in all cases, the cks bit in adcsr should be set according to the frequency of p so that the conversion time is within the range shown in tabl e 32.16 in section 32, el ectrical characteristics. (1) (2) p adf address write signal input sampling timing t d t spl t conv (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 28.6 a/d conversion timing
section 28 a/d converter rev.6.00 mar. 27, 2009 page 874 of 1036 rej09b0254-0600 table 28.4 a/d convers ion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay t d 17 ? 28 10 ? 17 input sampling time t spl ? 129 ? ? 65 ? a/d conversion time t conv 514 ? 525 259 ? 266 note: values in the table are numbers of states (t cyc ). 28.4.5 external tr igger input timing a/d conversion can be externally triggered. when the trge1, trge0 bits are set to 1 in adcr, external trigger input is enabled at the adtrg pin. a high-to-low transition at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d co nversion. other operations, regardless of the conversion mode, are the same as if the adst bit had been set to 1 by software. figure 28.7 shows the timing. a/d conversion p adtrg external trigger signal adst figure 28.7 external trigger input timing
section 28 a/d converter rev.6.00 mar. 27, 2009 page 875 of 1036 rej09b0254-0600 28.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 28.6 definitions of a/d conversion accuracy the a/d converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. the absolute accuracy of this a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: ? offset error ? full-scale error ? quantization error ? nonlinearity error these four error quantities are explained below using figure 28.8. in the figure, the 10 bits of the a/d converter have been simplified to 3 bits. offset error is the deviation between actual an d ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 28.8, item (1)). full-scale error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 28.8, item (2)). quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb (figure 28.8, item (3)). nonlinearity error is the de viation between actual an d ideal a/d conversion characteristics between zero voltage and full-scale voltage (figure 28.8, item (4)). note that it does not include offset, full-scal e or quantization error.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 876 of 1036 rej09b0254-0600 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs analog input voltage fs: full-scale voltage (3) quantization error ideal a/d conversion characteristics (4) nonlinearity error ideal a/d conversion characteristics actual a/d convertion characteristics (2) full-scale erro r digital output analog input voltage (1) offset error fs digital output figure 28.8 definitions of a/d conversion accuracy 28.7 usage notes when using the a/d converter, note the points listed in section 28.7.1 below. 28.7.1 setting analog input voltage ? analog input voltage range: during a/d conversion, the voltages input to the analog input pins ann should be in the range av ss ann av cc (n = 2 to 7). ? set the av cc and av ss input voltages as defined in sec tion 32, electrical characteristics. 28.7.2 processing of analog input pins to prevent damage from voltage surges at the analog input pins (an2 to an7), connect an input protection circuit like the one shown in figure 28.9. the circuit shown also includes an rc filter to suppress noise. this circuit is shown as an example; the circu it constants should be selected according to actual application co nditions. table 28.5 lis ts the analog input pin specifications and figure 28.10 shows an equivalent circuit diagram of the analog input ports.
section 28 a/d converter rev.6.00 mar. 27, 2009 page 877 of 1036 rej09b0254-0600 28.7.3 access size and read data table 28.6 shows the relationship between access si ze and read data. note the read data obtained with different access sizes, bus widths, and endian modes. the case is shown here in which h'3ff is obtained when av cc is input as an analog input. ff is the data containing the upper 8 bits of the conversion result, and c0 is the data containing the lower 2 bits. 0.01 f 10 f av cc an2 to an7 av ss superh microprocessor * 100 0.1 f note: * figure 28.9 example of analog input protection circuit 1.0 k a n2 to an7 20 pf 1 m figure 28.10 analog input pin equivalent circuit
section 28 a/d converter rev.6.00 mar. 27, 2009 page 878 of 1036 rej09b0254-0600 table 28.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 5 k table 28.6 relationship between access size and read data bus width 32 bits (d31?d0) 16 bits (d15?d0) 8 bits (d7?d0) access size command endian big little big little big little byte access mov.l mov.b mov.l mov.b #addrah,r9 @r9,r8 #addral,r9 @r9,r8 ffffffff c0c0c0c0 ffffffff c0c0c0c0 ffff c0c0 ffff c0c0 ff c0 ff c0 word access mov.l mov.w mov.l mov.w #addrah,r9 @r9,r8 #addral,r9 @r9,r8 ffxxffxx c0xxc0xx ffxxffxx c0xxc0xx ffxx c0xx ffxx c0xx ff xx c0 xx xx ff xx c0 longword access mov.l mov.l #addrah,r9 @r9,r8 ffxxc0xx ffxxc0xx ffxx c0xx c0xx ffxx ff xx c0 xx xx c0 xx ff in this table: #addrah .equ h'04000080 #addral .equ h'04000082 values are shown in hexadecimal for the case where read data is output to an external device via r8.
section 29 d/a converter rev.6.00 mar. 27, 2009 page 879 of 1036 rej09b0254-0600 section 29 d/a converter 29.1 overview this lsi includes a d/a converter with two channels. 29.1.1 features d/a converter features are listed below. ? eight-bit resolution ? two output channels ? conversion time: maximum 10 s (with 20-pf capacitive load) ? output voltage: 0 v to avcc 29.1.2 block diagram figure 29.1 shows a block diagram of the d/a converter. a v cc da 0 da 1 dacr dadr0 dadr1 module data bus bus interface on-chip data bus control circuit 8-bit d/a av ss legend: dacr: dadr0: dadr1: d/a control register d/a data register 0 d/a data register 1 figure 29.1 d/a converter block diagram
section 29 d/a converter rev.6.00 mar. 27, 2009 page 880 of 1036 rej09b0254-0600 29.1.3 i/o pins table 29.1 summarizes the d/a converter?s input and output pins. table 29.1 d/a converter pins pin name abbreviation i/o function analog power-supply pin avcc input a nalog power supply and d/a converter standard voltage analog ground pin avss input analog ground analog output pin 0 da0 out put analog output, channel 0 analog output pin 1 da1 out put analog output, channel 1 29.1.4 register configuration table 29.2 summarizes the d/ a converter?s registers. table 29.2 d/a converter registers name abbreviation r/w initial value address * 1 access size d/a data register 0 dadr0 r/w h'00 h'040000a0 (h'a40000a0) * 2 8 d/a data register 1 dadr1 r/w h'00 h'040000a2 (h'a40000a2) * 2 8 d/a control register da cr r/w h'1f h'040000a4 (h'a40000a4) * 2 8 notes: these registers are located in area 1 of ph ysical space. therefore, when the cache is on, either access these registers from the p2 area of logical space or else make an appropriate setting using the mmu so that these registers are not cached. 1. lower 16 bits of the address 2. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 29 d/a converter rev.6.00 mar. 27, 2009 page 881 of 1036 rej09b0254-0600 29.2 register descriptions 29.2.1 d/a data registers 0 and 1 (dadr0/1) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the d/a data registers (dadr0 and dadr1) are 8-bit read/write registers that store the data to be converted. when analog output is enabled, the d/a data register values are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset. 29.2.2 d/a control register (dacr) bit: 7 6 5 4 3 2 1 0 daoe1 daoe0 dae ? ? ? ? ? initial value: 0 0 0 1 1 1 1 1 r/w: r/w r/w r/w r r r r r dacr is an 8-bit read/write register that contro ls the operation of the d/a converter. dacr is initialized to h'1f by a reset. bit 7?d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7: daoe1 description 0 da1 analog output is disabled (initial value) 1 channel-1 d/a conversion and da1 analog output are enabled bit 6?d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6: daoe0 description 0 da0 analog output is disabled (initial value) 1 channel-0 d/a conversion and da0 analog output are enabled
section 29 d/a converter rev.6.00 mar. 27, 2009 page 882 of 1036 rej09b0254-0600 bit 5?d/a enable (dae): controls d/a conversion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, d/a conversion is controlled independently in channels 0 and 1. when this lsi enters standby mode while d/a conversion is enabled, the d/a output is held and the analog power-supply current is equivalent to that during d/a conversion. to reduce the analog power-supply current in standby mode, clear the daoe0 and daoe1 bits and disable the d/a output. bit 7: daoe1 bit 6: daoe0 bit 5: dae description 0 0 ? d/a conversion is disabled in channels 0 and 1 (initial value) 0 1 0 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 0 1 1 d/a conversion is enabled in channels 0 and 1 1 0 0 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 1 0 1 d/a conversion is enabled in channels 0 and 1 1 1 ? d/a conversion is enabled in channels 0 and 1 when the dae bit is set to 1, even if bits daoe0 and daoe1 in da cr and the adst bit in adcsr are cleared to 0, the same current is dr awn from the analog power supply as during a/d and d/a conversion. bits 4 to 0?reserved: read-only bits, always read as 1.
section 29 d/a converter rev.6.00 mar. 27, 2009 page 883 of 1036 rej09b0254-0600 29.3 operation the d/a converter has two built- in d/a conversion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. an example of d/a conversion on channel 0 is given next. timing is indicated in figure 29.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversion starts and da0 becomes an output pin. the converted result is output after the conversion time. the output value is (dadr0 contents/256) avcc. output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle t dconv high-impedance state conversion result 1 conversion data 1 conversion data 2 conversion result 2 t dconv p a ddress bus dadr0 daoe0 da0 dacr write cycle dadr0 write cycle dacr write cycle legend: t dconv : d/a conversion time figure 29.2 example of d/a converter operation
section 29 d/a converter rev.6.00 mar. 27, 2009 page 884 of 1036 rej09b0254-0600
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 885 of 1036 rej09b0254-0600 section 30 pc card controller (pcc) 30.1 overview the pc card controller (pcc) controls the external buffer, interrupts, and exclusive ports of the pc card interface to be connected to the SH7727. using the pcc enables two slots of pc cards that conform to the pcmcia rev. 2.1/jeida ver. 4.2 standard to be easily connected to the SH7727. 30.1.1 features the pcc has the following features: ? as a pc card interface to be connected to physical area 6, an ic memory card interface and an i/o card interface are supported. ? outputs control signals for the external buffer ( pcc0drv ). ? supports a preemptive operating system by switching attribute memory, common memory, and i/o space by using addresses. ? provides a segment bit (an address bit for th e pc card) for common memory, enabling access to a 64-mb space fully conformi ng to pcmcia specifications. ? disables the pcc operation and supports only a bu s interface of a pc card interface which is same as the sh7709/sh7729 series (by using the p0use bit of pcc0gcr). ? when the pcc is enabled (p0use bit in pcc0gcr set to 1), pcc0wait functions as a wait signal in the same manner as wait .
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 886 of 1036 rej09b0254-0600 30.1.2 block diagram figure 30.1 shows a block diagram of the pc card controller. pc card controller (pcc) area 6 pc card interface signals area 6 internal interrupt signals pcc0wait pcc0reset pcc0drv iois16 (pcc0wp) pcc0rdy( ireq ) pcc0bvd1( stschg ) pcc0bvd2(spkr) pcc0cd1 pcc0cd2 pcc0vs1 pcc0vs2 pccreg battery dead software interrupt rdy/bsy signal change internal data bus card detection signal change internal bus control signal stschg signal change area 6: an ic memory card interface and an i/o card interface are supported. area 6 register (0:3) and register control register selection bus interface interrupt controller battery warning ireq signal figure 30.1 pc card controller block diagram
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 887 of 1036 rej09b0254-0600 30.1.3 register configuration table 30.1 lists the pc card controller registers. table 30.1 pc card controller registers physical area register name symbol read/ write initial value address access size physical area 6 (pcc0) area 6 interface status register pcc0isr r * 1 h'04000160 (h'a4000160) * 2 8 bits area 6 general control register pcc0gcr r/w h'00 h'04000162 (h'a4000162) * 2 8 bits area 6 card status change register pcc0cscr r/w h'00 h'04000164 (h'a4000164) * 2 8 bits area 6 card status change interrupt enable register pcc0cscier r/w h'00 h'04000166 (h'a4000166) * 2 8 bits notes: 1. depends on the pc card status. 2. when address translation by the mmu do es not apply, the address in parentheses should be used.
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 888 of 1036 rej09b0254-0600 30.1.4 pcmcia support the SH7727 supports an interf ace based on pcmcia specifications for physical areas 6. interfaces supported are the ic memory card interface and i/o card interf ace defined in the pcmcia rev. 2.1/jeida ver. 4.2 standard. both the ic memory card interface and i/o card interface are supported in area 6. table 30.2 features of the pcmcia interface item feature access random access data bus 8/16 bits memory type mask rom, otprom, eprom, eeprom, flash memory, sram common memory capacity maximum 64 mbytes (supports full pcmcia specifications by using a segment bit (an address bit for the pc card)) attribute memory capaci ty maximum 32 mbytes i/o space capacity maximum 32 mbytes others dynamic bus sizing for i/o bus width * the pcmcia interface can be accessed from the address- conversion region and non-address-conversion region. note: * dynamic bus sizing for the i/o bus width is supported only in little-endian mode. the SH7727 can directly access 32- and 64-mb phy sical areas in a 64-mb memory space and an i/o space of the pc card (continuous 32 /16-mb area mode). the sh 7727 provides a segment bit (an address bit for the pc card) in the general control register for area 6 to support a common memory space with full pcmcia specifications (64 mb).
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 889 of 1036 rej09b0254-0600 continuous 32-mb area mode: setting 0 (initial value) in bit 3 (p0mmod) of the general control register enables the continuous 32-mb area mode. in this mode, the attribute memory space and i/o memory space are 32 mb and th e common memory space is 64 mb. in the common memory space, set 1 in b it 2 (p0pa25) of the general control register to access an address of more than 32 mb. by this operation, 1 is output to a25 pin, enabling an address space of more than 32 mb to be accessed. when an address of 32 mb or less is accessed, no setting is required (initial value: 0). th is bit does not affect access to attribute memory space or i/o memory space. figure 30.2 shows the relationship between the memory space of the SH7727 and the memory and i/o spaces of the pc card in th e continuous 32-mb ar ea mode. although memory space and i/o space are supported in area 6. in area 6, set 1 in bit 0 (p0reg) of the gene ral control register to access the common memory space of the pc card, and set 0 in bit 0 to access th e attribute memory space (initial value: 0). by this operation, the set value is output to pccreg pin, enabling any space to be accessed. when the i/o space is accessed in area 6, the output of pccreg pin is always 0 regardless of the value of bit 0 (p0reg). see the register descriptions in section 30.2, register descriptions for details of register settings. SH7727 memory space pc card address space general control register bit settings p0mmod = 0 p0pa24 = x p0pa25 = x p0reg = 0 (attribute) p0pa25 = 0 p0reg = 1 (common memory) p0pa25 = 0 p0reg = 1 (common memory) p0pa25 = x p0reg = x pin pccreg is always 0 attribute memory/ common memory 32 mb i/o space 32 mb p0reg p0pa25 h'18000000 h'1a000000 x: don't care area 6 32 mb i/o space common mermoy 32 mb total 64 mb attribute memory figure 30.2 continuo us 32-mb area mode
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 890 of 1036 rej09b0254-0600 continuous 16-mb area mode: setting 1 in bit 3 (p0mmod) of the general control register enables the continuous 16 -mb area mode. in this mode, th e attribute memory space and i/o memory space are 16 mb, and the common memory space is 64 mb. in the common memory space, set the pc card address in b it 2 (p0pa25) and bit 1 (p0pa24) of the general control register to access an address of more than 16 mb. by th is operation, values ar e output to a25 and a24 pins, enabling an address space of more than 16 mb to be accessed (initial value: 0 for p0pa25 and p0pa24). when an address of 16 mb or less is accessed, no settings are required. this bit does not affect access to attribute memory space or i/o memory space. figure 30.3 shows the relationship between the memory space of the SH7727 and the memory and i/o spaces of the pc card in th e continuous 16-mb ar ea mode. although memory space and i/o space are supported in area 6. the attribute memory space, common memory space, and i/o space of the pc card are provided as 16-mb physical spaces in this mode. ther efore, the SH7727 automatically controls pccreg pin (the value of bit 0 (p0reg) in the general control register is ignored). in area 6, the output of pccreg pin is 0 when the attribute memory space or i/o space is accessed, and 1 when the common memory space is accessed. see the register descriptions in section 30.2, register descriptions for details of register settings. SH7727 memory space pc card address space general control register bit settings p0mmod = 1 p0reg = x attribute memory 16 mb (pin pccreg is alwys 0) i/o space 16 mb (pin pccreg is alwys 0) attribute memory common memory i/o space 16 mb 16 mb 16 mb p0pa25 = x, p0pa24 = x p0pa25 = 0, p0pa24 = 0 p0pa25 = 0, p0pa24 = 1 p0pa25 = 1, p0pa24 = 0 p0pa25 = 1, p0pa24 = 1 common mermoy (pin pccreg is always 1) total 64 mb not used h'18000000 h'1a000000 p0pa25 = x, p0pa24 = x x: don't care area 6 p0pa25 p0pa24 figure 30.3 continuous 16-mb area mode (area 6)
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 891 of 1036 rej09b0254-0600 30.2 register descriptions 30.2.1 area 6 interface status register (pcc0isr) bit: 7 6 5 4 3 2 1 0 bit name: p0rdy/ ireq p0mwp p0vs2 p0vs1 p0cd2 p0cd1 p0bvd2 spkr p0bvd1 stschg initial value: * * * * * * * * r/w: r r r r r r r r note: * depends on the pc card status. the area 6 interface status register (pcc0isr) is an 8-bit read-only register which is used to read the status of the pc card connected to area 6. the initial value of pcc0isr depends on the pc card status. bit 7?pcc0 ready (p0rdy/ireq): the value of rdy/ bsy pin of the pc card connected to area 6 is read when the ic memory card interface is connected. the value of ireq pin of the pc card connected to area 6 is read when the i/o card interface is connected . this bit cannot be written to. bit 7: p0rdy/ireq description 0 indicates that the value of rdy/ bsy pin is 0 when the pc card connected to area 6 is the ic memory card interfac e type. indicates that the value of ireq pin is 0 when the pc card connected to area 6 is the i/o card interface type 1 indicates that the value of rdy/ bsy pin is 1 when the pc card connected to area 6 is the ic memory card interfac e type. indicates that the value of ireq pin is 1 when the pc card connected to area 6 is the i/o card interface type
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 892 of 1036 rej09b0254-0600 bit 6?pcc0 write protect (p0mwp): the value of wp pin of the pc card connected to area 6 is read when the ic memory card interface is conn ected. 0 is read when the i/o card interface is connected. this bit cannot be written to. bit 6: p0mwp description 0 indicates that the value of wp pin is 0 when the pc card connected to area 6 uses the ic memory card interface. the value of bit 6 is always 0 when the pc card connected to area 6 is the i/o card interface type 1 indicates that the value of wp pin is 1 when the pc card connected to area 6 is the ic memory card interface type bit 5?pcc0 voltage sense 2 (p0vs2): the value of vs2 pin of the pc card connected to area 6 is read. this bit cannot be written to. bit 5: p0vs2 description 0 the value of vs2 pin of the pc card connected to area 6 is 0 1 the value of vs2 pin of the pc card connected to area 6 is 1 bit 4?pcc0 voltage sense 1 (p0vs1): the value of vs1 pin of the pc card connected to area 6 is read. this bit cannot be written to. bit 4: p0vs1 description 0 the value of vs1 pin of the pc card connected to area 6 is 0 1 the value of vs1 pin of the pc card connected to area 6 is 1 bit 3?pcc0 card detect 2 (p0cd2): the value of cd2 pin of the pc card connected to area 6 is read. this bit cannot be written to. bit 3: p0cd2 description 0 the value of cd2 pin of the pc card connected to area 6 is 0 1 the value of cd2 pin of the pc card connected to area 6 is 1
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 893 of 1036 rej09b0254-0600 bit 2?pcc0 card detect 1 (p0cd1): the value of cd1 pin of the pc card connected to area 6 is read. this bit cannot be written to. bit 2: p0cd1 description 0 the value of cd1 pin of the pc card connected to area 6 is 0 1 the value of cd1 pin of the pc card connected to area 6 is 1 bits 1 and 0?pcc0 battery voltage detect 2 and 1 (p0bvd2, p0bvd1): the values of bvd2 and bvd1 pins of the pc card connected to area 6 are read when the ic memory card interface is connected. the values of spkr and stschg pins of the pc card connected to area 6 are read when the i/o card interface is c onnected. these bits cannot be written to. ? ic memory interface bit 1: p0bvd2 bit 0: p0bvd1 description 1 1 the battery voltage of the pc card connected to area 6 is normal (battery good) 0 1 the battery must be changed although data is guaranteed for the pc card connected to area 6 (battery warning) 1 0 the battery voltage is abnormal and data is not guaranteed for the pc card connected to area 6 (battery dead) 0 0 the battery voltage is abnormal and data is not guaranteed for the pc card connected to area 6 (battery dead) ? i/o card interface bit 1: p0spkr description 0 the value of spkr pin of the pc card connected to area 6 is 0 1 the value of spkr pin of the pc card connected to area 6 is 1 bit 0: p0stschg description 0 the value of stschg pin of the pc card connected to area 6 is 0 1 the value of stschg pin of the pc card connected to area 6 is 1
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 894 of 1036 rej09b0254-0600 30.2.2 area 6 general control register (pcc0gcr) bit: 7 6 5 4 3 2 1 0 bit name: p0drve p0pccr p0pcct p0use p0mmo d p0pa25 p0pa24 p0reg initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the area 6 general control register (pcc0gcr) is an 8-bit readable/writable register which controls the external buffer, resets, address a25 and a24 pins, and reg pin, and sets the pc card type for the pc card connected to area 6. pcc0 gcr is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. bit 7?pcc0 buffer control (p0drve): controls the external buffer for the pc card connected to area 6. bit 7: p0drve description 0 high-level setting for control pcc0drv pin of the external buffer for the pc card connected to area 6 (initial value) 1 low-level setting for control pcc0drv pin of the external buffer for the pc card connected to area 6 bit 6?pcc0 card reset (p0pccr): controls resets for the pc card connected to area 6. bit 6: p0pccr description 0 low-level setting for reset pcc0reset pin for the pc card connected to area 6 (initial value) 1 high-level setting for reset pcc0reset pin for the pc card connected to area 6 bit 5?pcc0 card type (p0pcct): specifies the type of the pc card connected to area 6. cleared to 0 when the pc card is the ic memory card interface type; set to 1 when the pc card is the i/o card interface type. bit 5: p0pcct description 0 the pc card connected to area 6 is handled as the ic memory card interface type (initial value) 1 the pc card connected to area 6 is handled as the i/o card interface type
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 895 of 1036 rej09b0254-0600 bit 4?pcc0 use/not use (p0use): specifies that the pc card co ntroller to be work or not work. bit 4: p0use description 0 pc card controller doesn?t work. 1 pc card controller works. bit 3?pcc0 mode (p0mmod): controls pccreg and a24 pins for the pc card connected to area 6. specifies either a24 of the address to be accessed or bit p0reg for outputting to pccreg pin. when the common memory space is acce ssed, specifies either a24 of the address to be accessed or bit p0pa24 for outputting to a24 pin. by this operation, continuous 32 or 16 mbytes can be selected for th e address area of the common memory space of the pc card. bit 3: p0mmod description 0 bit p0reg is output to pccreg pin, and a24 of address to be accessed is output to a24 pin (continuous 32-mb area mode) (initial value) 1 a24 of address to be accessed is output to pccreg pin. when the common memory space is accessed, p0pa24 is output to a24 pin (continuous 16-mb area mode) bit 2?pc card address (p0pa25): controls a25 pin for the pc card connected to area 6. when the common memory space is accessed for the pc card connected to area 6, this bit is output to a25 pin. when the attribute memory space or i/o space is accessed, this bit is meaningless. bit 2: p0pa25 description 0 when the common memory space is accessed for the pc card connected to area 6, 0 is output to a25 pin (initial value) 1 when the common memory space is accessed for the pc card connected to area 6, 1 is output to a25 pin
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 896 of 1036 rej09b0254-0600 bit 1?pc card address (p0pa24): controls a24 pin for the pc card connected to area 6. when bit p0mmod is 1 and the common memory sp ace is accessed for the pc card connected to area 6, this bit is output to a24 pin. when b it p0mmod is 0 or the attribute memory space or i/o space is accessed, this bit is meaningless. bit 1: p0pa24 description 0 when bit p0mmod is 1 and the common memory space is accessed for the pc card connected to area 6, 0 is output to a24 pin (initial value) 1 when bit p0mmod is 1 and the common memory space is accessed for the pc card connected to area 6, 1 is output to a24 pin bit 0?pcc0reg space indication (p0reg): controls pccreg pin for the pc card connected to area 6. when bit p0mmod is 0, this bit is output to pccreg pin for the pc card connected to area 6. when bit p0 mmod is 1 or the i/o card inte rface is accessed, this bit is meaningless. bit 0: p0reg description 0 when bit p0mmod is 0 and the pc card connected to area 6 is accessed, 0 is output to pccreg pin (initial value) 1 when bit p0mmod is 0 and the pc card connected to area 6 is accessed, 1 is output to pccreg pin 30.2.3 area 6 card status change register (pcc0cscr) bit: 7 6 5 4 3 2 1 0 bit name: p0scdi ? p0ireq p0sc p0cdc p0rc p0bw p0bd initial value: 0 0 0 0 0 0 0 0 r/w: r/w ? r/w r/w r/w r/w r/w r/w the area 6 card status change register (pcc0cscr) is an 8-bit readable/writable able register. pcc0cscr bits are set to 1 by interrupt sources of the pc card connected to area 6 (only bit 7 can be set to 1 as required). pcc0cscr is initialized by a power-on reset but retains its value in a manual reset and in software standby mode.
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 897 of 1036 rej09b0254-0600 bit 7?pcc0 software card det ect change int errupt (p0scdi): a pcc0 software card detect change interrupt can be generated by writing 1 to this bit. when this bit is set to 1, the same interrupt as the pcc0 card detect change interr upt (bit 3 set status) occurs if bit 3 (pcc0 card detect change enable) in the area 6 card status ch ange interrupt enable register (pcc0cscier) is set to 1. if bit 3 is cleared to 0, no interrupt occurs. bit 7: p0scdi description 0 no software card detect change interr upt occurs for the pc card connected to area 6 (initial value) 1 software card detect change interrupt occurs for the pc card connected to area 6 bit 6?reserved: always reads 0. the write value should always be 0. bit 5?pcc0ireq request (p0ireq): indicates the interrupt request for the ireq pin of the pc card when the pc card connected to area 6 is th e i/o card interface type. the p0ireq bit is set to 1 when an interrupt request signal in pulse mode or level mode is input to the ireq pin. the mode is selected by bits 5 and 6 (pcc0ireq interrupt enable bits) in the area 6 card status change interrupt enable register (pcc0cscier). this bit can be cleared to 0 only in pulse mode. write 0 to bit 5 to clear the bit to 0. this bit is not changed if 1 is written. in level mode, bit 5 is a read-only bit which reflects the ireq pin state (if the ireq pin is low, 1 is read). this bit always reads 0 on the ic memory card interface. bit 5: ireq description 0 no interrupt request on the ireq pin of the pc card when the pc card is on the i/o card interface (initial value) 1 an interrupt request on the ireq pin of the pc card has occurred when the pc card is on the i/o card interface
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 898 of 1036 rej09b0254-0600 bit 4?pcc0 status change (p0sc): indicates a change in the value of the stschg pin of the pc card when the pc card connected to area 6 is the i/o card interface type. when the stschg pin is changed from 1 to 0, the p 0 sc bit is set to 1. when stschg pin is not changed, the p0sc bit remains at 0. write 0 to bit 4 when this bit is se t to 1 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the ic memory card interface. bit 4: p0sc description 0 stschg pin of the pc card is not changed when the pc card is on the i/o card interface (initial value) 1 stschg pin of the pc card is changed from 1 to 0 when the pc card is on the i/o card interface bit 3?pcc0 card detect change (p0cdc): indicates a change in the value of the cd1 and cd2 pins in the pc card connect ed to area 6. when the cd1 and cd2 values are changed, the p0cdc bit is set to 1. when the values are not changed, the p0cdc bit remains at 0. write 0 to bit 3 in order to clear this bit to 0. this bit is not changed if 1 is written. bit 3: p0cdc description 0 cd1 and cd2 pins in the pc card are not changed (initial value) 1 cd1 and cd2 pins in the pc card are changed bit 2?pcc0 ready change (p0rc): indicates a change in the value of the rdy/ bsy pin of the pc card when the pc card co nnected to area 6 is the ic memory card interface type. when the rdy/ bsy pin is changed from 0 to 1, the p0rc bit is set to 1. when the rdy/ bsy pin is not changed, the p0rc bit remains at 0. write 0 to bit 2 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit alwa ys reads 0 on the i/o card interface. bit 2: p0rc description 0 rdy/ bsy pin in the pc card is not changed when the pc card is on the ic memory card interfac e (initial value) 1 rdy/ bsy pin in the pc card is changed from 0 to 1 when the pc card is on the ic memory card interface
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 899 of 1036 rej09b0254-0600 bit 1?pcc0 battery warning (p0bw): indicates whether the bvd2 and bvd1 pins of the pc card are in the state in which ?the battery must be changed although the da ta is guaranteed? when the pc card connected to area 6 is on the ic memory card interface. when the bvd2 and bvd1 pins are 0 and 1, respectively, the p0bw bit is set to 1; in other cases, the p0bw bit remains at 0. this bit is updated when the bvd2 and bvd1 pins are changed. write 0 to bit 1 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the i/o card interface. bit 1: p0bw description 0 bvd2 and bvd1 of the pc card are not in the battery warning state when the pc card is in the ic memory card interface (initial value) 1 bvd2 and bvd1 of the pc card are in the battery warning state and ?the battery must be changed although the data is guaranteed? when the pc card is on the ic memory card interface bit 0?pcc0 battery dead (p0bd): indicates whether the bvd2 and bvd1 pins of the pc card are in the state in which ?the battery must be changed since the data is not guaranteed? when the pc card connected to area 6 is on the ic memory card interface. when the bvd2 and bvd1 pins are 1 and 0 or 0 and 0, the p0bd b it is set to 1; in other cases, the p0bd bit remains at 0. this bit is updated when the bvd2 and bvd1 pins are changed. write 0 to bit 0 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the i/o card interface. bit 0: p0bd description 0 bvd2 and bvd1 of the pc card are no t in the state in which ?the battery must be changed since the data is not guaranteed? when the pc card is on the ic memory card inte rface (initial value) 1 bvd2 and bvd1 of the pc card are in the state in which ?the battery must be changed since the data is not guaranteed? when the pc card is on the ic memory card interface
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 900 of 1036 rej09b0254-0600 30.2.4 area 6 card stat us change interrupt enab le register (pcc0cscier) bit: 7 6 5 4 3 2 1 0 bit name: p0cre ireqe1 ireqe0 p0sce p0cde p0re p0bwe p0bde initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the area 6 card status change interrupt en able register (pcc0cscier) is an 8-bit readable/writable register. p cc0cscier enables or disables interrupt requests for interrupt sources for the pc card connected to area 6. wh en a pcc0cscier is set to 1, the corresponding interrupt is enabled, and when the bit is cleared to 0, the interrupt is disabled. pcc0cscier is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. bit 7?pcc0 card reset enable (p0cre): when this bit is set to 1, and when the cd1 and cd2 pins detect that a pc card is connected to area 6, the area 6 general control register (pcc0gcr) is initialized. bit 7: p0cre description 0 the area 6 general control register (p cc0gcr) is not initialized even if a pc card is detected in area 6 (initial value) 1 the area 6 general control register (pcc0gcr) is initialized when a pc card is detected connected to area 6
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 901 of 1036 rej09b0254-0600 bits 6 and 5?pcc0ireq request enable (ireqe1, ireqe0): these bits enable or disable ireq pin interrupt requests and select the interrupt mode when the pc card connected to area 6 is the i/o card interface type. note that bit 5 (p0ire q) in the area 6 card st atus change register (pcc0cscr) is cleared if the values in bits 6 and 5 in this register are changed. these bits have no meaning on the ic memory card interface. bit 6: ireqe1 bit 5: ireqe0 description 0 0 ireq requests are not accepted for the pc card connected to area 6. bit 5 in the status change register (p cc0cscr) functions as a read-only bit that indicates the inverse of the ireq pin signal. (initial value) 0 1 the level-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in level mode, an interrupt occurs when level 0 of the signal input from the ireq pin is detected. 1 0 the pulse-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in pulse mode, an interrupt occurs when a falling edge from 1 to 0 of the signal input from the ireq pin is detected. 1 1 the pulse-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in pulse mode, an interrupt occurs when a rising edge from 0 to 1 of the signal input from the ireq pin is detected. bit 4?pcc0 status change enable (p0sce): when the pc card connected to area 6 is on the i/o card interface, bit 4 enables or disables the interrupt request when the value of the bvd1 pin ( stschg pin) is changed. this bit has no meaning in the ic memory card interface. bit 4: p0sce description 0 no interrupt occurs for the pc card connected to area 6 regardless of the value of the bvd1 pin ( stschg pin) (initial value) 1 an interrupt occurs for the pc card connected to area 6 when the value of the bvd1 pin ( stschg pin) is changed from 1 to 0 bit 3?pcc0 card detect change enable (p0cde): bit 3 enables or disables the interrupt request when the values of the cd1 and cd2 pins are changed. bit 3: p0cde description 0 no interrupt occurs for the pc card connected to area 6 regardless of the values of the cd1 and cd2 pins (initial value) 1 an interrupt occurs for the pc card connected to area 6 when the values of the cd1 and cd2 pins are changed
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 902 of 1036 rej09b0254-0600 bit 2?pcc0 ready change enable (p0re): when the pc card connected to area 6 is on the ic memory card interface, bit 2 enables or disables the interrupt request when the value of the rdy/ bsy pin is changed. this bit has no meaning on the i/o card interface. bit 2: p0re description 0 no interrupt occurs for the pc card connected to area 6 regardless of the value of the rdy/ bsy pin (initial value) 1 an interrupt occurs for the pc card connected to area 6 when the value of the rdy/ bsy pin is changed from 0 to 1 bit 1?pcc0 battery warning enable (p0bwe): when the pc card connected to area 6 is on the ic memory card interface, bit 1 enables or di sables the interrupt request when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed although the data is guaranteed?. this bit has no meaning on the i/o card interface. bit 1: p0bwe description 0 no interrupt occurs when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed although the data is guaranteed? (initial value) 1 an interrupt occurs when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed although the data is guaranteed? bit 0?pcc0 battery dead enable (p0bde): when the pc card connected to area 6 is on the ic memory card interface, bit 0 enables or disa bles the interrupt request when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed since the data is not guaranteed?. this bit has no m eaning on the i/o card interface. bit 0: p0bde description 0 no interrupt occurs when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed since the data is not guaranteed? (initial value) 1 an interrupt occurs when the bvd2 and bvd1 pins are in the state in which ?the battery must be changed since the data is not guaranteed?
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 903 of 1036 rej09b0254-0600 30.3 operation 30.3.1 pc card connection specification (interface di agram, pin correspondence) a25 to a0 d15 to d0 pcc0drv rd/ wr ce1b ce2b rd we iciord iciowr pcc0reset pccreg a25 to a0 d15 to d0 cd1 cd2 vs1 vs2 ce1 ce2 oe we /pgm ( iord ) ( iowr ) reset reg area 6 pc card (memory or i/o) g g g dir dir g d7 to d0 d15 to d8 pcc0wait iois16 pcc0rdy pcc0bvd1 pcc0bvd2 wait wp( iois16 ) rdy/ bsy ( ireq ) bvd1 ( stschg ) bvd2 ( spkr ) g pcc0cd1 / cd2 pcc0vs1 / vs2 SH7727 figure 30.4 SH7727 interface
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 904 of 1036 rej09b0254-0600 table 30.3 pcmcia support interface ic memory card interface i/o card interface pin signal name i/o function signal name i/o function SH7727 corresponding pin 1 gnd ground gnd ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable ce1b 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we / pgm i write enable we / pgm i write enable we 16 rdy/ bsy o ready/busy ireq o interrupt request pcc0rdy 17 vcc power supply vcc power supply ? 18 vpp1 programming power supply vpp1 programming and peripheral power supply ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2 28 a1 i address a1 i address a1
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 905 of 1036 rej09b0254-0600 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function SH7727 corresponding pin 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp o write protect iois16 o 16-bit i/o port iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection pcc0cd1 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2b 43 vs1 o voltage sense vs1 o voltage sense pcc0vs1 44 rfu reserved iord i i/o read iciord 45 rfu reserved iowr i i/o write iciowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 vcc power supply vcc power supply ? 52 vpp2 programming power supply vpp2 programming and peripheral power supply ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address a25 57 vs2 o voltage sense vs2 o voltage sense pcc0vs2
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 906 of 1036 rej09b0254-0600 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function SH7727 corresponding pin 58 reset i reset reset i reset pcc0reset 59 wait o wait request wait o wait request pcc0wait 60 rfu reserved inpack o input acknowledge ? 61 reg i attribute memory space select reg i attribute memory space select pccreg 62 bvd2 o battery voltage detection spkr o digital sound signal pcc0bvd2 63 bvd1 o battery voltage detection stschg o card status change pcc0bvd1 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection pcc0cd2 68 gnd ground gnd ground ?
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 907 of 1036 rej09b0254-0600 30.3.2 pc card interface timing (1) memory card interface timing ckio tpcm1 tpcm2 a 25 to a0 pcc0drv rd/ wr cexx rd (read) d15 to d0 (read) we (write) d15 to d0 (write) pccreg pcc0reset 0 0 figure 30.5 pcmcia memory card interface basic timing
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 908 of 1036 rej09b0254-0600 ckio a 25 to a0 d15 to d0 (write) d15 to d0 (read) tpcm0 tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w pcc0reset 0 0 pcc0drv pcc0wait rd/ wr cexx rd (read) we (write) pccreg figure 30.6 pcmcia memory card interface wait timing
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 909 of 1036 rej09b0254-0600 ckio tpci1 tpci2 a 25 to a0 pcc0drv iciord (at read) d15 to d0 (read) iciowr (write) d15 to d0 (write) pcc0reset 0 rd/ wr cexx pccreg figure 30.7 pcmcia i/o card interface basic timing
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 910 of 1036 rej09b0254-0600 ckio a 25 to a0 d15 to d0 (write) d15 to d0 (read) pcc0wait iois16 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w pcc0reset 0 0 pcc0drv iciord (read) iciowr (write) rd/ wr cexx pccreg figure 30.8 pcmcia i/o card interface wait timing
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 911 of 1036 rej09b0254-0600 tpci0 tpci1 tpci1w tpci2 tpci1 tpci1w tpci2 tpci2w ckio 0 0 a 25 to a1 a 0 d15 to d0 (write) d15 to d0 (read) pcc0wait iois16 pcc0reset pcc0drv iciord (read) iciowr (write) rd/ wr cexx pccreg figure 30.9 dynamic bus sizing timi ng for pcmcia i/o card interface refer to section 12, bus state controller (bsc), and section 32, electrical characteristics, for more details.
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 912 of 1036 rej09b0254-0600 30.3.3 usage notes external bus frequency limit when using pc card: according to the pc card standard, the attribute memory access time is specified as 600 ns (3.3 v)/300 ns (5 v). theref ore, when the SH7727 accesses attribute memory, the bus cycle mu st be coordinated with the pc card interface timing. in the SH7727, the timing can be adjusted by setting the ted and teh values in the pcr register, and the number of waits and number of idle states in the wcr1 and wcr2 registers, allowing a pc card to be used within the above frequency ranges. the common memory access time and i/o access time (based on the iord and iowr signals) are also similarly specified (see table below), and a pc card must be used within the above ranges in order to satisfy all these specifications. pc card space access time (5 v operation) access time (3.3 v operation) attribute memory 300 ns 600 ns common memory 250 ns 600 ns i/o space (? iord /? iowr pulse width) 165 ns 165 ns pin function control and card type switching: when setting pin function controller pin functions to dedicated pc card use ("other function"), the disabled state should first be set in the card status change interrupt enable register (pcc0cscier). also, the card status change register (pcc0cscr) must be cleared after the setting has been made. however, this restriction does not apply to the card detection pins ( cd1 , cd2 ). when changing the card type bit (p0pcct) in the area 6 general control register (pcc0gcr), the disabled state should first be set in the card status change interrupt enable register (pcc0cscier). also, the card status change re gister (pcc0cscr) must be cleared after the setting has been made. reason: when pc card controller settings are modified, the functions of pc card pins that generate various interrupts change, with the result that unnecessary interrupts may be generated.
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 913 of 1036 rej09b0254-0600 setting procedure when using pc card controller: the following steps should be followed when using a card controller: 1. drive pin asemd0 high. 2. set bit 0 (a6pcm) in bus control register 1 (bcr1) in the bus state controller to 1. 3. set bit 4 (p0use) in the area 6 general control register in the pc card controller to 1. 4. set the pin function controller to custom pc card pin functions (?other functions?).
section 30 pc card controller (pcc) rev.6.00 mar. 27, 2009 page 914 of 1036 rej09b0254-0600
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 915 of 1036 rej09b0254-0600 section 31 user-deb ugging interface (h-udi) 31.1 overview the SH7727 incorporates a user-debugging in terface (h-udi) and advanced user debugger (aud) for program debugging. 31.2 user debugging interface (h-udi) the h-udi (user-debugging interface) performs on-chip debugging which is supported by the SH7727. the h-udi described here is a serial interface which is compatible with jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary- scan architecture) specifications. the h-udi in the SH7727 supports a boundary scan mode, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the emulator manual for the method of connecting the emulator. 31.2.1 pin description tck: h-udi serial data input/output clock pin. da ta is serially supplied to the h-udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronization with this clock. tms: mode select input pin. the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol conforms to the jtag standard (ieee std. 1149.1). trst : h-udi reset input pin. input is accepted as ynchronously with respect to tck, and when low, the h-udi is reset. see section 31.4.2 , reset configuration, for more information. tdi: h-udi serial data input pin. data transfer to the h-udi is ex ecuted by changing this signal in synchronization with tck. tdo: h-udi serial data output pin. data output from the h-udi is executed by reading this signal in synchronization with tck. asemd0 : the ase mode select pin. if a low level is input to the asemd0 pin while the resetp pin is asserted, ase mode is entered, and if a high level is input, normal mode is entered. when using the user system alone and not using an emulator or the h-udi, a high level
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 916 of 1036 rej09b0254-0600 should be input. in ase mode, boundary scan and emulator functions can be used. hold the input level to the asemd0 pin for at least one cycle after the resetp pin is negated. asebrkak : dedicated emulator pin. 31.2.2 block diagram figure 31.1 shows the block diagram of the h-udi. sdir sdid tck tdo tdi tms trst mux shift register tap controller decoder local bus figure 31.1 h-udi block diagram 31.3 register descriptions the h-udi has the following registers. ? sdir: instruction register ? sdid: device identification register ? sdbsr: boundary-scan register
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 917 of 1036 rej09b0254-0600 table 31.1 shows h-udi register configuration. table 31.1 h-udi registers cpu side h-udi side name abbreviation r/w size address r/w size initial value * instruction register sdir r 16 h?04000200 r/w 16 h?ffff device identification register sdid ? ? ? r 32 h?0004200f boundary-scan register sdbsr ? ? ? r/w ? undefined note: * initialized when trst pin is low or when tap is in the test-logic-reset state. 31.3.1 bypass register (sdbpr) the bypass register (sdbpr) is a 1-bit register that cannot be accessed by the cpu. setting the sdir register to the bypass mode makes the sdbpr register to be connected between the tdi and tdo h-udi pins. 31.3.2 instruction register (sdir) the instruction register (sdir) is a 16-bit read-only register. the register is in bypass mode in its initial state. it is initialized by trst or in the tap test-logic-reset state, and can be written by the h-udi irrespective of the cpu mode. operation is not guaranteed when a reserved command is set to this register. bit: 15 14 13 12 11 10 9 8 ti3 ti2 ti1 ti0 ? ? ? ? initial value: 1 1 1 1 1 1 1 1 bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 1 1 1 1 1 1 1 1 bits 15 to 12?test instruction bits (ti3 to ti0): cannot be written by the cpu.
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 918 of 1036 rej09b0254-0600 table 31.2 h-udi commands ti3 ti2 ti1 ti0 description 0 0 0 0 extest 0 1 0 0 sample/preload 0 1 0 1 reserved 0 1 1 0 h-udi reset negate 0 1 1 1 h-udi reset assert 1 0 0 ? reserved 1 0 1 ? h-udi interrupt 1 1 0 ? reserved 1 1 1 0 reserved 1 1 1 1 bypass mode (initial value) 0 0 0 1 recovery from sleep bits 11 to 0?reserved: always read 1. 31.3.3 boundary-scan register (sdbsr) boundary-scan register (sdbsr) is a shift register allocated on the pad to control the i/o pins in this lsi. the boundary-scan test is available in complian ce with the jtag standard by using the extest and sample/preload instructions. table 31.3 lis ts the correspondence between the SH7727 pins and the boundary-scan register.
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 919 of 1036 rej09b0254-0600 table 31.3 correspondence between SH7727 pins a nd boundary-scan register bit pin name i/o from tdi 391 d31/ptb7 in 390 d30/ptb6 in 389 d29/ptb5 in 388 d28/ptb4 in 387 d27/ptb3 in 386 d26/ptb2 in 385 d25/ptb1 in 384 d24/ptb0 in 383 d23/pta7 in 382 d22/pta6 in 381 d21/pta5 in 380 d20/pta4 in 379 d19/pta3 in 378 d18/pta2 in 377 d17/pta1 in 376 d16/pta0 in 375 d15 in 374 d14 in 373 d13 in 372 d12 in 371 d11 in 370 d10 in 369 d9 in 368 d8 in 367 d7 in 366 d6 in 365 d5 in 364 d4 in 363 d3 in 362 d2 in 361 d1 in 360 d0 in bit pin name i/o 359 md1 in 358 md2 in 357 nmi in 356 irq0/ irl0 /pth0 in 355 irq1/ irl1 /pth1 in 354 irq2/ irl2 /pth2 in 353 irq3/ irl3 /pth3 in 352 irq4/pth4 in 351 md5 in 350 breq in 349 vepwc out 348 vcpwc out 347 back out 346 d31/ptb7 out 345 d30/ptb6 out 344 d29/ptb5 out 343 d28/ptb4 out 342 d27/ptb3 out 341 d26/ptb2 out 340 d25/ptb1 out 339 d24/ptb0 out 338 d23/pta7 out 337 d22/pta6 out 336 d21/pta5 out 335 d20/pta4 out 334 d19/pta3 out 333 d18/pta2 out 332 d17/pta1 out 331 d16/pta0 out 330 d15 out 329 d14 out 328 d13 out 327 d12 out
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 920 of 1036 rej09b0254-0600 bit pin name i/o 326 d11 out 325 d10 out 324 d9 out 323 d8 out 322 d7 out 321 d6 out 320 d5 out 319 d4 out 318 d3 out 317 d2 out 316 d1 out 315 d0 out 314 vepwc control 313 vcpwc control 312 back control 311 d31/ptb7 control 310 d30/ptb6 control 309 d29/ptb5 control 308 d28/ptb4 control 307 d27/ptb3 control 306 d26/ptb2 control 305 d25/ptb1 control 304 d24/ptb0 control 303 d23/pta7 control 302 d22/pta6 control 301 d21/pta5 control 300 d20/pta4 control 299 d19/pta3 control 298 d18/pta2 control 297 d17/pta1 control 296 d16/pta0 control 295 d15 control 294 d14 control 293 d13 control 292 d12 control bit pin name i/o 291 d11 control 290 d10 control 289 d9 control 288 d8 control 287 d7 control 286 d6 control 285 d5 control 284 d4 control 283 d3 control 282 d2 control 281 d1 control 280 d0 control 279 bs /ptk4 in 278 we2 /dqmul/ iciord /ptk6 in 277 we3 /dqmuu/ iciord /ptk7 in 276 audsync /pte7/pcc0rdy in 275 cs4 /ptk2 in 274 cs5 / ce1a /ptk3 in 273 ce2a /pte4 in 272 ce2b /pte5 in 271 afe_hc1/usb1d_dpls/ptk0 in 270 afe_rlycnt /usb1d_dmns/ ptk1 in 269 afe_sclk/usb1d_txdpls in 268 ptm7/pint7/afe_fs/ usb1d_rcv in 267 ptm6/pint6/afe_rxin/ usb1d_speed in 266 ptm5/pint5/afe_txout/ usb1d_txse0 in 265 a0 out 264 a1 out 263 a2 out 262 a3 out 261 a4 out 260 a5 out
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 921 of 1036 rej09b0254-0600 bit pin name i/o 259 a6 out 258 a7 out 257 a8 out 256 a9 out 255 a10 out 254 a11 out 253 a12 out 252 a13 out 251 a14 out 250 a15 out 249 a16 out 248 a17 out 247 a18 out 246 a19 out 245 a20 out 244 a21 out 243 a22 out 242 a23 out 241 a24 out 240 a25 out 239 bs /ptk4 out 238 rd out 237 we0 /dqmll out 236 we1 /dqmlu/ we out 235 we2 /dqmul/ iciord /ptk6 out 234 we3 /dqmuu/ iciowr /ptk7 out 233 rd/ wr out 232 audsync /pte7/pcc0rdy out 231 cs0 out 230 cs2 out 229 cs3 out 228 cs4 /ptk2 out 227 cs5 / ce1a /ptk3 out 226 cs6 / ce1b out 225 ce2a /pte4 out bit pin name i/o 224 ce2b /pte5 out 223 afe_hc1/usb1d_dpls/ptk0 out 222 afe_rlycnt / usb1d _dmns/ ptk1 out 221 afe_sclk/usb1d_txdpls out 220 ptm7/pint7/afe_fs/ usb1d_rcv out 219 ptm6/pint6/afe_rxin/ usb1d_speed out 218 ptm5/pint5/afe_txout/ usb1d_txse0 out 217 a0 control 216 a1 control 215 a2 control 214 a3 control 213 a4 control 212 a5 control 211 a6 control 210 a7 control 209 a8 control 208 a9 control 207 a10 control 206 a11 control 205 a12 control 204 a13 control 203 a14 control 202 a15 control 201 a16 control 200 a17 control 199 a18 control 198 a19 control 197 a20 control 196 a21 control 195 a22 control 194 a23 control 193 a24 control
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 922 of 1036 rej09b0254-0600 bit pin name i/o 192 a25 control 191 bs /ptk4 control 190 rd control 189 we0 /dqmll control 188 we1 /dqmlu/we control 187 we2 /dqmul/ iciord /ptk6 control 186 we3 /dqmuu/ iciowr /ptk7 control 185 rd/ wr control 184 audsync /pte7/pcc0rdy control 183 cs0 control 182 cs2 control 181 cs3 control 180 cs4 /ptk2 control 179 cs5 / ce1a /ptk3 control 178 cs6 / ce1b control 177 ce2a /pte4 control 176 ce2b /pte5 control 175 afe_hc1/usb1d_dpls/ptk0 control 174 afe_rlycnt / usb1d _dmns/ ptk1 control 173 afe_sclk/usb1d_txdpls control 172 ptm7/pint7/afe_fs/ usb1d_rcv control 171 ptm6/pint6/afe_rxin/ usb1d_speed control 170 ptm5/pint5/afe_txout/ usb1d_txse0 control 169 ptm4/pint4/ afe_rdet in 168 reserved/usb1d_suspend0 in 167 usb1_ovr_current /usbf_vbus in 166 usb2_ovr_current in 165 rts2 /usb1d_txenl in 164 pte2/usb1_pwr_en in 163 pte1/usb2_pwr_en in 162 cke/ptk5 in 161 ras /ptj0 in bit pin name i/o 160 reserved/ptj1 in 159 reserved/ cas /ptj2 in 158 reserved/ptj3 in 157 reserved/ptj4 in 156 reservedptj5 in 155 cl1/ptd5 in 154 don/ptd7 in 153 m_disp/pte6 in 152 flm/pte3 in 151 wait in 150 audck/pth6/ pcc0wait in 149 iois16 /ptg7 in 148 asebrkak /ptg5 in 147 ptg4 in 146 audata3/ptg3/pcc0bvd2 in 145 audata2/ptg2/pcc0bvd1 in 144 audata1/ptg1/ pcc0cd2 in 143 audata0/ptg0/ pcc0cd1 in 142 pth5/ adtrg in 141 ptf3/pint11/reserved in 140 ptf2/ pccreg /reserved in 139 ptf1/ pcc0vs1 /reserved in 138 ptf0/ pcc0vs2 /reserved in 137 md0 in 136 ptm4/pint4/ afe_rdet out 135 reserved/usb1d_suspend0 out 134 rts2 /usb1d_txenl out 133 pte2/usb1_pwr_en out 132 pte1/usb2_pwr_en out 131 cke/ptk5 out 130 ras /ptj0 out 129 reserved/ptj1 out 128 reserved/ cas /ptj2 out 127 reserved/ptj3 out 126 reserved/ptj4 out
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 923 of 1036 rej09b0254-0600 bit pin name i/o 125 reserved/ptj5 out 124 cl1/ptd5 out 123 don/ptd7 out 122 m_disp/pte6 out 121 flm/pte3 out 120 pcc0reset/drak0 out 119 pcc0drv /dack0 out 118 asebrkak/ptg5 out 117 audata3/ptg3/pcc0bvd2 out 116 audata2/ptg2/pcc0bvd1 out 115 audata1/ptg1/ pcc0cd2 out 114 audata0/ptg0/ pcc0cd1 out 113 ptf3/pint11/reserved out 112 ptf2/ pccreg /reserved out 111 ptf1/ pcc0vs1 /reserved out 110 ptf0/ pcc0vs2 /reserved out 109 ptm4/pint4/ afe_rdet control 108 reserved/usb1d_suspend0 control 107 rts2 /usb1d_txenl control 106 pte2/usb1_pwr_en control 105 pte1/usb2_pwr_en control 104 cke/ptk5 control 103 ras /ptj0 control 102 reserved/ptj1 control 101 reserved/ cas /ptj2 control 100 reserved/ptj3 control 99 reserved/ptj4 control 98 reserved/ptj5 control 97 cl1/ptd5 control 96 don/ptd7 control 95 m_disp/pte6 control 94 flm/pte3 control 93 pcc0reset/drak0 control 92 pcc0drv /dack0 control 91 asebrkak /ptg5 control bit pin name i/o 90 audata3/ptg3/pcc0bvd2 control 89 audata2/ptg2/pcc0bvd1 control 88 audata1/ptg1/ pcc0cd2 control 87 audata0/ptg0/ pcc0cd1 control 86 ptf3/pint11/reserved control 85 ptf2/ pccreg /reserved control 84 ptf1/ pcc0vs1 /reserved control 83 ptf0/ pcc0vs2 /reserved control 82 ptm3/lcd15/pint10 in 81 ptm2/lcd14/pint9 in 80 ptm1/lcd13/pint8 in 79 ptm0/lcd12 in 78 status0/ptj6 in 77 status1/ptj7 in 76 cl2/pth7 in 75 sck0/scpt1 in 74 siomclk/scpt3 in 73 sck_sio/scpt5 in 72 siofsync/scpt6 in 71 rxd0/scpt0 in 70 rxd2/scpt4 in 69 lcd7/ptd3 in 68 lcd6/ptd2 in 67 lcd1/ptd1 in 66 lcd0/ptd0 in 65 dreq0 /ptd4 in 64 lclk/uclk/ptd6 in 63 rxd_sio/scpt2 in 62 cts2 /irq5/scpt7 in 61 lcd11/ptc7/pint3 in 60 lcd10/ptc6/pint2 in 59 lcd9/ptc5/pint1 in 58 lcd8/ptc4/pint0 in 57 lcd5/ptc3 in 56 lcd4/ptc2 in
section 31 user-debugging interface (h-udi) rev.6.00 mar. 27, 2009 page 924 of 1036 rej09b0254-0600 bit pin name i/o 55 lcd3/ptc1 in 54 lcd2/ptc0 in 53 md3 in 52 md4 in 51 ptm3/lcd15/pint10 out 50 ptm2/lcd14/pint9 out 49 ptm1/lcd13/pint8 out 48 ptm0/lcd12 out 47 status0/ptj6 out 46 status1/ptj7 out 45 cl2/pth7 out 44 txd0/scpt0 out 43 sck0/scpt1 out 42 txd_sio/scpt2 out 41 siomclk/scpt3 out 40 txd2/scpt4 out 39 sck_sio/scpt5 out 38 siofsync/scpt6 out 37 lcd11/ptc7/pint3 out 36 lcd10/ptc6/pint2 out 35 lcd9/ptc5/pint1 out 34 lcd8/ptc4/pint0 out 33 lcd7/ptd3 out 32 lcd6/ptd2 out 31 lcd5/ptc3 out 30 lcd4/ptc2 out 29 lcd3/ptc1 out 28 lcd2/ptc0 out 27 lcd1/ptd1 out bit pin name i/o 26 lcd0/ptd0 out 25 ptm3/lcd15/pint10 control 24 ptm2/lcd14/pint9 control 23 ptm1/lcd13/pint8 control 22 ptm0/lcd12 control 21 status0/ptj6 control 20 status1/ptj7 control 19 cl2/pth7 control 18 txd0/scpt0 control 17 sck0/scpt1 control 16 txd_sio/scpt2 control 15 siomclk/scpt3 control 14 txd2/scpt4 control 13 sck_sio/scpt5 control 12 siofsync/scpt6 control 11 lcd11/ptc7/pint3 control 10 lcd10/ptc6/pint2 control 9 lcd9/ptc5/pint1 control 8 lcd8/ptc4/pint0 control 7 lcd7/ptd3 control 6 lcd6/ptd2 control 5 lcd5/ptc3 control 4 lcd4/ptc2 control 3 lcd3/ptc1 control 2 lcd2/ptc0 control 1 lcd1/ptd1 control 0 lcd0/ptd0 control to tdo note: control is a signal that is active in its lo w level. setting the control signal to low level drives the corresponding pin with the out value.
section 31 user-debugging interface (h-udi) rev. 5.00 dec 12, 2005 page 925 of 1034 rej09b0254-0500 31.4 h-udi operations 31.4.1 tap controller figure 31.2 shows the internal states of tap co ntroller. state transitions basically conform with the jtag standard. tset-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 1 0 1 1 10 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 0 1 0 1 1 10 figure 31.2 tap controller state transitions note: the transition condition is the tms value on the rising edge of tck. the tdi value is sampled on the rising edge of tck; shifting occurs on the falling edge of tck. the tdo value changes on the tck falling edge. the tdo is at high impedance, except with shift- dr (shift-sr) and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck.
section 31 user-debugging interface (h-udi) rev. 5.00 dec 12, 2005 page 926 of 1034 rej09b0254-0500 31.4.2 reset configuration table 31.4 reset configuration asdmd0 * 1 resetp trst chip state h l l normal reset and h-udi reset h normal reset h l h-udi reset only h normal operation l l l reset hold * 2 h ase user mode * 3 : normal reset ase break mode * 3 : resetp assertion masked h l h-udi reset only h normal operation notes: 1. performs main chip mode and ase mode settings asemd0 = h, main chip mode asemd0 = l, ase mode when user system is used alone without using emulator or h-udi, set asemd0 to h. 2. during ase mode, reset hold is enabled by setting resetp and trst pins at low level for a constant cycle. in this state, the cpu does not start up, even if resetp is set to high level. when trst is set to high level, h-udi op eration is enabled, but the cpu does not start up. the reset hold state is cancelled by the following: ? boot request from h-udi (boot sequence) ? another resetp assert (power-on reset) 3. there are two ase modes, one for executin g software in the emulator?s firmware (ase break mode) and one for executing user software (ase user mode).
section 31 user-debugging interface (h-udi) rev. 5.00 dec 12, 2005 page 927 of 1034 rej09b0254-0500 31.4.3 h-udi reset an h-udi reset is executed by setting an h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h-udi reset is released by inputting an h-udi reset negate command. h-udi reset negate sdir chip internal reset cpu state branch to h'a0000000 h-udi reset assert figure 31.3 h-udi reset 31.4.4 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command from the h-udi in the sdir. an h-udi interrupt is a general exception /interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are not accepted in sleep mode or standby mode. 31.4.5 bypass setting the command from h-udi to sdir allows to set the h-udi pins to the bypass mode that conforms with the jtag standard. 31.4.6 using h-udi to recover from sleep mode it is possible to recover from sleep mode by setting a command (0001) from the h-udi in sdir.
section 31 user-debugging interface (h-udi) rev. 5.00 dec 12, 2005 page 928 of 1034 rej09b0254-0500 31.5 usage notes 1. an h-udi command other than an h-udi interrupt , once set, will not be modified as long as another command is not re-issued from the h-udi. an h-udi interrupt command, however, will be changed to a bypass command once set. 2. because chip operations are suspended in st andby mode, h-udi commands are not accepted. however, the tap controller remains in operation at this time. 3. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. 31.6 advanced user debugger (aud) the aud is a function exclusively for use by an emulator. refer to the user's manual for the relevant emulator for details of the aud.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 929 of 1036 rej09b0254-0600 section 32 electrical characteristics 32.1 absolute maximum ratings table 32.1 shows the absolute maximum ratings. table 32.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) vccq ?0.3 to 4.2 v power supply voltage (internal) vcc vcc ? pll1 vcc ? pll2 vcc ? rtc ?0.3 to 2.5 v input voltage (except port l) vin ?0.3 to vccq + 0.3 v input voltage (port l) vin ?0.3 to avcc + 0.3 v analog power-supply voltage avcc ?0.3 to 4.6 v usb power-supply voltage avcc_usb ?0.3 to 4.2 v analog input voltage v an ?0.3 to avcc + 0.3 v operating temperature topr ?20 to 75 c storage temperature tstr ?55 to 125 c caution: operating the chip in excess of the absolute maximum rating may result in permanent damage. ? order of turning on 1.9 v power (vcc, vcc-pll1, vcc-pll2, vcc-rtc) and 3.3 v power (vccq, avcc, avcc_usb): 1. first turn on the 3.3 v powe r, then turn on the 1.9 v power within 1 ms. this interval should be as short as possible. 2. until voltage is applied to all power supplies, a low level is input at the resetp pin and, a maximum of 4 ckio clock cycles have been ge nerated, internal circuits remain unsettled, and so pin states are also undefined. the syst em design must ensure that these undefined states do not cause erroneous system operation. note that the resetp pin will not accept low level input while the ca pin is low level. 3. the state of pins md5 to md0 should be established after power supply startup and maintained until after the resetp pin is negated. read-in of pins md5 to md0 is always performed while the resetp pin is asserted. waveforms at power-on are shown in the following figure 32.1.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 930 of 1036 rej09b0254-0600 pin states undefined (max. 1 ms) 3.3 v 1.9 v 3.3 v power 1.9 v power resetp a ll other pins * pin states undefined power-on reset state note: * except power/gnd, clock related, and analog pins figure 32.1 power-on sequence ? power-off order 1. in the reverse order of powering-on, first turn off the 1.9 v power, then turn off the 3.3 v power within 1 ms. this interval should be as short as possible. 2. pin states are undefined while only the 1.9 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 931 of 1036 rej09b0254-0600 32.2 dc characteristics tables 32.2 and 32.3 list dc characteristics. table 32.2 dc characteristics (1) condition: ta = ?20 to 75c item symbol min typ max unit measurement conditions power supply voltage 3.0 ? 3.6 160 mhz products v cc q 2.6 ? 3.6 100 mhz products 1.70 ? 2.05 160 mhz products v cc , v cc -pll1, v cc -pll2, v cc -rtc * 1 1.60 ? 2.05 v 100 mhz products analog (a/d, d/a) power- supply voltage av cc * 2 3.0 3.3 3.6 v same potential as vccq when not used analog usb power-supply voltage av cc _usb 3.0 3.3 3.6 v same potential as vccq when not used during a/d conversion ? 0.8 2 ma during a/d and d/a conversion ? 2.4 6 ma analog (a/d, d/a) power- supply current idle ai cc ? 0.01 5.0 ma ta = 25 c current dissipation normal operation i cc * 3 ? 330 650 ma ta = 25 c, vcc = 1.9 v, i = 160 mhz, x/y memory on, cache on, and renesas test program operating ? 260 ? ta = 25 c, vcc = 1.9 v, i = 160 mhz, x/y memory off, cache on, and renesas test program operating
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 932 of 1036 rej09b0254-0600 item symbol min typ max unit measurement conditions ? 250 450 ta = 25 c, vcc = 1.9 v, i = 100 mhz, x/y memory on, cache on, and renesas test program operating i cc * 3 ? 190 ? ta = 25 c, vcc = 1.9 v, i = 100 mhz, x/y memory off, cache on, and renesas test program operating normal operation i cc q ? 20 ? ma v cc q = 3.3 v b = 33 mhz in sleep mode * 1 i sleep ? 40 50 ma total vcc + vccq, vcc = 1.9 v, vccq = 3.3 v, b = 33 mhz, and no external bus cycles except refresh cycles i cc ? 30 120 ta = 25 c (with rtc clock input) * 4 current dissipation in standby mode i cc q ? 10 30 a ta = 25 c (with rtc clock input) * 4 notes: 1. regardless of whether the pll or rtc is used, connect vcc?pll and vcc?rtc to vcc, and vss?pll and vss?rtc to vss. 2. avcc conditions must be: vccq ? 0.3 v avcc vccq + 0.3 v. if the a/d and d/a converters are not used, do not leave the avcc and avss pins open. connect avcc to vccq, and connect avss to vssq. 3. current dissipation values are for v ih min = vccq ? 0.5 v and v il max = 0.5 v with all output pins in the no-load state. 4. there is no stipulation regarding the powe r supply in standby mode when there is no rtc clock input.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 933 of 1036 rej09b0254-0600 table 32.2 dc characteristics (2) condition: ta = ?20 to 75c item symbol min typ max unit measurement conditions resetp , resetm , nmi, irq5 to irq0, md5 to md0, irl3 to irl0 , pint15 to pint0, asemd0 , adtrg , trst , extal, ckio, ca v cc q 0.9 ? v cc q + 0.3 extal2 ? ? ? connect to vcc-rtc when no crystal resonator is connected port l 2.0 ? av cc + 0.3 input high voltage other input pins v ih 2.0 ? v cc q + 0.3 v input low voltage resetp , resetm , nmi v il ?0.3 ? v cc q 0.1 v ?0.3 ? 0.5 standby mode breq , irq5 to irq0, md5 to md0 ?0.3 ? v cc q 0.2 normal operation port l ?0.3 ? av cc 0.2 other input pin ?0.3 ? v cc q 0.2 input leak current all input pins |iin| ? ? 1.0 a vin = 0.5 to v cc q ? 0.5 v three-state leak current i/o, all output pins (off condition) |isti| ? ? 1.0 a vin = 0.5 to v cc q ? 0.5 v v oh 2.4 ? ? v v cc q = 3.0 v, i oh = ?200 a output high voltage all output pins 2.0 ? ? v v cc q = 3.0 v, i oh = ?2ma output low voltage all output pins v ol ? ? 0.55 v v cc q = 3.6 v, i ol = 1.6 ma
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 934 of 1036 rej09b0254-0600 item symbol min typ max unit measurement conditions pull-up resistance port pin ppull 30 60 120 k pins other than analog pins c ? ? 10 pf pin capacity analog pins * c an ? ? 20 pf note: * there are four analog pins, usb1_p, usb2_p, usb1_m, and usb2_m. table 32.3 permitted output current values conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.0 to 3.6 v, ta = ?20 to 75c item symbol min typ max unit output low-level permissible current (per pin) i ol ? ? 2.0 ma output low-level permissible current (total) i ol ? ? 120 ma output high-level permissible current (per pin) ?i oh ? ? 2.0 ma output high-level permissible current (total) (?i oh ) ? ? 40 ma caution: to ensure lsi reliability, do not exceed the value for output current given in table 32.3. 32.3 ac characteristics in general, inputting for this lsi should be clock synchronous. keep the setup and hold times for each input signal unless otherwise specified. regarding the power supply and frequency specifications of the individual products, refer to figure 32.2, tables 32.2 and 32.4.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 935 of 1036 rej09b0254-0600 vccq (v) i = 24 to 100 mhz b = 24 to 50 mhz p = 6 * to 33.34 mhz i = 24 to 100 mhz b = 24 to 33.34 mhz p = 6 * to 33.34 mhz i = 24 to 160 mhz b = 24 to 66.67 mhz p = 6 * to 33.34 mhz i = 24 to 144 mhz b = 24 to 50 mhz p = 6 * to 33.34 mhz 3.6 3.0 vccq (v) 3.6 3.0 2.6 1.60 1.70 1.70 1.75 2.05 vcc (v) 2.05 vcc (v) (1) 100 mhz products (2) 160 mhz products note: * when using the usb function controller, select a peripheral clock (p ) setting of 13 mhz or above. figure 32.2 power supply vo ltage and operating frequency
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 936 of 1036 rej09b0254-0600 table 32.4 maximum opera ting frequencies (1) item symbol min max unit power supply voltage conditions reference products cpu, cache, tlb (i ) 24 100 v cc = 1.60 to 2.05 v v cc q = 2.6 to 3.6 v ? 24 33.34 v cc = 1.60 to 2.05 v v cc q = 2.6 to 3.6 v table 32.5 external bus (b ) or ckio i/o frequency 24 50 v cc = 1.70 to 2.05 v v cc q= 3.0 to 3.6 v table 32.6 peripheral modules (p ) f 6 33.34 mhz v cc = 1.60 to 2.05 v v cc q = 2.6 to 3.6 v ? 100 mhz products table 32.4 maximum opera ting frequencies (2) item symbol min max unit power supply voltage conditions reference products 24 144 v cc = 1.70 to 2.05 v v cc q= 3.0 to 3.6 v ? cpu, cache, tlb (i ) 24 160 v cc = 1.75 to 2.05 v v cc q= 3.0 to 3.6 v ? 24 50 v cc = 1.70 to 2.05 v v cc q= 3.0 to 3.6 v table 32.7 external bus (b ) or ckio i/o frequency 24 66.67 v cc = 1.75 to 2.05 v v cc q= 3.0 to 3.6 v table 32.8 peripheral modules (p ) f 6 33.34 mhz v cc = 1.70 to 2.05 v v cc q= 3.0 to 3.6 v ? 160 mhz products
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 937 of 1036 rej09b0254-0600 32.3.1 clock timing table 32.5 clock timing (1) conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c, 100 mhz products item symbol min max unit figure extal clock input frequency f ex 6 33.34 mhz 32.3 extal clock input cycle time t excyc 30 166.7 ns extal clock input low pulse width t exl 9 ? ns extal clock input high pulse width t exh 9 ? ns extal clock input rise time t exr ? 6 ns extal clock input fall time t exf ? 6 ns ckio clock input frequency f cki 24 33.34 mhz 32.4 ckio clock input cycle time t ckicyc 30 41.7 ns ckio clock input low pulse width t ckil 9 ? ns ckio clock input high pulse width t ckih 9 ? ns ckio clock input rise time t ckir ? 6 ns ckio clock input fall time t ckif ? 6 ns ckio clock output frequency f op 24 33.34 mhz 32.5 ckio clock output cycle time t cyc 30 41.7 ns ckio clock output low pulse width t ckol 8 ? ns ckio clock output high pulse width t ckoh 8 ? ns ckio clock output rise time t ckor ? 6 ns ckio clock output fall time t ckof ? 6 ns ckio2 clock output delay time t ck2d ? 2.5 ns ckio2 clock output rise time t ck2or ? 7 ns ckio2 clock output fall time t ck2of ? 7 ns power-on oscillation settling time t osc1 10 ? ms 32.6 resetp setup time (at power on and cancellation of standby mode) t resps 20 ? ns 32.6, 32.7 resetm setup time (at cancellation of standby mode) t resms 0 ? ns resetp assert time (at power on and cancellation of standby mode) t respw 20 ? t cyc resetm assert time (at cancellation of standby mode) t resmw 20 ? t cyc standby return oscillation settling time 1 t osc2 10 ? ms 32.7 standby return oscillation settling time 2 t osc3 10 ? ms 32.8 standby return oscillation settling time 3 t osc4 11 ? ms 32.9 pll synchronization settling ti me 1 (at cancellation of standby mode) t pll1 100 ? s 32.10, 32.11 pll synchronization settling time 2 (at multiplier change) t pll2 100 ? s 32.12 irq/irl interrupt determination time (rtc used and standby mode) t irqstb 100 ? s 32.11
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 938 of 1036 rej09b0254-0600 table 32.6 clock timing (2) conditions: vccq = 3.0 to 3.6 v, vcc = 1.70 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c, 100 mhz products item symbol min max unit figure extal clock input frequency f ex 6 50 mhz 32.3 extal clock input cycle time t excyc 20 166.7 ns extal clock input low pulse width t exl 4 ? ns extal clock input high pulse width t exh 4 ? ns extal clock input rise time t exr ? 6 ns extal clock input fall time t exf ? 6 ns ckio clock input frequency f cki 24 50 mhz 32.4 ckio clock input cycle time t ckicyc 20 41.7 ns ckio clock input low pulse width t ckil 4 ? ns ckio clock input high pulse width t ckih 4 ? ns ckio clock input rise time t ckir ? 6 ns ckio clock input fall time t ckif ? 6 ns ckio clock output frequency f op 24 50 mhz 32.5 ckio clock output cycle time t cyc 20 41.7 ns ckio clock output low pulse width t ckol 3 ? ns ckio clock output high pulse width t ckoh 3 ? ns ckio clock output rise time t ckor ? 5 ns ckio clock output fall time t ckof ? 5 ns ckio2 clock output delay time t ck2d ? 2.5 ns ckio2 clock output rise time t ck2or ? 7 ns ckio2 clock output fall time t ck2of ? 7 ns power-on oscillation settling time t osc1 10 ? ms 32.6 resetp setup time (at power on and cancellation of standby mode) t resps 20 ? ns 32.6, 32.7 resetm setup time (at cancellation of standby mode) t resms 0 ? ns resetp assert time (at power on and cancellation of standby mode) t respw 20 ? t cyc resetm assert time (at cancellation of standby mode) t resmw 20 ? t cyc standby return oscillation settling time 1 t osc2 10 ? ms 32.7 standby return oscillation settling time 2 t osc3 10 ? ms 32.8 standby return oscillation settling time 3 t osc4 11 ? ms 32.9 pll synchronization settling ti me 1 (at cancellation of standby mode) t pll1 100 ? s 32.10, 32.11 pll synchronization settling time 2 (at multiplier change) t pll2 100 ? s 32.12 irq/irl interrupt determination time (rtc used and standby mode) t irqstb 100 ? s 32.11
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 939 of 1036 rej09b0254-0600 table 32.7 clock timing (3) conditions: vccq = 3.0 to 3.6 v, vcc = 1.70 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c, 160 mhz products item symbol min max unit figure extal clock input frequency f ex 6 50 mhz 32.3 extal clock input cycle time t excyc 20 166.7 ns extal clock input low pulse width t exl 4 ? ns extal clock input high pulse width t exh 4 ? ns extal clock input rise time t exr ? 6 ns extal clock input fall time t exf ? 6 ns ckio clock input frequency f cki 24 50 mhz 32.4 ckio clock input cycle time t ckicyc 20 41.7 ns ckio clock input low pulse width t ckil 4 ? ns ckio clock input high pulse width t ckih 4 ? ns ckio clock input rise time t ckir ? 6 ns ckio clock input fall time t ckif ? 6 ns ckio clock output frequency f op 24 50 mhz 32.5 ckio clock output cycle time t cyc 20 41.7 ns ckio clock output low pulse width t ckol 3 ? ns ckio clock output high pulse width t ckoh 3 ? ns ckio clock output rise time t ckor ? 5 ns ckio clock output fall time t ckof ? 5 ns ckio2 clock output delay time t ck2d ? 2.5 ns ckio2 clock output rise time t ck2or ? 7 ns ckio2 clock output fall time t ck2of ? 7 ns power-on oscillation settling time t osc1 10 ? ms 32.6 resetp setup time (at power on and cancellation of standby mode) t resps 20 ? ns 32.6, 32.7 resetm setup time (at cancellation of standby mode) t resms 0 ? ns resetp assert time (at power on and cancellation of standby mode) t respw 20 ? t cyc resetm assert time (at cancellation of standby mode) t resmw 20 ? t cyc standby return oscillation settling time 1 t osc2 10 ? ms 32.7 standby return oscillation settling time 2 t osc3 10 ? ms 32.8 standby return oscillation settling time 3 t osc4 11 ? ms 32.9 pll synchronization settling ti me 1 (at cancellation of standby mode) t pll1 100 ? s 32.10, 32.11 pll synchronization settling time 2 (at multiplier change) t pll2 100 ? s 32.12 irq/irl interrupt determination time (rtc used and standby mode) t irqstb 100 ? s 32.11
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 940 of 1036 rej09b0254-0600 table 32.8 clock timing (4) conditions: vccq = 3.0 to 3.6 v, vcc = 1.75 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c, 160 mhz products item symbol min max unit figure extal clock input frequency f ex 6 66.67 mhz 32.3 extal clock input cycle time t excyc 15 166.7 ns extal clock input low pulse width t exl 1.5 ? ns extal clock input high pulse width t exh 1.5 ? ns extal clock input rise time t exr ? 6 ns extal clock input fall time t exf ? 6 ns ckio clock input frequency f cki 24 66.67 mhz 32.4 ckio clock input cycle time t ckicyc 15 41.7 ns ckio clock input low pulse width t ckil 1.5 ? ns ckio clock input high pulse width t ckih 1.5 ? ns ckio clock input rise time t ckir ? 6 ns ckio clock input fall time t ckif ? 6 ns ckio clock output frequency f op 24 66.67 mhz 32.5 ckio clock output cycle time t cyc 15 41.7 ns ckio clock output low pulse width t ckol 3 ? ns ckio clock output high pulse width t ckoh 3 ? ns ckio clock output rise time t ckor ? 5 ns ckio clock output fall time t ckof ? 5 ns ckio2 clock output delay time t ck2d ? 2.5 ns ckio2 clock output rise time t ck2or ? 7 ns ckio2 clock output fall time t ck2of ? 7 ns power-on oscillation settling time t osc1 10 ? ms 32.6 resetp setup time (at power on and cancellation of standby mode) t resps 20 ? ns 32.6, 32.7 resetm setup time (at cancellation of standby mode) t resms 0 ? ns resetp assert time (at power on and cancellation of standby mode) t respw 20 ? t cyc resetm assert time (at cancellation of standby mode) t resmw 20 ? t cyc standby return oscillation settling time 1 t osc2 10 ? ms 32.7 standby return oscillation settling time 2 t osc3 10 ? ms 32.8 standby return oscillation settling time 3 t osc4 11 ? ms 32.9 pll synchronization settling ti me 1 (at cancellation of standby mode) t pll1 100 ? s 32.10, 32.11 pll synchronization settling time 2 (at multiplier change) t pll2 100 ? s 32.12 irq/irl interrupt determination time (rtc used and standby mode) t irqstb 100 ? s 32.11
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 941 of 1036 rej09b0254-0600 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il extal * (input) note: * the clock input from the extal pin. figure 32.3 extal clock input timing t ckih t ckif t ckir t ckil t ckicyc v ih 1/2 v cc q 1/2 v cc q v ih v il v ih v il ckio (input) figure 32.4 ckio clock input timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 942 of 1036 rej09b0254-0600 t cyc t ckol t ckoh v oh 1/2v cc q ckio (output) 1/2v cc q t ckor t ckof t ck2d t ck2d v oh v ol v ol v oh v oh v oh v oh v ol v ol ckio2 (output) t ck2or t ck2of figure 32.5 ckio clock output timing v cc q min t resp/mw t resp/ms t osc1 v cc q resetp ckio, internal clock stable oscillation note: oscillation settling time when built-in oscillator is used figure 32.6 power-on oscillation settling time
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 943 of 1036 rej09b0254-0600 ckio, internal clock stable oscillation standby t osc2 t resp/mw resetp resetm note: oscillation settling time when built-in oscillator is used figure 32.7 oscillation settling time at standby return (return by reset) ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when built-in oscillator is used figure 32.8 oscillation settling time at standby return (return by nmi)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 944 of 1036 rej09b0254-0600 ckio, internal clock stable oscillation standby t osc4 irq4 to irq0 pint0/1 note: oscillation settling time when built-in oscillator is used figure 32.9 oscillation sett ling time at standby return (return by irq4 to irq0) extal input, ckio input stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status0 status1 pll synchronization note: pll oscillation setting time when clock is input from extal pin or ckio pin in continuous oscillation mode. t pll1 pll synchronization figure 32.10 pll synchronization se ttling time by reset or nmi interrupt
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 945 of 1036 rej09b0254-0600 extal input, ckio input stable input clock irq4 ? irq0/ irl3 ? irl0 interrupt request stable input clock normal normal pll output, ckio output internal clock status0 status1 t pll1 pll synchronization t irlstb note: pll oscillation setting time when clock is input from extal pin or ckio pin in continuous oscillation mode. pll synchronization standby figure 32.11 pll synchronization settlin g time by irq/irl and pint0/1 interrupt t pll2 extal input * 1 ckio output * 2 , pll output internal clock notes: 1. clock mode 7, ckio input. 2. clock mode 7, pll output. multiplier factor change figure 32.12 pll sync stabilization ti me at frequency multip lier factor change
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 946 of 1036 rej09b0254-0600 32.3.2 control signal timing table 32.9 control signal timing conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c min max figure resetp pulse width t respw 20 * 2 ? tcyc resetp setup time * 1 t resps 23 ? ns resetp hold time t resph 2 ? ns resetm pulse width t resmw 12 * 3 ? tcyc resetm setup time t resms 3 ? ns resetm hold time t resmh 34 ? ns 32.13 32.14 breq setup time t breqs 10 ? ns breq hold time t breqh 3 ? ns 32.15 nmi setup time * 1 t nmis 10 ? ns nmi hold time t nmih 4 ? ns irq5?irq0 setup time * 1 t irqs 10 ? ns irq5?irq0 hold time t irqh 4 ? ns 32.14 back delay time t backd ? 10 ns status1, status0 delay time t std ? 16 ns bus tri-state delay time 1 t boff1 0 15 ns bus tri-state delay time 2 t boff2 0 15 ns bus buffer-on time 1 t bon1 0 15 ns bus buffer-on time 2 t bon2 0 15 ns 32.15 32.16 notes: 1. resetp , nmi and irq5 to irq0 are asynchronous. changes are detected at the clock fall when the setup shown is used. when the setup cannot be used, detection can be delayed until the next clock falls. when using as irl, please observe the setup time. 2. in the standby mode, t respw = t osc2 (10 ms). in the sleep mode, t respw = t pll1 (100 s). when the clock multiplication ratio is changed, t respw = t pll1 (100 s). 3. in the standby mode, t resmw = t osc2 (10 ms). in the sleep mode, resetm must be kept low until status (0-1) changes to reset (hh). when the clock multiplication ratio is changed, resetm must be kept low until status (0-1) changes to reset (hh).
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 947 of 1036 rej09b0254-0600 ckio t resps/ms t resps/ms resetp resetm t respw/mw figure 32.13 reset input timing ckio resetp resetm t resph/mh t resps/ms v ih v il nmi t nmih t nmis v ih v il irq5 to irq0 t irqh t irqs v ih v il figure 32.14 interrupt signal input timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 948 of 1036 rej09b0254-0600 ckio breq back rd , rd/ wr , ras , cas , csn , wen , bs , a25 to a0, d31 to d0 t backd t boff2 t boff1 t bon1 t backd t bon2 t breqh t breqh t breqs t breqs mcsn figure 32.15 bus release timing ckio t std t boff2 t boff1 t std t bon2 t bon1 normal mode standby mode normal mode status 0 status 1 r d , rd/ wr , ras , cas , csn , wen , bs , mcsn a25 to a0, d31 to d0 figure 32.16 pin drive timing at standby
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 949 of 1036 rej09b0254-0600 32.3.3 ac bus timing table 32.10 bus timing conditions: clock modes 0/1/2/7, vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit conditions figure address delay time t ad 1.5 13 ns vcc = 1.70 to 2.05 v vccq = 3.0 to 3.6 v 32.17 to 32.30, 32.33 to 32.40 1.5 16 other than the above address setup time t as 0 ? ns 32.17 to 32.19 address hold time t ah * 1 7 ? ns 32.17 to 32.22 bs delay time t bsd ? 12 ns 32.17 to 32.30, 32.34 to 32.40 cs delay time 1 t csd1 1.5 12 ns 32.17 to 32.40 cs delay time 2 t csd2 1 12 ns 32.17 to 32.22 read/write delay time t rwd 1.5 10 ns 32.17 to 32.40 read/write hold time t rwh 0 ? ns 32.17 to 32.22 read strobe delay time t rsd ? 10 ns 32.17 to 32.22, 32.34 to 32.37 read data setup time 1 t rds1 6 ? ns 32.17 to 32.22, 32.34 to 32.40 read data setup time 2 t rds2 7 ? ns 32.23 to 32.26 read data hold time 1 t rdh1 * 2 0 ? ns 32.17 to 32.22, 32.34 to 32.40 read data hold time 2 t rdh2 2 ? ns 32.23 to 32.26 write enable delay time t wed 1 10 ns 32.17 to 32.19, 32.34, 32.35 write data delay time 1 t wdd1 ? 14 ns 32.17 to 32.19, 32.34, 32.35, 32.38 to 32.40 write data delay time 2 t wdd2 ? 13 ns 32.27 to 32.30
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 950 of 1036 rej09b0254-0600 item symbol min max unit conditions figure write data hold time 1 t wdh1 1.5 ? ns 32.17 to 32.19, 32.34, 32.35, 32.38 to 32.40 write data hold time 2 t wdh2 1.5 ? ns 32.27 to 32.30 write data hold time 3 t wdh3 2 ? ns 32.17 to 32.19 write data hold time 4 t wdh4 2 ? ns 32.34, 32.35, 32.38 to 32.40 wait setup time t wts 5 ? ns vcc = 1.70 to 2.05 v vccq = 3.0 to 3.6 v 6 ? other than the above 32.18 to 32.22, 32.35, 32.37, 32.39, 32.40 wait hold time t wth 0 ? ns 32.18 to 32.22, 32.35, 32.37, 32.39, 32.40 ras delay time 2 t rasd2 1.5 12 ns 32.23 to 32.33 cas delay time 2 t casd2 1.5 12 ns 32.23 to 32.33 dqm delay time t dqmd 1.5 10 ns 32.23 to 32.30 cke delay time t cked 1.5 12 ns 32.32 iciord delay time t icrsd ? 12 ns 32.38 to 32.40 iciowr delay time t icwsd ? 12 ns 32.38 to 32.40 iois16 setup time t io16s 12 ? ns 32.39, 32.40 iois16 hold time t io16h 4 ? ns 32.39, 32.40 dack delay time 1 t dakd1 ? 10 ns 32.17 to 32.30, 32.33 to 32.40 notes: 1. t ah : this is to deal with the latest negate timing of cs n, rd, or we n. 2. t rdh1 : this is to deal with the earliest negate timing of cs n or rd.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 951 of 1036 rej09b0254-0600 32.3.4 basic timing t 1 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs t 2 t ad t ah t ad t csd1 t rwd t rsd t csd2 t wed t wdd1 t rds1 t bsd t bsd t dakd1 t dakd1 t rdh1 t rdh1 t wed t rsd t ah t rwh t rwd t wdh1 t rwh t rwh t ah t wdh3 dackn (read) (write) t as figure 32.17 basic bus cycle (no wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 952 of 1036 rej09b0254-0600 t 1 t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) wen d31 to d0 (write) bs wait t ad t ad t rwd t rwh t ah t ah t rsd t csd1 t wed t wdd1 t bsd t wts t wth t bsd t rds1 t csd2 t wed t rsd t rdh1 t rdh1 t rwd t ah t rwh t wdh3 t wdh1 t rwh t dakd1 t dakd1 dackn (read) (write) t as figure 32.18 basic bus cycle (one wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 953 of 1036 rej09b0254-0600 t 1 t w t w t 2 ckio a25 to a0 csn rd/ wr rd d31 to d0 (read) notes: t rdh1 : specified based on the earliest negate timing of csn or rd . t ah : specified based on the latest negate timing of csn , rd , or wen . wen d31 to d0 (write) bs wait t ad t ad t rwd t rsd t wed t wts t wth t bsd t bsd t rds1 t wts t wth t csd1 t csd2 t rsd t wed t rdh1 t ah t rwh t rdh1 t ah t rwh t rwd t rwh t ah t wdh3 t wdh1 t dakd1 t dakd1 dackn t wdd1 (read) (write) t as figure 32.19 basic bus cycle (external wait, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 954 of 1036 rej09b0254-0600 32.3.5 burst rom timing ckio a25 to a4 a3 to a0 csn rd/ wr rd d31 to d0 bs dackn wait t ad t ad t ad t ad t csd1 t rwd t bsd t bsd t ah t bsd t dakd1 t dakd1 t csd2 t rsd t rds1 t wts t wth t rds t rsd t 1 t b2 t b1 t b2 t b1 t b2 t b1 t 2 t rsd t rdh1 t rsd t ah t rdh1 t rwh t ah t rwh t rwd t rdh1 t bsd note: in the write cycle, the basic bus cycle is performed. figure 32.20 burst rom bus cycle (no wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 955 of 1036 rej09b0254-0600 ckio a25 to a4 a3 to a0 csn rd/ wr rd d31 to d0 bs wait dackn t ad t ad t ad t csd1 t rwh t rwd t rsd t rsd t rdh1 t rdh1 t rds1 t bsd t dakd1 t dakd1 t bsd t bsd t wts t wth t wts t wth t 1 t w t w t b2 t b1 t b2 t w t 2 t 2 t csd2 t rds1 t rsd t rsd t ah t ah t rdh1 t ah t rsd t rwd t rwh t rdh1 note: in the write cycle, the basic bus cycle is performed. t bsd figure 32.21 burst rom bus cycle (two waits)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 956 of 1036 rej09b0254-0600 ckio a25 to a4 a3 to a0 csn rd/ wr rd d31 to d0 bs dackn wait t 1 t w t w t b2 t b1 t 2 t bw t ad t ad t csd1 t csd2 t rwd t rwh t rdh1 t ah t ah t rwd t rsd t rsd1 t ah t ad t bsd t wts t wth t wts t wth t wts t wth t wts t wth t bsd t rds1 t rdh1 t rsd t dakd1 t dakd1 t rdh1 t rwh t rsd1 t rds note: in the write cycle, the basic bus cycle is performed. t bsd t bsd figure 32.22 burst rom bus cycl e (external wait, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 957 of 1036 rej09b0254-0600 32.3.6 synchronous dram timing ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke a 25 to a16 a 15 to a0 tr t ad tc1 tc2 (tpc) d31 to d0 t ad t ad t ad t ad t csd1 t rwd t csd1 t rwd t rasd2 t dqmd t dqmd t rdh2 t bsd t bsd (high) t rds2 t rasd2 t casd2 t casd2 t ad t ad t ad dackn t dakd1 t dakd1 row address row address read a command row address column address figure 32.23 synchronous dram read bus cycle (rcd = 0, cas latency = 1, tpc = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 958 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a 25 to a16 a 15 to a0 tr trw trw tc1 tcw td1 (tpc) (tpc) d31 to d0 t ad t ad t ad t ad t csd1 t rwd t dqmd t rdh2 t bsd t bsd t rds2 t csd1 t rwd t rasd2 t dqmd t rasd2 t casd2 t casd2 t ad t ad t ad t ad dackn t dakd1 t dakd1 row address row address row address column address read a command figure 32.24 synchronous dram read bus cycle (rcd = 2, cas latency = 2, tpc = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 959 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a 25 to a16 a 15 to a0 tr tc1 tc2/td1 tc3/td2 tc4/td3 td4 (tpc) (tpc) d31 to d0 t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rasd2 t dqmd t bsd t bsd t rds2 t rdh2 t rds2 t rdh2 t dqmd t rasd2 t casd2 t casd2 t dakd1 t dakd1 dackn row address row address row address read command read a command column address (1-4) figure 32.25 synchronous dram read bus cycle (burst read (single read 4), rcd = 0, cas latency = 1, tpc = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 960 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke a 25 to a16 a 15 to a0 tr trw tc1 tc2 tc3 tc4/td1 td2 td3 td4 (tpc) d31 to d0 (read) t ad t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t rwd t dqmd t rds2 t bsd t bsd t rdh2 t rds2 t rdh2 t csd1 t rwd t rasd2 t rasd2 t casd2 t dqmd t casd2 read command (high) t dakd1 t dakd1 dackn row address row address row address column address (1-4) figure 32.26 synchronous dram read bus cycle (burst read (single read 4), rcd = 1, cas latency = 3, tpc = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 961 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke a 25 to a16 a 15 to a0 tr tc1 (trwl) (tpc) (high) d31 to d0 t ad t ad t ad t csd1 t rwd t rasd2 t ad t ad t ad t ad t ad t csd1 t rwd t rwd t rasd2 t casd2 t dqmd t wdd2 t bsd t dqmd t wdh2 t bsd t casd2 t dakd1 t dakd1 dackn row address row address row address write a command column address figure 32.27 synchronous dram write bus cycle (rcd = 0, tpc = 0, trwl = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 962 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke a 25 to a16 a 15 to a0 tr trw trw tc1 (trwl) (trwl) (tpc) (tpc) (high) d31 to d0 t ad t ad t ad t ad t ad t ad t ad t csd1 t rwd t rwd t ad t ad t ad t csd1 t rwd t rasd2 t rasd2 t dqmd t wdd2 t bsd t casd2 t dqmd t wdh2 t bsd t casd2 t dakd1 t dakd1 dackn row address row address row address column address write a command figure 32.28 synchronous dram write bus cycle (rcd = 2, tpc = 1, trwl = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 963 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke a 25 to a16 a 15 to a0 tr tc1 tc2 tc3 tc4 (trwl) (tpc) (tpc) (high) d31 to d0 t ad t ad t ad t ad t ad t csd1 t rwd t rwd t ad t ad t ad t ad t csd1 t rwd t rasd2 t rasd2 t dqmd t wdd2 t wdd2 t bsd t casd2 t dqmd t wdh2 t bsd t casd2 column address (1-4) t dakd1 t dakd1 dackn row address row address row address write command write a command figure 32.29 synchronous dram write bus cycle (burst mode (single write 4), rcd = 0, tpc = 1, trwl = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 964 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas bs dqmxx cke (high) a 25 to a16 a 15 to a0 tr trw tc1 tc2 tc3 td4 (trwl) (tpc) d31 to d0 write command t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t dqmd t bsd t bsd t wdd2 t wdd2 t wdh2 t dqmd t rasd2 t casd2 t casd2 t dakd1 t dakd1 dackn row address row address row address column address (1-4) write a command figure 32.30 synchronous dram write bus cycle (burst mode (single write 4), rcd = 1, tpc = 0, trwl = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 965 of 1036 rej09b0254-0600 ckio csn rd/ wr cas cke ras tp tpc trr trrw trrw (tpc) (tpc) trrw t csd1 t csd1 t rasd2 t rasd2 t rasd2 t rasd2 t casd2 t casd2 t rwd t rwd (high) figure 32.31 synchronous dram auto -refresh cycle (tras = 1, tpc = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 966 of 1036 rej09b0254-0600 tpc tra1 (trs2) (trs2) trs3 ckio cke csn ras cas rd/ wr t rwd t rwd t casd2 t rasd2 t casd2 t csd1 t rasd2 tp t csd1 t rasd2 t rasd2 (tpc) (tpc) t cked t cked t rwd figure 32.32 synchronous dram self-refresh cycle (tpc = 0)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 967 of 1036 rej09b0254-0600 ckio a 12 or a10 rd/ wr csn ras cas d31 to d0 a 13 or a11 a 11 to a2 or a9 to a2 trp1 trp2 trp3 trp4 tmw1 tmw2 tmw3 tmw4 (high) cke t ad t ad t ad t ad t ad t ad t ad t ad t ad t ad t ad t csd1 t csd1 t rwd t rwd t rwd t rasd2 t rasd2 t rasd2 t rasd2 t casd2 t casd2 t dakd1 t dakd1 dackn figure 32.33 synchronous d ram mode register write cycle
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 968 of 1036 rej09b0254-0600 32.3.7 pcmcia timing t pcm1 t pcm2 ckio a25 to a0 cexx rd/ wr rd d15 to d0 we1 d15 to d0 bs dackn t ad t ad t csd1 t csd1 t rwd t rsd t rsd t rwd t dakd1 t dakd1 t wed t wdd1 t wed t rds1 t rdh1 t bsd t bsd t wdh4 t wdh1 (read) (read) (write) (write) figure 32.34 pcmcia memory bus cycle (ted = 0, teh = 0, no wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 969 of 1036 rej09b0254-0600 t rds1 ckio t pcm0 t pcm0w t pcm1 t pcm1w t pcm1w t pcm2 t pcm2w a25 to a0 cexx rd/ wr rd (read) d15 to d0 (read) we1 (write) d15 to d0 (write) bs dackn wait t ad t csd1 t rwd t ad t csd1 t rwd t wdh4 t rsd t rsd t dakd1 t dakd1 t wed t wdd1 t wed t wdh1 t rdh1 t bsd t wts t wth t wts t bsd t wth figure 32.35 pcmcia memory bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 970 of 1036 rej09b0254-0600 ckio t pcm1 t pcm2 t pcm1 t pcm2 t pcm1 t pcm2 t pcm1 t pcm2 a25 to a4 a3 to a0 cexx rd/ wr rd d15 to d0 bs dackn t ad t ad t csd1 t rwd t csd1 t rwd t ad t ad t ad t ad t dakd1 t rsd t rsd t rdh1 t rdh1 t rsd t rsd t bsd t bsd t bsd t bsd t rds1 t rds1 note: even though burst mode is set, write cycle operation is the same as in normal mode. (read) (read) t dakd1 figure 32.36 pcmcia memory bus cycle (burst read, ted = 0, teh = 0, no wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 971 of 1036 rej09b0254-0600 t rds1 t rsd ckio t pcm0 t pcm1 t pcm1w t pcm1w t pcm1w t pcm2 t pcm1 t pcm1w t pcm2 t pcm2w a25 to a4 a3 to a0 cexx rd/ wr rd (read) d15 to d0 (read) bs dackn wait t ad t ad t csd1 t rwd t csd1 t dakd1 t rwd t ad t ad t ad t rsd t rsd t rsd t dakd1 t bsd t bsd t bsd t bsd t rdh1 t rdh1 t rds1 t wts t wth t wts t wts t wth t wth note: even though burst mode is set, the write cycle operation is the same as in normal mode. figure 32.37 pcmcia memory bus cycle (burst read, ted = 1, teh = 1, two wa its, burst pitch = 3, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 972 of 1036 rej09b0254-0600 t pci1 t pci2 ckio a25 to a0 cexx rd/ wr iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs dackn t ad t ad t csd1 t csd1 t rwd t icrsd t icrsd t rwd t dakd1 t dakd1 t icwsd t wdd1 t icwsd t rdh1 t rds1 t bsd t bsd t wdh1 t wdh4 figure 32.38 pcmcia i/o bus cycle (ted = 0, teh = 0, no wait)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 973 of 1036 rej09b0254-0600 t rds1 ckio t pci0 t pci0w t pci1 t pci1w t pci1w t pci2 t pci2w a25 to a0 cexx rd/ wr iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs dackn wait iois16 t ad t csd1 t rwd t ad t csd1 t rwd t icrsd t icrsd t dakd1 t dakd1 t icwsd t wdd1 t icwsd t wdh1 t wdh4 t rdh1 t bsd t bsd t wts t wth t wts t wth t io16s t io16h figure 32.39 pcmcia i/o bus cycle (ted = 2, teh = 1, one wait, external wait, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 974 of 1036 rej09b0254-0600 t rdh1 t icwsd t rds1 ckio t pci0 t pci1 t pci1w t pci2 t pci1 t pci1w t pci2 t pci2w a25 to a4 a0 cexx rd/ wr iciord (read) d15 to d0 (read) iciowr (write) d15 to d0 (write) bs wait dackn iois16 t ad t ad t csd1 t csd1 t rwd t rwd t wdd1 t wdh3 t wdh4 t bsd t bsd t ad t ad t icrsd t icrsd t icrsd t icrsd t wts t wth t wth t io16s t io16h t ad t rds1 t csd1 t dakd1 t dakd1 t icwsd t icwsd t icwsd t rdh1 t wdd2 t wdh1 t bsd t bsd t wts figure 32.40 pcmcia i/o bus cycle (ted = 1, teh = 1, one wait , bus sizing, waitsel = 1)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 975 of 1036 rej09b0254-0600 32.3.8 peripheral mo dule signal timing table 32.11 peripheral module signal timing conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c module item symbol min max unit figure rtc oscillation settling time t rosc ? 3 s 32.41 asynchronization t scyc 4 ? 32.42 input clock cycle clock synchronization 6 ? p cyc * 32.43 input clock rise time t sckr ? 1.5 input clock fall time t sckf ? 1.5 p cyc * input clock pulse width t sckw 0.4 0.6 t scyc 32.42 transmission data delay time t txd ? 100 receive data setup time (clock synchronization) t rxs 100 ? receive data hold time (clock synchronization) t rxh 100 ? rts delay time t rtsd ? 100 cts setup time (clock synchronization) t ctss 100 ? sci cts hold time (clock synchronization) t ctsh 100 ? ns 32.43 output data delay time t portd ? 26 input data setup time (1) t ports1 15 ? input data hold time (1) t porth1 8 ? input data setup time (2) t ports2 t cyc + 15 ? input data hold time (2) t porth2 8 ? input data setup time (3) t ports3 3 t cyc + 15 ? port input data hold time (3) t porth3 8 ? ns 32.44 dreq setup time t drqs 8 ? dreq hold time t dreqh 8 ? 32.45 dmac drak delay time t drakd ? 14 ns 32.46 note: * p cyc stands for ?peripheral clock (p ) cycle.?
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 976 of 1036 rej09b0254-0600 rtc crystal oscillator stable oscillation v cc v ccmin t rosc figure 32.41 oscillation settling time at rtc crystal oscillator power-on t sckw t sckr t sckf t scyc sck figure 32.42 sck input clock timing t scyc t txd sck txd (data trans- missiion) rxd (data reception) t rxh t rxs t rtsd rts cts t ctsh t ctss figure 32.43 sci i/o timing in clock synchronous mode
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 977 of 1036 rej09b0254-0600 t ports1 ckio port a to h, j to m, sc (read) (bus clock:peripheral clock ratio = 1:1) port a to h, j to m, sc (write) t porth1 t ports3 port a to h, j to m, sc (read) (bus clock:peripheral clock ratio = 1:1/4) t porth3 t ports2 port a to h, j to m, sc (read) (bus clock:peripheral clock ratio = 1:1/2) t porth2 t portd figure 32.44 i/o port timing d req ckio t drqs t drqh figure 32.45 dreq input timing drak ckio t drakd t drakd figure 32.46 drak output timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 978 of 1036 rej09b0254-0600 32.3.9 h-udi-related pin timing table 32.12 h-udi-related pin timing conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure tck cycle time t tckcyc 50 ? ns tck high pulse width t tckh 12 ? ns tck low pulse width t tckl 12 ? ns tck rise/fall time t tckf ? 4 ns figure 32.47 trst setup time t trsts 12 ? ns trst hold time t trsth 50 ? t cyc figure 32.48 tdi setup time t tdis 10 ? ns tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ? 19 ns figure 32.49 asemd0 setup time t asemdh 12 ? ns figure 32.50 asemd0 hold time t asemds 12 ? ns t tckl t tckf v il v il v ih v ih v ih 1/2 v cc q 1/2 v cc q t tckf t tckh t tckcyc tck (input) figure 32.47 tck input timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 979 of 1036 rej09b0254-0600 resetp t trsts t trsth trst figure 32.48 trst input timing (reset hold) tck tdi tms t tdis t tmss t tdih t tckcyc t tmsh t tdod tdo figure 32.49 h-udi data transfer timing t asemdos t asemdoh resetp asemd0 figure 32.50 asemd0 input timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 980 of 1036 rej09b0254-0600 32.3.10 lcdc timing table 32.13 lcdc timing conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure lclk input clock frequency t freq ? 50 mhz 32.51 lclk input clock rise time t r ? 3 ns lclk input clock fall time t f ? 3 ns lclk input clock duty t duty 90 110 % clock (cl2/dclk) cycle time t cc 25 ? ns clock (cl2/dclk) high-level width t chw 7 ? ns clock (cl2/dclk) low-level width t clw 7 ? ns clock (cl2/dclk) transition time (rise, fall) t ct ? 3 ns data (lcd) delay time t dd ?3.5 3 ns data (lcd) transition time (rise, fall) t dt ? 3 ns display enable (m/disp) delay time t id ?3.5 3 ns display enable (m/disp) transition time (rise, fall) t it ? 3 ns horizontal sync. signal (cl1/hsync) delay time t hd ?3.5 3 ns horizontal sync. singal (cl1/hsync) transition time t ht ? 3 ns vertical sync. signal (flm/vsync) delay time t vd ?3.5 3 ns vertical sync. signal (flm/vsync) transition time t vt ? 3 ns
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 981 of 1036 rej09b0254-0600 t cc 0.2vcc 0.8vcc t vt t vd t vt 0.2vcc 0.8vcc 0.8vcc t it t it 0.2vcc 0.8vcc t dt t dt 0.2vcc 0.8vcc t ht t hd cl2/dclk lcdd m/disp cl1/hsync flm/vsync cl2/dclk t id t chw t clw t ht t ct t cc t ct t dd 0.2vcc figure 32.51 lcdc ac specification
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 982 of 1036 rej09b0254-0600 32.3.11 siof module signal timing table 32.14 siof module signal timing conditions: v cc q = 2.6 to 3.6 v, v cc = 1.60 to 2.05 v, av cc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit figure siomclk clock input cycle time t mcyc 30 ? ns 32.52 siomclk input high-level width t mwh 0.4 t mcyc ? ns 32.52 siomclk input low-level width t mwl 0.4 t mcyc ? ns 32.52 sck_sio clock cycle time t sicyc 2 t pcyc ? ns 32.53 to 32.57 sck_sio output high-level width t swho 0.4 t sicyc ? ns 32.53 to 32.56 sck_sio output low-level width t swlo 0.4 t sicyc ? ns 32.53 to 32.56 siofsync output delay time t fsd ? 20 ns 32.53 to 32.56 sck_sio input high-level width t swhi 0.4 t sicyc ? ns 32.57 sck_sio input low-level width t swli 0.4 t sicyc ? ns 32.57 siofsync input setup time t fss 20 ? ns 32.57 siofsync input hold time t fsh 20 ? ns 32.57 txd_sio output delay time t stdd ? 20 ns 32.53 to 32.57 rxd_sio input setup time t srds 20 ? ns 32.53 to 32.57 rxd_sio input hold time t srdh 20 ? ns 32.53 to 32.57 note: t pcyc is the cycle time (ns) of the peripheral clock (p ) t mwh siomclk t mwl t mcyc figure 32.52 siomclk input timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 983 of 1036 rej09b0254-0600 t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd figure 32.53 siof transmit/receive timi ng (master mode 1: fall sampling time) t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swho t swlo t fsd t stdd t stdd figure 32.54 siof transmit/receive timi ng (master mode 1: rise sampling time)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 984 of 1036 rej09b0254-0600 t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd t stdd t stdd figure 32.55 siof transmit/receive timi ng (master mode 2: fall sampling time) t srds t srdh sck_sio (output) siofsync (output) txd_sio rxd_sio t fsd t sicyc t swlo t swho t fsd t stdd t stdd t stdd t stdd figure 32.56 siof transmit/receive timi ng (master mode 2: rise sampling time)
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 985 of 1036 rej09b0254-0600 t srds t srdh sck_sio (input) siofsync (input) txd_sio rxd_sio t fss t sicyc t swli t swhi t fsh t stdd t stdd figure 32.57 siof transmit/receive timi ng (slave mode 1 and slave mode 2) 32.3.12 usb module signal timing table 32.15 usb module signal timing conditions: v cc q = 2.6 to 3.6 v, v cc = 1.60 to 2.05 v, av cc = 3.3 0.3 v, t a = ?20 to 75c item symbol min max unit figure uclk external input clock frequency (48 mhz) (when using usb function controller) t freq 47.9 48.1 mhz 32.58 uclk external input clock frequency (48 mhz) (when using usb host controller) 47.976 48.024 clock rise time t r48 ? 6 ns clock fall time t f48 ? 6 ns t high t low t freq 10% t r48 t f48 90% uclk (input) figure 32.58 usb clock timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 986 of 1036 rej09b0254-0600 table 32.16 usb electrical ch aracteristics (full-speed) item symbol min max unit state * 1 transition time (rise) * 2 t r 4 20 ns cl = 50 pf transition time (fall) * 2 t f 4 20 ns cl = 50 pf rise/fall time matching t rfm 90 111 % (tr/tf) output signal crossover power supply voltage v crs 1.3 2.0 v ? notes: measured with edge control c edge = 47 pf and connection of direct resister rs = 27 . 1. value when cl = 50 pf unless specified otherwise. 2. value within 10% to 90% of the signal power supply voltage. table 32.17 usb electrical ch aracteristics (low-speed) item symbol min max unit state 75 ? ns cl = 200 pf transition time (rise) * t r ? 300 ns cl = 600 pf 75 ? ns cl = 200 pf transition time (fall) * t f ? 300 ns cl = 600 pf rise/fall time matching t rfm 80 125 % (tr/tf) output signal crossover power supply voltage v crs 1.3 2.2 v ? notes: measured with edge control c edge = 47 pf and connection of direct resister rs = 27 . * value within 10% to 90% of the signal power supply voltage.
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 987 of 1036 rej09b0254-0600 32.3.13 afeif module signal timing table 32.18 afeif module signal timing conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item symbol min max unit afe_sclk clock input cycle time t ascyc 8 t pcyc ? ns afe_sclk input high-level width t aswh 0.4 t ascyc ? ns afe_sclk input low-level width t aswl 0.4 t ascyc ? ns afe_fs input time t afsd 0 50 ns afe_txout output delay time t atdd ? t pcyc + 20 ns afe_rxin input setup time t ards 20 ? ns afe_rxin input hold time t ardh 2 t pcyc + 20 ? ns afe_hc1 output delay time t ahcd ? 3 t pcyc + 20 ns afe_rlyc output delay time t arlyd ? t pcyc + 20 ns note: t pcyc is the cycle time (ns) of the peripheral clock (p ).
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 988 of 1036 rej09b0254-0600 t ards t ardh a fe_sclk a fe_fs a fe_txout a fe_rxin a fe_hc1 a fe_rlyc t afsd t ascyc t aswl t aswh t ahcd t ahcd t arlyd t afsd t atdd figure 32.59 afeif module ac timing
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 989 of 1036 rej09b0254-0600 32.3.14 ac characteristics measurement conditions ? i/o signal reference level: 1.2 vccq ? input pulse level: vssq to 3.0 v (where resetp , resetm , asemd0 , irl3 to irl0 , adtrg , pint[15] to pint[0], ca, nmi, irq5 to irq0, ckio, and md5 to md0 are within vssq to vccq) ? input rise and fall times: 1 ns i ol i oh c l v ref lsi output pin dut output notes: c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pf: ckio, ras , cas , cs0 , cs2 to cs6 , ce2a , ce2b , back 50pf: all other pins i ol and i oh are the values shown in table 32.3. 1. 2. figure 32.60 output load circuit
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 990 of 1036 rej09b0254-0600 32.3.15 delay time variation due to load capacitance a graph (reference data) of the variation in delay time when a load capacita nce greater than that stipulated (30 pf or 50 pf) is connected to this lsi?s pins is shown below. the graph shown in figure 32.61 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. if the connected load capacitance exceeds the range shown in figure 32.61, the graph will not be a straight line. +3 +2 +1 +0 +0 +10 +20 +30 +40 +50 load capacitance [pf] delay time [ns] figure 32.61 load ca pacitance vs. delay time
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 991 of 1036 rej09b0254-0600 32.4 a/d converter characteristics table 32.19 lists the a/d converter characteristics. table 32.19 a/d converter characteristics conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item min typ max unit resolution 10 10 10 bits conversion time 15 ? ? s analog input capacitance ? ? 20 pf permissible signal-source (single- source) impedance ? ? 5 k nonlinearity error ? ? 3.0 lsb offset error ? ? 2.0 lsb full-scale error ? ? 2.0 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb 32.5 d/a converter characteristics table 32.20 lists the d/a converter characteristics. table 32.20 d/a converter characteristics conditions: vccq = 2.6 to 3.6 v, vcc = 1.60 to 2.05 v, avcc = 3.3 0.3 v, ta = ?20 to 75c item min typ max unit test conditions resolution 8 8 8 bits conversion time ? ? 10.0 s 20 pf capacitive load absolute accuracy ? 2.5 4.0 lsb 2 m resistance load
section 32 electrical characteristics rev.6.00 mar. 27, 2009 page 992 of 1036 rej09b0254-0600
appendix a pin functions rev.6.00 mar. 27 2009 page 993 of 1036 rej09b0254-0600 appendix a pin functions a.1 pin functions table a.1 pin functions type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges xtal2 2 o o o o o extal2 3 i i i i i xtal 179 o o o o o extal 180 i i i i i cap1, cap2 171, 174 ? ? ? ? ? ckio2 19 o(z) o o(z) o(z) o(z) clock and oscillation related ckio 189 io io io io io status0 /ptj[6], status1 /ptj[7] 185, 186 o/io o o/p o/k o/p resetp , resetm 220, 147 i i i i i ca 221 i i i i i scan_testen 224 i i i i i md0 to md5 169, 5, 6, 222, 223, 15 i i i i i system control asemd0 150 i i i i i nmi 7 i i i i i irq0 / irl0 /pth[0] to irq3 / irl3 /pth[3] 8, 9, 10, 11 i/i/i v i/i/i i/i/z i/i/i interrupts irq4 /pth[4] 12 i/i v i/i i/z i/i breq 16 i i i i i back 17 o h h h l d31 /ptb[7] to d24 /ptb[0], d23 /pta[7] to d16 /pta[0] 21 to 28, 30, 32 to 34, 36, 38 to 40 io/io z k/p z/k z/p bus functions d15 to d0 41, 43, 45 to 52, 54, 56 to 60 io z k z z
appendix a pin functions rev.6.00 mar. 27, 2009 page 994 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges a0 to a25 61 to 63, 65, 67 to 74, 76, 78 to 85, 87, 89, 90, 92, 94 o z o z(l) z bs /ptk[4] 95 o/io h o/p z(h)/k z/p rd 96 o h o z(h) z we0 /dqmll 97 o/o h o/o z(h)/z(h) z/z we1 /dqmlu/ we 98 o/o/o h o/o/o z(h)/z(h)/ z(h) z/z/z we2 /dqmul/ iciord / ptk[6], we3 /dqmuu/ iciowr / ptk[7] 99, 101 o/o/o/ io h o/o/o/p z(h)/z(h)/ o/k z/z/z/p rdwr 103 o h o z(h) z cs0 , cs2 , cs3 105, 106, 107 o h o z(h) z cs4 /ptk[2] 108 o/io h o/p z(h)/k z/p cs5 / ce1a /ptk[3] 109 o/o/io h o/o/p z(h)/z(h)/ k z/z/p cs6 / ce1b 110 o/o h o/o z(h)/z(h) z/z ce2a / pte[4], ce2b / pte[5] 111, 112 o/io v o/p z(h)/k z/p cke /ptk[5] 128 o/io h o/p o/k o/p reserved / cas /ptj[2] 131 o/o/io h o/o/p o/z(h)/k o/z(h)/p wait 146 i z z z z iois16 / ptg[7] 149 i/i v i/i z/z(v) i/i bus functions ras /ptj[0], reserved /ptj[1], reserved /ptj[3] * 3 , reserved /ptj[4] * 3 , reserved /ptj[5] * 3 129, 130, 133, 135, 136 o/io h o/p z(h)/k z(h)/p afe_hc1 / usb1d_dpls/ptk[0] 113 o/i/io l o/i/p z/z/k o/i/p afe_rlycnt / usb1d_dmns/ptk[1] 114 o/i/io l o/i/p o/z/k o/i/p afe/usb digital/port related afe_sclk / usb1d_txdpls 116 i/o i i/o z/o i/o
appendix a pin functions rev.6.00 mar. 27 2009 page 995 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges afe/usb digital/port related ptm[7]/pint[7] / afe_fs/usb1d_rcv, ptm[6]/pint[6] / afe_rxin/usb1d_speed, ptm[5]/pint[5] / afe_txout/ usb1d_txse0 118, 119, 120 i/i/i/o v i/i/i/o z(v)/i/z/o i/i/i/o ptm[4]/pint[4] / afe_rdet 121 i/i/i v i/i/i z(v)/i/z i/i/i usb1d_suspend 122 o o o o o jtag pte[0]/tdo * 1 143 io/o v/o * 1 p/o k/o p/o ptf[7]/pint[15]/ trst * 1 , ptf[6]/pint[14]/tms * 1 , ptf[5]/pint[13]/tdi * 1 , ptf[4]/pint[12]/tck * 1 160, 162, 163, 164 i/i/i v/i * 1 i/i/i z/i/i i/i/i dmac dreq0 / ptd[4] 218 i/i v z/i z/z(v) i/i drak0 /pcc0reset 144 o/o h o/o z(h)/z o/o dack0 /pcc0drv 145 o/o h o/o z/z o/o port/pcc/ aud related pte[7] /pcc0rdy/ audsync * 1 104 io/i/o v/o * 1 p/i/o k/z/o p/i/o pcc0wait / pth[6]/audck * 1 176 i/i/i v/v * 1 i/i/i z/z(v)/z i/i/i pcc0bvd2/ ptg[3]/audata[3] * 1 , pccbvd1/ ptg[2]/audata[2] * 1 , pcc0cd2 / ptg[1]/audata[1] * 1 , pcc0cd1 / ptg[0]/audata[0] * 1 153, 154, 156, 158 i/i/o v/o * 1 i/i/o z/z(v)/o i/i/o ptg[4] 152 i v i z(v) i ptf[3]/pint[11] 165 i/i v i/i z(v)/i i/i pccreg/ ptf[2] 166 o/i v o/i z/z(v) o/i ptg[5]/ asebrkak * 1 151 i/o v/o * 1 i/o z(v)/o i/o pcc0vs1 / ptf[1] , pcc0vs2 / ptf[0] 167, 168 i/i v i/i z/z(v) i/i
appendix a pin functions rev.6.00 mar. 27, 2009 page 996 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges lcdc related ptd[5] /cl1, ptd[7] /don, pte[6] /m_disp, pte[3] /flm, pth[7]/ cl2 138, 140, 141, 142, 187 io/o v p/l k/l * 2 p/o vepwc, vcpwc 13, 14 o l l l * 2 o lcd15/ ptm[3]/pint[10] to lcd13/ ptm[1]/pint[8] 181, 182, 183 o/i/i v l/i/i k * 2 /z(v)/i o/i/i lcd12/ ptm[0] 184 o/i v l/i k * 2 /z(v) o/i lcd11/ ptc[7]/pint[3] to lcd8/ ptc[4]/pint[0] 204, 205, 206, 208 o/io/i v l/p/i k * 2 /k/i o/p/i lcd7/ ptd[3] to lcd0/ ptd[0] 210 to 217 o/io v l/p k * 2 /k o/p lclk/uclk/ ptd[6] 219 i/i/i v i/i/i z/z/z(v) i/i/i siomclk /scpt[3] 194 i/io i z/p z/k i/p serial related sck_sio /scpt[5] 196 io/io i z/p z/k io/p siofsync /scpt[6] 197 io/io i z/p k/k io/p rxd0 /scpt[0], rxd2 /scpt[4] 198, 201 i/i z z/i z/z i/z rxd_sio /scpt[2] 199 i/i i z/i z/z i/z scpt[7] / cts2 / irq5 203 i/i/i v i/z/i z(v)/z/i i/i/i txd0 /scpt[0], txd2 /scpt[4] 191, 195 o/o z z/o z/k o/z sck0 /scpt[1] 192 io/io v z/p v/k io/p txd_sio /scpt[2] 193 o/o h z/o z/k o/o rts2 /usb1d_txenl 125 o/o l o/o z/o o/o usb related pte[2] /usb1_pwr_en, pte[1] /usb2_pwr_en 126, 127 io/o v p/o k/o p/o usb1_ovr_current / usbf_vbus 123 i/i i z/z z/z i/i usb2_ovr_current 124 i i z z i usb1_p(analog), usb1_m(analog), usb2_p(analog), usb2_m(analog) 226, 227, 229, 230 io l l k io
appendix a pin functions rev.6.00 mar. 27 2009 page 997 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no. (hqfp) i/o power- on reset manual reset standby release/ open bus privileges adtrg /pth[5] 148 i/i v i/i i/z i/i adc an[2]/ptl[2], an[3]/ptl[3], an[4]/ptl[4], an[5]/ptl[5] 233, 234, 235, 236 i/i z z/i z/z i/i adc/dac an[6] /ptl[6]/da[1], an[7] /ptl[7]/da[0] 238, 239 i/i/o z z/i/z z/z/o i/i/o avcc_usb 225, 231 ? ? ? ? ? avss_usb 228 ? ? ? ? ? avss 232, 240 ? ? ? ? ? avcc 237 ? ? ? ? ? vcc-pll1, vcc-pll2 170, 175 ? ? ? ? ? vss-pll1, vss-pll2 172, 173 ? ? ? ? ? vcc-rtc 1 ? ? ? ? ? vss-rtc 4 ? ? ? ? ? power supply vcc 37, 93, 139, 157, 178, 202 ? ? ? ? ? vss 35, 91, 137, 155, 177, 200 ? ? ? ? ? vccq 20, 31, 44, 55, 66, 77, 88, 102, 117, 134, 161, 190, 209 ? ? ? ? ? vssq 18, 29, 42, 53, 64, 75, 86, 100, 115, 132, 159, 188, 207 ? ? ? ? ? notes: 1. the initial status is determined from the level of asemd0 when resetting. 2. in accordance with the power mana gement sequence described in section 25.3.6, power management registers of this manual, ma ke sure to clear the don register to 0 and interrupt the power supply bef ore entering the standby mode. 3. the initial status of ptj3 to ptj5 is high level output, but it may change briefly to low level when resetting.
appendix a pin functions rev.6.00 mar. 27, 2009 page 998 of 1036 rej09b0254-0600 i: input (input buffer on) o: output (output buffer on) h: high-level output l: low-level output z: high-impedance (input and output buffers off) p: i or o according to setting of register k: input pins are high-impedance, output pin status is retained v: input/output buffer off, pull-up mos on ( ): based on status of internal registers (refer to the register tables for information on individual pins.)
appendix a pin functions rev.6.00 mar. 27 2009 page 999 of 1036 rej09b0254-0600 a.2 treatment of unused pins table a.2 treatment of unused pins type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used xtal2 2 b4 o open extal2 3 a2 i pull up (vcc- rtc) xtal 179 v4 o open extal 180 v2 i pull up cap1, cap2 171, 174 u3, w4 ? open ckio2 19 c7 o open clock and oscillation related ckio 189 r1 io open status0 /ptj[6], status1 /ptj[7] 185, 186 u1, r2 o/io open resetp , resetm 220, 147 h1, t11 i pull up ca 221 g4 i pull up scan_testen 224 g1 i pull up md0 to md5 169, 5, 6, 222, 223, 15 t5, a3, b5, g3, g2, c6 i always used system control asemd0 150 t10 i pull up nmi 7 a4 i pull up irq0 / irl0 /pth[0] to irq3 / irl3 /pth[3] 8, 9, 10, 11 c4, a5, d4, c5 i/i/i pull up interrupts irq4 /pth[4] 12 d5 i/i pull up breq 16 d6 i pull up back 17 a7 o open bus functions d31 /ptb[7] to d24 /ptb[0], d23 /pta[7] to d16 /pta[0] 21 to 28, 30, 32 to 34, 36, 38 to 40 a8, b8, c8, d8, a9, b9, d9, c9, d10, b10, c11, d11, a11, c12, b12, a12 io/io open d15 to d0 41, 43, 45 to 52, 54, 56 to 60 d13, d11, d14, c14, b14, a14, d15, c15, c17, a15, a16, a17, b17, a18, b16, b18 io open
appendix a pin functions rev.6.00 mar. 27, 2009 page 1000 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used bus functions a0 to a25 61 to 63, 65, 67 to 74, 76, 78 to 85, 87, 89, 90, 92, 94 a19, d18, b19, c19, d19, d17, e19, d16, e17, e16, f19, f18, f16, g18, g17, g16, h19, h18, h17, h16, j19, j16, k19, k16, k18,l16 o open bs /ptk[4] 95 l18 o/io open rd/ wr 96 l19 o open we0 /dqmll 97 m16 o/o open we1 /dqmlu/ we 98 m17 o/o/o open we2 /dqmul/ iciord /ptk[6], we3 /dqmuu/ iciowr /ptk[7] 99, 101 m18 o/o/o/i o open rd/ wr 103 n18 o open cs0 , cs2 , cs3 105, 106, 107 p16, p17, p18 o open cs4 /ptk[2] 108 p19 o/io open cs5 / ce1a /ptk[3] 109 r16 o/o/io open cs6 / ce1b 110 r17 o/o open ce2a /pte[4], ce2b /pte[5] 111, 112 u17, r19 o/io open cke /ptk[5] 128 u16 o/io open reserved / cas /ptj[2] 131 u15 o/o/io open wait 146 v11 i pull up iois16 /ptg[7] 149 w10 i/i open ras /ptj[0], reserved /ptj[1], reserved /ptj[3], reserved /ptj[4], reserved /ptj[5] 129, 130, 133, 135, 136 w15, t16, w14, u14, t14 o/io open
appendix a pin functions rev.6.00 mar. 27 2009 page 1001 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used afe_hc1 /usb1d_dpls/ ptk[0], afe_rlycnt /usb1d_dmns/ ptk[1] 113, 114 t17, t19 o/i/io open afe_sclk /usb1d_txdpls 116 u19 i/io pull up ptm[7]/pint[7] /afe_fs/ usb1d_rcv, ptm[6]/pint[6] /afe_rxin/ usb1d_speed, ptm[5]/pint[5] /afe_txout/ usb1d_txse0 118, 119, 120 v19, t18, v18 i/i/i/o open ptm[4]/pint[4] / afe_rdet 121 w19 i/i/i open afe/usb digital/port related reserved/usb1d_suspend 122 v16 o open pte[0]/tdo * 1 143 u12 io/o open jtag ptf[7]/pint[15]/ trst * 1 , ptf[6]/pint[14]/tms * 1 , ptf[5]/pint[13]/tdi * 1 , ptf[4]/pint[12]/tck * 1 160, 162, 163, 164 w8, u7, v7, w7 i/i/i pull up dreq0 /ptd[4] 218 h3 i/i pull up dmac drak0 /pcc0reset, dack0 /pcc0drv 144, 145 t12, w11 o/o open port/pcc/ aud related pte[7] /pcc0rdy/ audsync 104 n19 io/i/o open pcc0wait / pth[6]/audck * 1 176 w3 i/i/i pull up pcc0bvd2/ ptg[3]/ audata[3] * 1 , pccbvd1/ ptg[2]/ audata[2] * 1 , pcc0cd2 / ptg[1]/ audata[1] * 1 , pcc0cd1 / ptg[0]/ audata[0] * 1 153, 154, 156, 158 u9, t9, w9, u8 i/i/o open ptg[4] 152 v10 i open ptf[3]/pint[11] 165 t6 i/i open pccreg/ ptf[2] 166 u6 o/i open ptg[5]/ asebrkak * 1 151 u10 i/o open pcc0vs1 / ptf[1] , pcc0vs2 / ptf[0] 167, 168 v6, w6 i/i open
appendix a pin functions rev.6.00 mar. 27, 2009 page 1002 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used ptd[5] /cl1, ptd[7] /don, pte[6] /m_disp, pte[3] /flm, cl2 /pth[7] 138, 140, 141, 142, 187 v13, t13, w12, v12, t1 io/o open vepwc, vcpwc 13, 14 a6, b6 o open lcd15/ ptm[3]/pint[10] to lcd13/ ptm[1]/pint[8] 181, 182, 183 w1, t2, v1 o/i/i open lcd12/ ptm[0] 184 u2 o/i open lcd11/ ptc[7]/pint[3] to lcd8/ ptc[4]/pint[0] 204, 205, 206, 208 m4, l1, l2, l3 o/io/i open lcd7/ ptd[3] to lcd0/ ptd[0] 210 to 217 k4, k3, k2, j3, j4, j2, j1, h4 o/io open lcdc related lclk/uclk/ ptd[6] 219 h2 i/i/i pull up siomclk /scpt[3] 194 p2 i/io pull up sck_sio /scpt[5], siofsync /scpt[6] 196, 197 p4, n1 io/io pull up rxd0 /scpt[0], rxd2 /scpt[4], rxd_sio /scpt[2] 198, 201, 199 n2, m1, n3 i/i pull up scpt[7] / cts2 / irq5 203 m3 i/i/i pull up txd0 /scpt[0], txd2 /scpt[4] 191, 195, 193 r3, p3, p1 o/o open sck0 /scpt[1] 192 r4 io/io open txd_sio /scpt[2] 193 p1 o/o open serial related rts2 /usb1d_txenl 125 w17 o/o open pte[2] /usb1_pwr_en, pte[1] /usb2_pwr_en 126, 127 v15, w16 io/o open usb1_ovr_current / usbf_vbus 123 w18 i/i pull up usb2_ovr_current 124 v17 i pull up usb related usb1_p(analog), usb1_m(analog), usb2_p(analog), usb2_m(analog) 226, 227, 229, 230 f3, f2, e4, e3 io open * 2 or pull down adtrg /pth[5] 148 u11 i/i pull up adc an[2]/ptl[2], an[3]/ptl[3], an[4]/ptl[4], an[5]/ptl[5] 233, 234, 235, 236 d3, d1, e2, c1 i/i open adc/dac an[6] /ptl[6]/da[1], an[7] /ptl[7]/da[0] 238, 239 b1, d2 i/i/o open * 3
appendix a pin functions rev.6.00 mar. 27 2009 page 1003 of 1036 rej09b0254-0600 type signal name (initial status: bold) pin no (hqfp) pin no (csp) i/o treatment when not used avcc_usb 225, 231 f4, c3 ? vccq avss_usb 228 f1 ? vssq avss 232, 240 e1, b2 ? vssq power supply avcc 237 c2 ? vccq vcc-pll1, vcc-pll2 170, 175 u5, v5 ? vcc vss-pll1, vss-pll2 172, 173 w5, u4 ? vcc vcc-rtc 1 a1 ? vcc vss-rtc 4 b3 ? vcc vcc 37, 93, 139, 157, 178, 202 d2, l17, u13, t8, w2, m2 ? vcc vss 35, 91, 137, 155, 177, 200 b11, k17, w13, v9, v3, n4 ? vss vccq 20, 31, 44, 55, 66, 77, 88, 102, 117, 134, 161, 190, 209 d7, c10, a13, b15, e18, g19, j17, n17, u18, v14, t7, t4, k1 ? vccq vssq 18, 29, 42, 53, 64, 75, 86, 100, 115, 132, 159, 188, 207 b7, a10, c13, c16, c18, f17, j18, m19, r18, t15, v8, t3, l4 ? vssq notes: for unused pins, the above table shows examples of processing. the indicated settings may not be suitable in some cases. 1. valid when asemd0 is low level. 2. in cases where either usb function is used, this should be fixed as per the not used and not active examples. 3. a/d pin functions are assumed.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1004 of 1036 rej09b0254-0600 a.3 pin status when accessing address spaces table a.3 pin status (normal memory/little endian) 8-bit bus width 16-bit bus width pin byte/word/ longword access byte access (address 2n) byte access (address 2n+1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w high high high high r high high high high rd/ wr w low low low low bs enabled enabled enabled enabled ras high high high high cas high high high high r high high high high we0 /dqmll w low low high low r high high high high we1 /dqmlu/ we w high high low low r high high high high we2 /dqmul/ iciord w high high high high r high high high high we3 /dqmuu/ iciowr w high high high high ce2a high high high high ce2b high high high high cke disabled disabl ed disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabl ed disabled disabled a25 to a0 address a ddress address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1005 of 1036 rej09b0254-0600 table a.3 pin status (normal memory/little endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r low low low low low low low rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled e nabled enabled enabled enabled ras high high high high high high high cas high high high high high high high r high high high high high high high we0 /dqmll w low high high high low high low r high high high high high high high we1 /dqmlu/ we w high low high high low high low r high high high high high high high we2 /dqmul/ iciord w high high low high high low low r high high high high high high high we3 /dqmuu/ iciowr w high high high low high low low ce2a high high high high high high high ce2b high high high high high high high cke disabled disabled disabled disabled dis abled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address address addre ss address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switched to port function, pull-up.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1006 of 1036 rej09b0254-0600 table a.4 pin status (normal memory/big endian) 8-bit bus width 16-bit bus width pin byte/word/ longword access byte access (address 2n) byte access (address 2n+1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w high high high high r high high high high rd/ wr w low low low low bs enabled enabled enabled enabled ras high high high high cas high high high high r high high high high we0 /dqmll w low high low low r high high high high we1 /dqmlu/ we w high low high low r high high high high we2 /dqmul/ iciord w high high high high r high high high high we3 /dqmuu/ iciowr w high high high high ce2a high high high high ce2b high high high high cke disabled disabl ed disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabl ed disabled disabled a25 to a0 address a ddress address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1007 of 1036 rej09b0254-0600 table a.4 pin status (normal memory/big endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r low low low low low low low rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled e nabled enabled enabled enabled ras high high high high high high high cas high high high high high high high r high high high high high high high we0 /dqmll w high high high low high low low r high high high high high high high we1 /dqmlu/ we w high high low high high low low r high high high high high high high we2 /dqmul/ iciord w high low high high low high low r high high high high high high high we3 /dqmuu/ iciowr w low high high high low high low ce2a high high high high high high high ce2b high high high high high high high cke disabled disabled disabled disabled dis abled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address address addre ss address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data valid data d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switched to port function, pull-up.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1008 of 1036 rej09b0254-0600 table a.5 pin status (burst rom/little endian) 8-bit bus width 16-bit bus width pin byte/word/ longword access byte access (address 2n) byte access (address 2n+1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w ? ? ? ? r high high high high rd/ wr w ? ? ? ? bs enabled enabled enabled enabled ras high high high high cas high high high high r high high high high we0 /dqmll w ? ? ? ? r high high high high we1 /dqmlu/ we w ? ? ? ? r high high high high we2 /dqmul/ iciord w ? ? ? ? r high high high high we3 /dqmuu/ iciowr w ? ? ? ? ce2a high high high high ce2b high high high high cke disabled disabl ed disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabl ed disabled disabled a25 to a0 address a ddress address address d7 to d0 valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1009 of 1036 rej09b0254-0600 table a.5 pin status (burst rom/little endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r low low low low low low low rd w ? ? ? ? ? ? ? r high high high high high high high rd/ wr w ? ? ? ? ? ? ? bs enabled enabled enabled e nabled enabled enabled enabled ras high high high high high high high cas high high high high high high high r high high high high high high high we0 /dqmll w ? ? ? ? ? ? ? r high high high high high high high we1 /dqmlu/ we w ? ? ? ? ? ? ? r high high high high high high high we2 /dqmul/ iciord w ? ? ? ? ? ? ? r high high high high high high high we3 /dqmuu/ iciowr w ? ? ? ? ? ? ? ce2a high high high high high high high ce2b high high high high high high high cke disabled disabled disabled disabled dis abled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address address addre ss address address address address d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switched to port function, pull-up.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1010 of 1036 rej09b0254-0600 table a.6 pin status (burst rom/big endian) 8-bit bus width 16-bit bus width pin byte/word/ longword access byte access (address 2n) byte access (address 2n+1) word/longword access cs6 to cs2 , cs0 enabled enabled enabled enabled r low low low low rd w ? ? ? ? r high high high high rd/ wr w ? ? ? ? bs enabled enabled enabled enabled ras high high high high cas high high high high r high high high high we0 /dqmll w ? ? ? ? r high high high high we1 /dqmlu/ we w ? ? ? ? r high high high high we2 /dqmul/ iciord w ? ? ? ? r high high high high we3 /dqmuu/ iciowr w ? ? ? ? ce2a high high high high ce2b high high high high cke disabled disabl ed disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabl ed disabled disabled a25 to a0 address a ddress address address d7 to d0 valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1011 of 1036 rej09b0254-0600 table a.6 pin status (burst rom/big endian) (cont) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r low low low low low low low rd w ? ? ? ? ? ? ? r high high high high high high high rd/ wr w ? ? ? ? ? ? ? bs enabled enabled enabled e nabled enabled enabled enabled ras high high high high high high high cas high high high high high high high r high high high high high high high we0 /dqmll w ? ? ? ? ? ? ? r high high high high high high high we1 /dqmlu/ we w ? ? ? ? ? ? ? r high high high high high high high we2 /dqmul/ iciord w ? ? ? ? ? ? ? r high high high high high high high we3 /dqmuu/ iciowr w ? ? ? ? ? ? ? ce2a high high high high high high high ce2b high high high high high high high cke disabled disabled disabled disabled dis abled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address address addre ss address address address address d7 to d0 invalid data invalid data invalid data valid data invalid data valid data invalid data d15 to d8 invalid data invalid data valid data invalid data invalid data valid data valid data d23 to d16 invalid data valid data invalid data invalid data valid data invalid data valid data d31 to d24 valid data invalid data invalid data invalid data valid data invalid data valid data notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switched to port function, pull-up.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1012 of 1036 rej09b0254-0600 table a.7 pin status (synch ronous dram/little endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r high high high high high high high rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled e nabled enabled enabled enabled ras low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 cas high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 r low high high high low high low we0 /dqmll w low high high high low high low r high low high high low high low we1 /dqmlu/ we w high low high high low high low r high high low high high low low we2 /dqmul/ iciord w high high low high high low low r high high high low high low low we3 /dqmuu/ iciowr w high high high low high low low ce2a high high high high high high high ce2b high high high high high high high cke high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 wait disabled disabled disabled disabled dis abled disabled disabled iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address command address command address command address command address command address command address command d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. low 32mb access/high 32mb access 2. normally high, but low during self-refresh.
appendix a pin functions rev.6.00 mar. 27 2009 page 1013 of 1036 rej09b0254-0600 table a.8 pin status (synchronous dram/big endian) 32-bit bus width pin byte access (address 4n) byte access (address 4n+1) byte access (address 4n+2) byte access (address 4n+3) word access (address 4n) word access (address 4n+2) longword access cs6 to cs2 , cs0 enabled enabled enabled e nabled enabled enabled enabled r high high high high high high high rd w high high high high high high high r high high high high high high high rd/ wr w low low low low low low low bs enabled enabled enabled e nabled enabled enabled enabled ras low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 low/ high * 1 cas high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 high/ low * 1 r high high high low high low low we0 /dqmll w high high high low high low low r high high low high high low low we1 /dqmlu/ we w high high low high high low low r high low high high low high low we2 /dqmul/ iciord w high low high high low high low r low high high high low high low we3 /dqmuu/ iciowr w low high high high low high low ce2a high high high high high high high ce2b high high high high high high high cke high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 high * 2 wait disabled disabled disabled disabled dis abled disabled disabled iois16 disabled disabled disabled disabled dis abled disabled disabled a25 to a0 address command address command address command address command address command address command address command d7 to d0 valid data invalid data invalid data invalid data valid data invalid data valid data d15 to d8 invalid data valid data invalid data invalid data valid data invalid data valid data d23 to d16 invalid data invalid data valid data invalid data invalid data valid data valid data d31 to d24 invalid data invalid data invalid data valid data invalid data valid data valid data notes: 1. low 32mb access/high 32mb access 2. normally high, but low during self-refresh.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1014 of 1036 rej09b0254-0600 table a.9 pin status (p cmcia/little endian) pcmcia memory interface (area 5) pcmcia/io interface (area 5) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras high high high high high high high high cas high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr w high high high high low low low low ce2a high high low low high high low low ce2b high high high high high high high high cke disabled disabled di sabled disabled disabled di sabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled dis abled disabled disabled enabled enabled a25 to a0 address address address a ddress address addres s address address d7 to d0 valid data valid data invalid data valid data valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1015 of 1036 rej09b0254-0600 table a.9 pin status (pcm cia/little endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras high high high high high high high high cas high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr w high high high high low low low low ce2a high high high high high high high high ce2b high high low low high high low low cke disabled disabled di sabled disabled disabled di sabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled disabled dis abled disabled disabled enabled enabled a25 to a0 address address address a ddress address addres s address address d7 to d0 valid data valid data invalid data valid data valid data valid data invalid data valid data d15 to d8 high-z * 2 invalid data valid data valid data high-z * 2 invalid data valid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switc hed to port function, pull-up.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1016 of 1036 rej09b0254-0600 table a.10 pin status (pcmcia/big endian) pcmcia memory interface (area 5) pcmcia/io interface (area 5) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras high high high high high high high high cas high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr w high high high high low low low low ce2a * 3 high high low low high high low low ce2b * 3 high high high high high high high high cke disabled disabled di sabled disabled disabled di sabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled dis abled disabled disabled di sabled disabled disabled a25 to a0 address address address a ddress address addres s address address d7 to d0 valid data invalid data valid data valid data valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2
appendix a pin functions rev.6.00 mar. 27 2009 page 1017 of 1036 rej09b0254-0600 table a.10 pin status (p cmcia/big endian) (cont) pcmcia memory interface (area 6) pcmcia/io interface (area 6) 8-bit bus width 16-bit bus width 8-bit bus width 16-bit bus width pin byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access byte/ word/ longword access byte access (address 2n) byte access (address 2n+1) word/ longword access cs6 to cs2 , cs0 enabled enabled high enabled enabled enabled high enabled r low low low low high high high high rd w high high high high high high high high r high high high high high high high high rd/ wr w low low low low low low low low bs enabled enabled enabled enabled enabled enabled enabled enabled ras high high high high high high high high cas high high high high high high high high r high high high high high high high high we0 /dqmll w high high high high high high high high r high high high high high high high high we1 /dqmlu/ we w low low low low high high high high r high high high high low low low low we2 /dqmul/ iciord w high high high high high high high high r high high high high high high high high we3 /dqmuu/ iciowr w high high high high low low low low ce2a * 3 high high high high high high high high ce2b * 3 high high low low high high low low cke disabled disabled di sabled disabled disabled di sabled disabled disabled wait enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 enabled * 1 iois16 disabled disabled dis abled disabled disabled di sabled disabled disabled a25 to a0 address address address a ddress address addres s address address d7 to d0 valid data invalid data valid data valid data valid data invalid data valid data valid data d15 to d8 high-z * 2 valid data invalid data valid data high-z * 2 valid data invalid data valid data d31 to d16 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 high-z * 2 notes: 1. disabled when the wait setting of the wcr2 register is 0. 2. unused pins can be switc hed to port function, pull-up. 3. the operation of the ce pin is the sa me as when operating in little endian mode.
appendix a pin functions rev.6.00 mar. 27, 2009 page 1018 of 1036 rej09b0254-0600
appendix b control registers rev.6.00 mar. 27, 2009 page 1019 of 1036 rej09b0254-0600 appendix b control registers b.1 register address map table b.1 memory-mapped control registers (address map) control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 pteh ccn l h'fffffff0 32 32 ptel ccn l h'fffffff4 32 32 ttb ccn l h'fffffff8 32 32 tea ccn l h'fffffffc 32 32 mmucr ccn l h'ffffffe0 32 32 ccr ccn l h'ffffffec 32 32 ccr2 ccn i h'040000b0 32 32 tra ccn l h'ffffffd0 32 32 expevt ccn l h'ffffffd4 32 32 intevt ccn l h'ffffffd8 32 32 basra ccn l h'ffffffe4 8 8 basrb ccn l h'ffffffe8 8 8 bara ubc l h'ffffffb0 32 32 bamra ubc l h'ffffffb4 32 32 bbra ubc l h'ffffffb8 16 16 barb ubc l h'ffffffa0 32 32 bamrb ubc l h'ffffffa4 32 32 bbrb ubc l h'ffffffa8 16 16 bdrb ubc l h'ffffff90 32 32 bdmrb ubc l h'ffffff94 32 32 brcr ubc l h'ffffff98 32 32 betr ubc l h'ffffff9c 16 16 brsr ubc l h'ffffffac 32 32 brdr ubc l h'ffffffbc 32 32 frqcr cpg i2 h'ffffff80 16 16 stbcr cpg i2 h'ffffff82 8 8 stbcr2 cpg i2 h'ffffff88 8 8 wtcnt cpg i2 h'ffffff84 8 16 wtcsr cpg i2 h'ffffff86 8 16
appendix b control registers rev.6.00 mar. 27, 2009 page 1020 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 ckio2cr cpg i2 h'0400023a 8 16 bcr1 bsc i h'ffffff60 16 16 bcr2 bsc i h'ffffff62 16 16 wcr1 bsc i h'ffffff64 16 16 wcr2 bsc i h'ffffff66 16 16 mcr bsc i h'ffffff68 16 16 pcr bsc i h'ffffff6c 16 16 rtcsr bsc i h'ffffff6e 16 16 rtcnt bsc i h'ffffff70 16 16 rtcor bsc i h'ffffff72 16 16 rfcr bsc i h'ffffff74 16 16 sdmr bsc i h'ffffd000? h'ffffefff ? 8 r64cnt rtc p h'fffffec0 8 8 rseccnt rtc p h'fffffec2 8 8 rmincnt rtc p h'fffffec4 8 8 rhrcnt rtc p h'fffffec6 8 8 rwkcnt rtc p h'fffffec8 8 8 rdaycnt rtc p h'fffffeca 8 8 rmoncnt rtc p h'fffffecc 8 8 ryrcnt rtc p h'fffffece 8 8 rsecar rtc p h'fffffed0 8 8 rminar rtc p h'fffffed2 8 8 rhrar rtc p h'fffffed4 8 8 rwkar rtc p h'fffffed6 8 8 rdayar rtc p h'fffffed8 8 8 rmonar rtc p h'fffffeda 8 8 rcr1 rtc p h'fffffedc 8 8 rcr2 rtc p h'fffffede 8 8 icr0 intc i2 h'fffffee0 16 16 ipra intc i2 h'fffffee2 16 16 iprb intc i2 h'fffffee4 16 16 tstr tmu p h'fffffe92 8 8 tcor0 tmu p h'fffffe94 32 32 tcnt0 tmu p h'fffffe98 32 32
appendix b control registers rev.6.00 mar. 27, 2009 page 1021 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 tcr0 tmu p h'fffffe9c 16 16 tcor1 tmu p h'fffffea0 32 32 tcnt1 tmu p h'fffffea4 32 32 tcr1 tmu p h'fffffea8 16 16 tcor2 tmu p h'fffffeac 32 32 tcnt2 tmu p h'fffffeb0 32 32 tcr2 tmu p h'fffffeb4 16 16 scsmr sci p h'fffffe80 8 8 scbrr sci p h'fffffe82 8 8 scscr sci p h'fffffe84 8 8 sctdr sci p h'fffffe86 8 8 scssr sci p h'fffffe88 8 8 scrdr sci p h'fffffe8a 8 8 scscmr sci p h'fffffe8c 8 8 intevt2 intc i2 h'04000000 32 32 irr0 intc i2 h'04000004 16 8 irr1 intc i2 h'04000006 16 8 irr2 intc i2 h'04000008 16 8 icr1 intc i2 h'04000010 16 16 icr2 intc i2 h'04000012 16 16 pinter intc i2 h'04000014 16 16 iprc intc i2 h'04000016 16 16 iprd intc i2 h'04000018 16 16 ipre intc i2 h'0400001a 16 16 sar0 dmac p1 h'04000020 32 16,32 dar0 dmac p1 h'04000024 32 16,32 dmatcr0 dmac p1 h'04000028 32 16,32 chcr0 dmac p1 h'0400002c 32 8,16,32 sar1 dmac p1 h'04000030 32 16,32 dar1 dmac p1 h'04000034 32 16,32 dmatcr1 dmac p1 h'04000038 32 16,32 chcr1 dmac p1 h'0400003c 32 8,16,32 sar2 dmac p1 h'04000040 32 16,32 dar2 dmac p1 h'04000044 32 16,32 dmatcr2 dmac p1 h'04000048 32 16,32
appendix b control registers rev.6.00 mar. 27, 2009 page 1022 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 chcr2 dmac p1 h'0400004c 32 8,16,32 sar3 dmac p1 h'04000050 32 16,32 dar3 dmac p1 h'04000054 32 16,32 dmatcr3 dmac p1 h'04000058 32 16,32 chcr3 dmac p1 h'0400005c 32 8,16,32 dmaor dmac p1 h'04000060 16 8,16 cmstr cmt p1 h'04000070 16 8,16,32 cmcsr cmt p1 h'04000072 16 8,16,32 cmcnt cmt p1 h'04000074 16 8,16,32 cmcor cmt p1 h'04000076 16 8,16,32 addrah a/d p1 h'04000080 8 8,16,32 * 5 * 6 addral a/d p1 h'04000082 8 8,16 * 5 addrbh a/d p1 h'04000084 8 8,16,32 * 5 * 6 addrbl a/d p1 h'04000086 8 8,16 * 5 addrch a/d p1 h'04000088 8 8,16,32 * 5 * 6 addrcl a/d p1 h'0400008a 8 8,16 * 5 addrdh a/d p1 h'0400008c 8 8,16,32 * 5 * 6 addrdl a/d p1 h'0400008e 8 8,16 * 5 adcsr a/d p1 h'04000090 8 8,16,32 * 5 * 6 adcr a/d p1 h'04000092 8 8,16 dadr0 d/a p1 h'040000a0 8 8,16,32 * 5 * 6 dadr1 d/a p1 h'040000a2 8 8,16 * 5 dacr d/a p1 h'040000a4 8 8,16,32 simdr siof p2 h'040000c0 16 16 siscr siof p2 h'040000c2 16 16 sitdar siof p2 h'040000c4 16 16 sirdar siof p2 h'040000c6 16 16 sicdar siof p2 h'040000c8 16 16 sictr siof p2 h'040000cc 16 16 sifctr siof p2 h'040000d0 16 16 sistr siof p2 h'040000d4 16 16 siier siof p2 h'040000d6 16 16 sitdr siof p2 h'040000e0 32 32 sirdr siof p2 h'040000e4 32 32 sitcr siof p2 h'040000e8 32 32
appendix b control registers rev.6.00 mar. 27, 2009 page 1023 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 sircr siof p2 h'040000ec 32 32 pacr port p h'04000100 16 16 pbcr port p h'04000102 16 16 pccr port p h'04000104 16 16 pdcr port p h'04000106 16 16 pecr port p h'04000108 16 16 pfcr port p h'0400010a 16 16 pgcr port p h'0400010c 16 16 phcr port p h'0400010e 16 16 pjcr port p h'04000110 16 16 pkcr port p h'04000112 16 16 plcr port p h'04000114 16 16 scpcr port p h'04000116 16 16 pmcr port p h'04000118 16 16 padr port p h'04000120 8 8 pbdr port p h'04000122 8 8 pcdr port p h'04000124 8 8 pddr port p h'04000126 8 8 pedr port p h'04000128 8 8 pfdr port p h'0400012a 8 8 pgdr port p h'0400012c 8 8 phdr port p h'0400012e 8 8 pjdr port p h'04000130 8 8 pkdr port p h'04000132 8 8 pldr port p h'04000134 8 8 scpdr port p h'04000136 8 8 pmdr port p h'04000138 8 8 reserved ? p h'04000140 ? access prohibited reserved ? p h'04000142 ? access prohibited reserved ? p h'04000144 ? access prohibited reserved ? p h'04000146 ? access prohibited reserved ? p h'04000148 ? access prohibited reserved ? p h'0400014a ? access prohibited reserved ? p h'0400014c ? access prohibited reserved ? p h'0400014e ? access prohibited
appendix b control registers rev.6.00 mar. 27, 2009 page 1024 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 scsmr2 scif p1 h'04000150 8 8 scbrr2 scif p1 h'04000152 8 8 scscr2 scif p1 h'04000154 8 8 scftdr2 scif p1 h'04000156 8 8 scssr2 scif p1 h'04000158 16 16 scfrdr2 scif p1 h'0400015a 8 8 scfcr2 scif p1 h'0400015c 8 8 scfdr2 scif p1 h'0400015e 16 16 pcc0isr pcc p2 h'04000160 8 8 pcc0gcr pcc p2 h'04000162 8 8 pcc0cscr pcc p2 h'04000164 8 8 pcc0cscier pcc p2 h'04000166 8 8 actr1 afe p2 h'04000180 16 16 actr2 afe p2 h'04000182 16 16 astr1 afe p2 h'04000184 16 16 astr2 afe p2 h'04000186 16 16 mrcr afe p2 h'04000188 16 16 mpcr afe p2 h'0400018a 16 16 dpnq afe p2 h'0400018c 16 16 rcnt afe p2 h'0400018e 16 16 acdr afe p2 h'04000190 16 16 asdr afe p2 h'04000192 16 16 tdfp afe p2 h'04000194 16 16/32 rdfp afe p2 h'04000198 16 16/32 sdir h-udi i2 h'04000200 16 16 iprf ppcnt p2 h'04000220 16 16 iprg ppcnt p2 h'04000222 16 16 irr3 ppcnt p2 h'04000224 16 16 irr4 ppcnt p2 h'04000226 16 16 icr3 ppcnr p2 h'04000228 16 16 chrar ppcnt p2 h'0400022a 16 16 reserved ? ? h'0400022c 16 16 reserved ? ? h'0400022e 16 16 stbcr3 ppcnt p2 h'04000230 8 8 srstr ppcnt p2 h'04000232 8 8
appendix b control registers rev.6.00 mar. 27, 2009 page 1025 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 reserved ? p2 h'04000238 16 16 expfc ppcnt p2 h'04000234 16 16 excpgcr ppcnt p2 h'04000236 8 8 usbifr0 usbf p2 h'04000240 8 8 usbifr1 usbf p2 h'04000241 8 8 usbepdr0i usbf p2 h'04000242 8 8 usbepdr0o usbf p2 h'04000243 8 8 usbtrg usbf p2 h'04000244 8 8 usbfclr usbf p2 h'04000245 8 8 usbepsz0o usbf p2 h'04000246 8 8 usbepdr0s usbf p2 h'04000247 8 8 usbdasts usbf p2 h'04000248 8 8 usbepdr2 usbf p2 h'04000249 8 8/32 usbisr0 usbf p2 h'0400024a 8 8 usbepstl usbf p2 h'0400024b 8 8 usbier0 usbf p2 h'0400024c 8 8 usbier1 usbf p2 h'0400024d 8 8 usbepdr1 usbf p2 h'0400024e 8 8/32 usbepsz1 usbf p2 h'0400025f 8 8 usbisr1 usbf p2 h'04000250 8 8 usbdma usbf p2 h'04000251 8 8 usbepdr3 usbf p2 h'04000252 8 8 hcrevision (usbhr) usbh p2 h'04000400 32 32 hccontrol (usbhc) usbh p2 h'04000404 32 32 hccommandstatus (usbhcs) usbh p2 h'04000408 32 32 hcinterruptstatus (usbhis) usbh p2 h'0400040c 32 32 hcinterruptenable (usbhie) usbh p2 h'04000410 32 32 hcinterruptdisable (usbhid) usbh p2 h'04000414 32 32 hchcca (usbhhcca) usbh p2 h'04000418 32 32
appendix b control registers rev.6.00 mar. 27, 2009 page 1026 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 hcperiodcurrented (usbhpced) usbh p2 h'0400041c 32 32 hccontrolheaded (usbhched) usbh p2 h'04000420 32 32 hccontrolcurrented (usbhcced) usbh p2 h'04000424 32 32 hcbulkheaded (usbhbhed) usbh p2 h'04000428 32 32 hcbulkcurrented (usbhbced) usbh p2 h'0400042c 32 32 hcdonehead (usbhdhed) usbh p2 h'04000430 32 32 hcfmlnterval (usbhfi) usbh p2 h'04000434 32 32 hcfmremaining (usbhfr) usbh p2 h'04000438 32 32 hcfmnumber (usbhfn) usbh p2 h'0400043c 32 32 hcperiodstart (usbhps) usbh p2 h'04000440 32 32 hclsthreshold (usbhlst) usbh p2 h'04000444 32 32 hcrhdescriptora (usbhrda) usbh p2 h'04000448 32 32 hcrhdescriptorb (usbhrdb) usbh p2 h'0400044c 32 32 hcrhstatus (usbhrs) usbh p2 h'04000450 32 32 hcrhportstatus1 (usbhrps1) usbh p2 h'04000454 32 32 hcrhportstatus2 (usbhrps2) usbh p2 h'04000458 32 32 ldpr00 to ldprff lcdc p2 h'04000800 to h'04000bfc 32 32 ldickr lcdc p2 h'04000c00 16 16 ldmtr lcdc p2 h'04000c02 16 16 lddfr lcdc p2 h'04000c04 16 16 ldsmr lcdc p2 h'04000c06 16 16 ldsaru lcdc p2 h'04000c08 32 32
appendix b control registers rev.6.00 mar. 27, 2009 page 1027 of 1036 rej09b0254-0600 control register module * 1 bus * 2 address * 4 size (bits) access size (bits) * 3 ldsarl lcdc p2 h'04000c0c 32 32 ldlaor lcdc p2 h'04000c10 16 16 ldpalcr lcdc p2 h'04000c12 16 16 ldhcnr lcdc p2 h'04000c14 16 16 ldhsynr lcdc p2 h'04000c16 16 16 ldvdlnr lcdc p2 h'04000c18 16 16 ldvtlnr lcdc p2 h'04000c1a 16 16 ldvsynr lcdc p2 h'04000c1c 16 16 ldaclnr lcdc p2 h'04000c1e 16 16 ldintr lcdc p2 h'04000c20 16 16 ldmppr lcdc p2 h'04000c24 16 16 ldpspr lcdc p2 h'04000c26 16 16 ldcntr lcdc p2 h'04000c28 16 16 notes: 1. modules ccn: cache controller ubc: user break controller cpg: clock pulse generator bsc: bus state controller rtc: realtime clock intc: interrupt controller tmu: timer unit sci: serial communication interface dmac: direct memory access controller cmt: compare-match timer a/d: a/d converter d/a: d/a converter siof: serial i/o port: port control scif: serial co mmunication interface with fifo pcc: pc card controller afe: analog front end interface h-udi: user-debugging interface ppcnt: peripheral bus interface controller usbf: usb function controller usbh: usb host controller lcdc: lcd controller 2. internal buses: l: cpu, ccn, cache, tlb, and dsp connected i: bsc, cache, dmac, intc, cpg, and udi connected i2: intc, cpg, and h-udi connected p: peripheral modules (rtc, tmu, sci) connected p1: peripheral modules (dmac, cmt, a/d, d/a, port, scif) connected p2: peripheral modules (siof, pcc, af e, ppcnt, usbf, usbh, lcdc) connected 3. the access size shown is for control regi ster access (read/write). an incorrect result will be obtained if a different size from that shown is used for access. 4. to exclude area 1 control registers from address translation by the mmu, set the first 3 bits of the logical address to 101, to locate the registers in the p2 space.
appendix b control registers rev.6.00 mar. 27, 2009 page 1028 of 1036 rej09b0254-0600 5. with 16-bit access, it is not possible to read data in two registers simultaneously. 6. with 32-bit access, it is not possible to read data in the register at [accessed address + 2] simultaneously.
appendix c product lineup rev.6.00 mar. 27, 2009 page 1029 of 1036 rej09b0254-0600 appendix c product lineup table c.1 SH7727 group product lineup power supply voltages abbreviation i/o internal operation frequency model name package 3.3 0.3 v 1.7 to 2.05 v 160 mhz hd6417727f160c 240-pin plastic hqfp (prqp0240kc-b) SH7727 3.3 0.3 v 1.7 to 2.05 v 160 mhz hd6417727bp160c 240-pin csp (plbg0240ja-a) 3.1 0.5 v 1.6 to 2.05 v 100 mhz hd6417727f100c 240-pin plastic hqfp (prqp0240kc-b) 3.1 0.5 v 1.6 to 2.05 v 100 mhz hd6417727bp100c 240-pin csp (plbg0240ja-a)
appendix c product lineup rev.6.00 mar. 27, 2009 page 1030 of 1036 rej09b0254-0600
appendix d package dimensions rev.6.00 mar. 27, 2009 page 1031 of 1036 rej09b0254-0600 appendix d package dimensions the following drawings show the package dimensions of SH7727. prqp0240kc-b p-hqfp240-32x32-0.50 h l e e c a d e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 mass[typ.] 7.0g fp-240b/fp-240bv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 1.25 32 1.25 34.4 34.6 34.8 0.10 0.7 0.5 0.3 0.15 0.20 32 3.20 34.8 34.6 34.4 3.95 0.50 0.40 0.25 0.27 0.22 0.17 0.22 0.17 0.12 0.5 8 0 0.10 1.3 index mark * 1 * 2 * 3 p e d e d xm y f 1 240 61 60 181 180 120 121 d h e h b z z 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure d.1 package dimensions (prqp0240kc-b)
appendix d package dimensions rev.6.00 mar. 27, 2009 page 1032 of 1036 rej09b0254-0600 e a max nom min dimension in millimeters symbol reference a b x y 1 13.00 0.10 0.65 0.35 0.40 0.45 0.28 0.33 0.38 1.40 13.00 0.08 v w 0.65 0.65 y 0.2 1 0.20 0.15 previous code jeita package code renesas code bp-240a/bp-240av 0.4g mass[typ.] e d z z e d z z e d s s e d p-lfbga240-13x13-0.65 plbg0240ja-a 1 1 a a b s s y s wa s wb v s y 1 2345678910111213141516171819 b c d e f g h j k l m n p r t u v w a a e e b a s b m 4 d e figure d.2 package dimensions (plbg0240ja-a)
appendix e using versions previous to the SH7727c rev.6.00 mar. 27, 2009 page 1033 of 1036 rej09b0254-0600 appendix e using versions previous to the SH7727c e.1 determining the version number based on the ma rkings on the chip (1) hqfp-240 package 6417727f sh3-dsp 100 hitachi 0124 bf80128 japan 6417727f sh3-dsp 100 hitachi b 0124 bf80128 japan version previous to SH7727b note: once stocks bearing hitachi markings are exhausted, chips bearing renesas markings may begin to appear. SH7727b "b" indication 6417727f sh3-dsp 100 c 0124 bf80128 SH7727c "c" indication (2) csp-240 package 6417727bp 100 bf80128 0124 japan 6417727bp 100 b bf80128 0124 japan "b" indication version previous to SH7727b SH7727b 6417727bp 100 c bf80128 0124 japan "c" indication SH7727c
appendix e using versions previous to the SH7727c rev.6.00 mar. 27, 2009 page 1034 of 1036 rej09b0254-0600
appendix f using port g control register (pgcr) with versions previous to the SH7727c rev.6.00 mar. 27, 2009 page 1035 of 1036 rej09b0254-0600 appendix f using port g control register (pgcr) with versions previous to the SH7727c bit: 15 14 13 12 11 10 9 8 pg7md1 pg7md0 ? ? pg5md1 pg5md0 pg4md1 pg4md0 initial value: 1 0 1 0 1/0 0 1 0 r/w: r/w r/w r r r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pg3md1 pg3md0 pg2md1 pg2md0 pg1md1 pg1md0 ? pg0md0 initial value: 1/0 0 1/0 0 1/0 0 1/0 0 r/w: r/w r/w r/w r/w r/w r/w r r/w the port g control register (pgcr) is a readable and writeable 16-bit register used to select pin functions. pgcr is initialized to h'aaaa ( asemd0 = 1) or h'a200 ( asemd0 = 0) at power-on reset, but it is not initialized by manual resets or in the standby mode or sleep mode. bits 15, 14: pg7 mode 1, 0 (pg7md1, pg7md0) bits 13, 12: reserved bits 11, 10: pg5 mode 1, 0 (pg5md1, pg5md0) bits 9, 8: pg4 mode 1, 0 (pg4md1, pg4md0) bits 7, 6: pg3 mode 1, 0 (pg3md1, pg3md0) bits 5, 4: pg2 mode 1, 0 (pg2md1, pg2md0) bits 3, 2: pg1 mode 1, 0 (pg1md1, pg1md0) bit 1: reserved bits 3, 0: pg0 mode 1, 0 (pg1md1, pg0md0) these bits are used to select pin functions and input pull-up mos control settings. in the pg1 and pg0 modes, bit 3 (pg1md1) is used to select between ?other function? and ?port input.? when the port input setting is selected (pg1md1 = 1), pull-up mos on-off selection is performed using bit 2 (pg1md0) in the pg1 mode and bit 0 (pg0md0) in the pg0 mode.
appendix f using port g control register (pgcr) with versions previous to the SH7727c rev.6.00 mar. 27, 2009 page 1036 of 1036 rej09b0254-0600 pg0 mode bit 3: pg1md1 bit 0: pg0md0 pin function 0 0 other function (see table 26.1) (initial value) asemd0 = 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) asemd0 = 1 1 port input (pull-up mos: off) pg1 to pg5 and pg7 mode bit (2n + 1): pgnmd1 bit 2n: pgnmd0 pin function 0 0 other function (n = 1, 2, 5) (see table 26.1) (initial value) asemd0 = 0 1 reserved 1 0 port input (pull-up mos: on) (initial value) asemd0 = 1 1 port input (pull-up mos: off) (n = 1, 2, 3, 5) bit (2n + 1): pgnmd1 bit 2n: pgnmd0 pin function 0 0 other function (see table 26.1) (n = 7), reserved (n = 4) 1 reserved 1 0 port input (pull-up mos: on) (initial value) 1 port input (pull-up mos: off) (n = 4, 7)
renesas 32-bit risc microcomputer hardware manual SH7727 group publication date: 1st edition, august 2001 rev.6.00, march 27, 2009 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2009. renesas technology corp., all rights reserved. printed in japan.
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SH7727 group rej09b0254-0600 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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